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  v850e/ma3 32-bit single-chip microcontrollers hardware printed in japan document no. u16397ej3v0ud00 (3rd edition) date published january 2006 n cp(k) user?s manual pd703131a pd 703134a pd703131ay pd 703134ay pd703132a pd 703136a pd703132ay pd 703136ay pd703133a pd 70f3134a pd 703133ay pd70f3134ay ? 2003
user?s manual u16397ej3v0ud 2 [memo]
user?s manual u16397ej3v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6
user?s manual u16397ej3v0ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of september, 2005. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u16397ej3v0ud 5 [memo]
user?s manual u16397ej3v0ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850e/ma3 to design application systems using the v850e/ma3. purpose this manual is intended to give users an understanding of the har dware functions of the v850e/ma3. organization the v850e/ma3 user?s manual is divided into two parts: hardware (this manual) and architecture (v850e1 architecture user?s manual) . the organization of each manual is as follows: hardware architecture ? pin functions ? data type ? cpu function ? register set ? internal peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. ? to find the details of a regi ster where the name is known refer to appendix a register index . ? to understand the details of an instruction function refer to the v850e1 architecture user?s manual . ? to know the electrical spec ifications of the v850e/ma3 refer to chapter 26 electrical specifications . ? to understand the overall f unctions of the v850e/ma3 read this manual according to the contents . ? how to interpret the register format for a bit whose bit number is enclosed in angle brackets < >, its bit name is defined as a reserved word in the device file. the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx. yyy? is described as is in a program, however, the compiler/assembler cannot re cognize it correctly. the mark shows major revised poi nts. the revised points can be easily searched by copying an ?? in the pdf file and specifying it in the ?find what:? field.
user?s manual u16397ej3v0ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresse s on the top and lower addresses on the bottom note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 data type: word ... 32 bits halfword ... 16 bits byte ... 8 bits
user?s manual u16397ej3v0ud 8 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850e/ma3 document name document no. v850e1 architecture user?s manual u14559e v850e/ma3 hardware user?s manual this manual v850e/ma1, v850e/ma2, v850e/ma3, v850e/me2 pci host bridge macro application note u17121e inverter control by v850 series 120 excitation method control by ze ro-cross detection application note u17209e inverter control by v850 series vector cont rol by hole sensor application note u17338e documents related to developm ent tools (user?s manuals) document name document no. ie-v850e1-cd-nw (pcmcia card ty pe on-chip debug emulator) u16647e operation u17293e c language u17291e assembly language u17292e ca850 (ver. 3.00) (c compiler package) link directive u17294e pm+ (ver. 6.00) (project manager) u17178e id850 (ver. 3.00) (integrated debugger) operation u17358e id850nw (ver. 3.00, 3.10) (integrated debugger) operation u17369e id850nwc (ver. 2.51) (integrated debugger) operation u16525e tw850 (ver. 2.00) (performanc e analysis tuning tool) u17241e basics u13430e installation u17419e technical u13431e rx850 (ver. 3.20) (real-time os) task debugger u17420e basics u13773e installation u17421e technical u13772e rx850 pro (ver. 3.20) (real-time os) task debugger u17422e az850 (ver. 3.30) (system performance analyzer) u17423e pg-fp4 flash memory programmer u15260e
user?s manual u16397ej3v0ud 9 contents chapter 1 introduction ...................................................................................................... .........20 1.1 overview ....................................................................................................................... ...........20 1.2 features ....................................................................................................................... ............22 1.3 applications ................................................................................................................... .........24 1.4 ordering information ........................................................................................................... ...24 1.5 pin configuration.............................................................................................................. ......25 1.6 function blocks ................................................................................................................ ......30 1.6.1 internal bl ock di agram ......................................................................................................... ......30 1.6.2 internal units................................................................................................................. .............31 chapter 2 pin functions .................................................................................................... ..........34 2.1 list of pin functions .......................................................................................................... ....34 2.2 pin status ..................................................................................................................... ...........44 2.3 pin i/o circuits and recommended connection of unused pins .....................................45 2.4 pin i/o circuits ............................................................................................................... .........49 chapter 3 cpu function..................................................................................................... ..........50 3.1 features ....................................................................................................................... ............50 3.2 cpu register set ............................................................................................................... .....51 3.2.1 program regi ster set........................................................................................................... .......52 3.2.2 system regi ster set ............................................................................................................ .......53 3.3 operating modes................................................................................................................ .....59 3.3.1 operating modes................................................................................................................ .......59 3.3.2 operating mode specific ation................................................................................................... .59 3.4 address space .................................................................................................................. ......60 3.4.1 cpu addre ss space .............................................................................................................. ....60 3.4.2 image .......................................................................................................................... ..............61 3.4.3 wraparound of cpu address s pace..........................................................................................62 3.4.4 memory map ..................................................................................................................... ........63 3.4.5 area ........................................................................................................................... ...............64 3.4.6 external memo ry expans ion...................................................................................................... 68 3.4.7 recommended use of address s pace.......................................................................................68 3.4.8 on-chip periphera l i/o registers ............................................................................................... .70 3.4.9 special re gisters.............................................................................................................. ..........81 3.4.10 system wait control register (vswc) ........................................................................................84 3.4.11 cautio ns ....................................................................................................................... .............84 chapter 4 port functions ................................................................................................... .......86 4.1 features ....................................................................................................................... ............86 4.2 port basic configuration....................................................................................................... .87 4.3 port configuratio n ............................................................................................................. .....88 4.3.1 port 0 ......................................................................................................................... ...............92 4.3.2 port 1 ......................................................................................................................... .............101 4.3.3 port 2 ......................................................................................................................... .............107
user?s manual u16397ej3v0ud 10 4.3.4 port 3......................................................................................................................... ..............118 4.3.5 port 4......................................................................................................................... ..............129 4.3.6 port 5......................................................................................................................... ..............135 4.3.7 port 7......................................................................................................................... ..............139 4.3.8 port 8......................................................................................................................... ..............142 4.3.9 port al ........................................................................................................................ ............144 4.3.10 port ah........................................................................................................................ ............148 4.3.11 port dl ........................................................................................................................ ............151 4.3.12 port cs........................................................................................................................ ............155 4.3.13 port ct ........................................................................................................................ ............160 4.3.14 port cm ........................................................................................................................ ...........165 4.3.15 port cd........................................................................................................................ ............170 4.3.16 port bd........................................................................................................................ ............174 4.4 setting to use alternate function of port pin....... ............................................................ 177 4.5 noise eliminator ............................................................................................................... .... 187 4.5.1 interrupt in put pin ............................................................................................................ ........187 4.5.2 timer enc1 input pins .......................................................................................................... ..188 4.5.3 timer p and timer q input pins................................................................................................1 88 4.6 cautions ....................................................................................................................... ......... 189 4.6.1 cautions on se tting port pins .................................................................................................. .189 4.6.2 cautions on bit manipulation instruct ion for port n r egister (pn) ..............................................190 4.6.3 hysteresis char acterist ics..................................................................................................... ...191 chapter 5 bus control function ........................................................................................ 192 5.1 features ....................................................................................................................... ......... 192 5.2 bus control pins ............................................................................................................... ... 192 5.2.1 pin status when internal rom, internal ra m, or on-chip peripher al i/o is a ccessed ..............195 5.3 memory block function ...................................................................................................... 196 5.3.1 chip select co ntrol f unction ................................................................................................... ..197 5.4 bus cycle type control function ................................ ...................................................... 200 5.4.1 bus cycle type configur ation registers 0, 1 (bct0, bct1) .......................................................200 5.4.2 chip select signal delay control regist er (cs dc)..................................................................... 202 5.5 bus access ..................................................................................................................... ...... 204 5.5.1 number of cloc ks for a ccess ...................................................................................................2 04 5.5.2 bus sizing functi on ............................................................................................................ ......204 5.5.3 endian contro l func tion ........................................................................................................ ....205 5.5.4 restrictions on big endianness with nec electronics devel opment t ools ...............................206 5.5.5 bus wid th...................................................................................................................... ...........208 5.6 write buffer function .......................................................................................................... 219 5.7 bus clock control function................................................................................................ 221 5.8 wait function.................................................................................................................. ...... 222 5.8.1 programmable wait function ....................................................................................................2 22 5.8.2 external wait function ......................................................................................................... .....228 5.8.3 relationship between programmable wait a nd external wait...................................................228 5.8.4 bus cycle for which wait function is valid .................................................................................229 5.9 idle state insertion function............................................ ................................................... 230 5.10 bus hold function .............................................................................................................. . 232 5.10.1 functional outline ............................................................................................................. .......232
user?s manual u16397ej3v0ud 11 5.10.2 bus hold pr ocedure ............................................................................................................. ....233 5.10.3 operation in powe r save mode ...............................................................................................233 5.10.4 bus hold timing................................................................................................................ ........234 5.10.5 bus hold timi ng (sram) ......................................................................................................... .235 5.10.6 bus hold timing (sdra m) .......................................................................................................2 37 5.11 bus priority................................................................................................................... .........241 5.12 boundary operation conditions .................. .......................................................................242 5.12.1 program space.................................................................................................................. ......242 5.12.2 data s pace ..................................................................................................................... .........242 chapter 6 memory access control function ...............................................................243 6.1 sram, external rom, external i/o interface......................................................................243 6.1.1 featur es ....................................................................................................................... ...........243 6.1.2 sram conn ecti on ................................................................................................................ ...244 6.1.3 sram, external rom, external i/o access .............................................................................246 6.2 page rom controller (romc) .............................................................................................263 6.2.1 featur es ....................................................................................................................... ...........263 6.2.2 page rom co nnecti on ............................................................................................................ 264 6.2.3 on-page ........................................................................................................................ ..........265 6.2.4 page rom configurati on register (prc) .................................................................................265 6.2.5 page rom access ................................................................................................................ ..266 6.3 dram controller (sdram) ..................................................................................................269 6.3.1 featur es ....................................................................................................................... ...........269 6.3.2 sdram con nection............................................................................................................... ..269 6.3.3 address multip lex func tion ..................................................................................................... .270 6.3.4 sdram configuration regist ers 1, 3, 4, 6 (scr1, scr3, scr4 , scr6 ).................................275 6.3.5 sdram a ccess ................................................................................................................... ....277 6.3.6 refresh contro l func tion ....................................................................................................... ...298 6.3.7 self-refresh cont rol function .................................................................................................. ..302 6.3.8 sdram initializa tion seque nce ...............................................................................................304 chapter 7 clock generator .................................................................................................. .306 7.1 overview ....................................................................................................................... .........306 7.2 configuration .................................................................................................................. ......306 7.3 control registers.............................................................................................................. ....308 7.4 operation ...................................................................................................................... .........313 7.4.1 operation of each cl ock ........................................................................................................ ..313 7.4.2 external clock input function.................................................................................................. ..313 7.5 pll function ................................................................................................................... ......314 7.5.1 overvi ew ....................................................................................................................... ..........314 7.5.2 selecting syst em clock......................................................................................................... ...314 7.5.3 pll mode....................................................................................................................... .........315 7.5.4 clock-throug h m ode............................................................................................................. ...315 chapter 8 16-bit timer/event counter p (tmp) ...............................................................316 8.1 overview ....................................................................................................................... .........316 8.2 functions ...................................................................................................................... .........316
user?s manual u16397ej3v0ud 12 8.3 configuration.................................................................................................................. ...... 317 8.4 registers ...................................................................................................................... ......... 319 8.5 timer output operations..................................................................................................... 331 8.6 operation ...................................................................................................................... ........ 332 8.6.1 interval timer mode (tpnmd2 to tpnmd0 bi ts = 000)............................................................. 339 8.6.2 external event count mode (tpn md2 to tpnmd0 bits = 001).................................................350 8.6.3 external trigger pulse output mode (tpnmd2 to tpnmd0 bits = 010) .....................................358 8.6.4 one-shot pulse output mode (tpnmd 2 to tpnmd0 bi ts = 01 1) .............................................. 370 8.6.5 pwm output mode (tpnmd2 to tpnmd0 bi ts = 100).............................................................. 377 8.6.6 free-running timer mode (tpnmd 2 to tpnmd0 bits = 101) .................................................... 386 8.6.7 pulse width measurement mode (tpn md2 to tpnmd0 bits = 110) ........................................ 403 chapter 9 16-bit timer/event counter q (tmq ).............................................................. 409 9.1 overview ....................................................................................................................... ........ 409 9.2 functions ...................................................................................................................... ........ 409 9.3 configuration.................................................................................................................. ...... 410 9.4 registers ...................................................................................................................... ......... 413 9.5 timer output operations..................................................................................................... 428 9.6 operation ...................................................................................................................... ........ 429 9.6.1 interval timer mode (tq0md2 to tq0md0 bi ts = 000)............................................................ 436 9.6.2 external event count mode (tq0 md2 to tq0md0 bits = 001) ................................................447 9.6.3 external trigger pulse output mode (tq0md2 to tq0md0 bits = 010) ....................................456 9.6.4 one-shot pulse output mode (tq0 md2 to tq0md0 bits = 011) ............................................. 469 9.6.5 pwm output mode (tq0md2 to tq0md0 bi ts = 100)............................................................. 478 9.6.6 free-running timer mode (tq0md2 to tq0md0 bi ts = 101 ) ...................................................489 9.6.7 pulse width measurement mode (tq0 md2 to tq0md0 bits = 110) ....................................... 509 chapter 10 16-bit interval timer d (tmd) ......................................................................... 515 10.1 features ....................................................................................................................... ......... 515 10.2 function overview .............................................................................................................. . 515 10.3 configuration.................................................................................................................. ...... 516 10.3.1 timers d0 to d3 (tmd0 to tmd3) ..........................................................................................517 10.3.2 compare registers d0 to d3 (cmd0 to cmd3 ) .......................................................................518 10.4 control registers .............................................................................................................. ... 520 10.5 operation ...................................................................................................................... ........ 521 10.5.1 compare op eration.............................................................................................................. ....521 10.6 application examples.......................................................................................................... 5 23 10.7 cautions ....................................................................................................................... ......... 523 chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) .............................................. 524 11.1 functions ...................................................................................................................... ........ 524 11.2 features ....................................................................................................................... ......... 524 11.3 configuration.................................................................................................................. ...... 525 11.4 control registers .............................................................................................................. ... 528 11.5 operation ...................................................................................................................... ........ 537 11.5.1 operation in general-p urpose time r mode ...............................................................................537
user?s manual u16397ej3v0ud 13 11.5.2 operation in udc mode .......................................................................................................... 540 11.6 supplementary description of internal operation .... ........................................................546 11.6.1 clearing of count val ue in udc mode b ..................................................................................546 11.6.2 transfer oper ation............................................................................................................. ......547 11.6.3 interrupt request signal ou tput upon compar e match ..............................................................548 11.6.4 ubd10 flag (bit 0 of status 10 register) o peratio n................................................................548 chapter 12 motor control function .................................................................................549 12.1 functional overview............................................................................................................ .549 12.2 configuration .................................................................................................................. ......550 12.3 control registers.............................................................................................................. ....554 12.4 operation ...................................................................................................................... .........564 12.4.1 system outline................................................................................................................. ........564 12.4.2 dead-time control (generation of negative-phase wa ve sign al)...............................................569 12.4.3 interrupt cull ing func tion ..................................................................................................... .....576 12.4.4 operation to rewrit e register with tr ansfer func tion ..................................................................583 12.4.5 tmp2 tuning operation for a/d conver sion start trigger signal out put .....................................601 12.4.6 a/d conversion start tri gger output functi on ............................................................................ 604 chapter 13 watchdog timer functions .............................................................................609 13.1 functions ...................................................................................................................... .........609 13.2 configuration .................................................................................................................. ......610 13.3 control registers.............................................................................................................. ....610 13.4 operation ...................................................................................................................... .........613 13.4.1 operation as wa tchdog ti mer ..................................................................................................61 3 13.4.2 operation as in terval timer .................................................................................................... ..614 chapter 14 a/d converter ................................................................................................... .....615 14.1 features ....................................................................................................................... ..........615 14.2 configuration .................................................................................................................. ......616 14.3 control registers.............................................................................................................. ....619 14.4 operation ...................................................................................................................... .........627 14.4.1 basic oper ation ................................................................................................................ .......627 14.4.2 operation mode and trigger mode ..........................................................................................628 14.5 operation in software trigger mode........................... ........................................................632 14.5.1 select mode operation .......................................................................................................... ..632 14.5.2 scan mode op eratio ns ........................................................................................................... .634 14.6 operation in timer trigger mode ........................................................................................635 14.6.1 select mode operation .......................................................................................................... ..636 14.6.2 scan mode op eration ............................................................................................................ ..638 14.7 operation in external trigger mode......................... ...........................................................641 14.7.1 select mode operat ions ......................................................................................................... .641 14.7.2 scan mode op eration ............................................................................................................ ..643 14.8 notes on operation............................................................................................................. ..645 14.8.1 stopping conversi on operatio n................................................................................................64 5 14.8.2 timer/external tr igger in terval................................................................................................ ..645 14.8.3 operation in st andby m ode .....................................................................................................6 45
user?s manual u16397ej3v0ud 14 14.8.4 timer interrupt request signa l in timer tr igger m ode ................................................................ 646 14.8.5 a/d conversi on time ............................................................................................................ ....646 14.8.6 stabilizatio n time ............................................................................................................. ........647 14.8.7 variation of a/d c onversion re sults .........................................................................................647 14.9 how to read a/d converter charac teristics table........................................................... 648 chapter 15 d/a converter ................................................................................................... .... 652 15.1 functions ...................................................................................................................... ........ 652 15.2 configuration.................................................................................................................. ...... 652 15.3 control registers .............................................................................................................. ... 653 15.4 operation ...................................................................................................................... ........ 655 15.4.1 operation in normal mode ....................................................................................................... 655 15.4.2 operation in real-t ime output mode .........................................................................................655 15.4.3 cautio ns ....................................................................................................................... ...........656 chapter 16 asynchronous serial interface a (uarta) ........................................... 657 16.1 mode switching between uarta and other serial interface ......................................... 657 16.1.1 mode switching between uarta0 and csib0, uarta1 and csib1, and uarta2 a nd csib 2 .........................................................................................................65 7 16.1.2 uarta3/i 2 c mode swit ching ...................................................................................................660 16.2 features ....................................................................................................................... ......... 661 16.3 configuration.................................................................................................................. ...... 662 16.4 control registers .............................................................................................................. ... 664 16.5 interrupt request si gnals ................................................................................................... 669 16.6 operation ...................................................................................................................... ........ 670 16.6.1 data fo rmat.................................................................................................................... ..........670 16.6.2 uart trans mission .............................................................................................................. ...672 16.6.3 continuous transmi ssion proc edure ........................................................................................673 16.6.4 uart rec eption................................................................................................................. ......675 16.6.5 reception errors............................................................................................................... .......676 16.6.6 parity types and operat ions .................................................................................................... .677 16.6.7 receive data no ise f ilter ...................................................................................................... ....678 16.7 dedicated baud rate generator ......................................................................................... 679 16.8 cautions ....................................................................................................................... ......... 686 chapter 17 clocked serial interface b (csib)............................................................. 687 17.1 mode switching between csib and other serial interface ............................................. 687 17.1.1 mode switching between uarta0 and csib0, uarta1 and csib1, and uarta2 a nd csib 2 .........................................................................................................68 7 17.2 features ....................................................................................................................... ......... 687 17.3 configuration.................................................................................................................. ...... 690 17.4 control registers .............................................................................................................. ... 692 17.5 operation ...................................................................................................................... ........ 699 17.5.1 single transfer mode (master mode, transmi ssion mo de) ....................................................... 699 17.5.2 single transfer mode (master mode, recept ion m ode) ............................................................ 701 17.5.3 single transfer mode (master mode, transmission/rec eption m ode) ....................................... 703 17.5.4 single transfer mode (slave m ode, transmissi on mode )..........................................................705
user?s manual u16397ej3v0ud 15 17.5.5 single transfer mode (slave mode, recept ion m ode)............................................................... 707 17.5.6 single transfer mode (slave mode, transmission/rece ption m ode).......................................... 709 17.5.7 continuous transfer mode (master mode, transmissi on mode )...............................................711 17.5.8 continuous transfer mode (mas ter mode, rec eption m ode) .................................................... 713 17.5.9 continuous transfer mode (master m ode, transmission/r eception mode) ...............................716 17.5.10 continuous transfer mode (slave mode, transmi ssion mode ) .................................................720 17.5.11 continuous transfer mode (sla ve mode, rec eption m ode)....................................................... 722 17.5.12 continuous transfer mode (slave mo de, transmission/rece ption mo de)..................................725 17.5.13 reception error ................................................................................................................ .......729 17.5.14 clock ti ming................................................................................................................... ..........730 17.6 output pins.................................................................................................................... ........732 chapter 18 i 2 c bus......................................................................................................................... 733 18.1 uarta3/i 2 c mode switching ...............................................................................................734 18.2 features ....................................................................................................................... ..........735 18.3 configuration .................................................................................................................. ......738 18.4 registers...................................................................................................................... ..........740 18.5 functions ...................................................................................................................... .........756 18.5.1 pin confi guratio n .............................................................................................................. .......756 18.6 i 2 c bus definitions and control methods................ ...........................................................757 18.6.1 start c onditi on ................................................................................................................ .........757 18.6.2 addres ses ...................................................................................................................... .........758 18.6.3 transfer direction specification............................................................................................... .759 18.6.4 ack............................................................................................................................ .............760 18.6.5 stop cond ition ................................................................................................................. ........761 18.6.6 wait........................................................................................................................... ..............762 18.6.7 wait state cance llation me thod ...............................................................................................76 4 18.7 i 2 c interrupt request signals (intiic)......................... ........................................................765 18.7.1 master devic e operat ion ........................................................................................................ ..765 18.7.2 slave device operation (when receivin g slave address (match with addres s))........................768 18.7.3 slave device operation (when receiving exte nsion c ode)........................................................ 772 18.7.4 operation without communica tion ...........................................................................................776 18.7.5 arbitration loss operation (operation as slave after ar bitration loss) ........................................776 18.7.6 operation when arbitr ation loss occurs (no communicati on after arbitr ation loss) ..................778 18.8 interrupt request signal (intiic) generation timi ng and wait control .........................785 18.9 address match detection method............. ..........................................................................786 18.10 error detection................................................................................................................ ......786 18.11 extension code................................................................................................................. ....787 18.12 arbitration.................................................................................................................... ..........788 18.13 wakeup function ................................................................................................................ ..789 18.14 communication reservation ...............................................................................................790 18.14.1 when communication reservation function is enabled (iicf. iicrsv bit = 0) ..........................790 18.14.2 when communication reservation function is disabled (iicf. iicrsv bit = 1)..........................794 18.15 cautions....................................................................................................................... ..........795 18.16 communication operations.................................................................................................796 18.16.1 master operation in si ngle master system ...............................................................................797 18.16.2 master operation in multimaste r system ..................................................................................798 18.16.3 slave oper ation ................................................................................................................ .......801
user?s manual u16397ej3v0ud 16 18.17 timing of data communication .......................................................................................... 804 chapter 19 dma functions (dma controller) ............................................................... 811 19.1 features ....................................................................................................................... ......... 811 19.2 configuration.................................................................................................................. ...... 812 19.3 control registers .............................................................................................................. ... 813 19.3.1 dma source address registers 0 to 3 (dsa0 to dsa3 ) ...........................................................813 19.3.2 dma destination address register s 0 to 3 (dda 0 to dda 3) .................................................... 815 19.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3 )..............................................................817 19.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc 3) .................................................818 19.3.5 dma channel control register s 0 to 3 (dchc 0 to dchc3 )......................................................820 19.3.6 dma terminal count output c ontrol register (dtoc)................................................................822 19.3.7 dma trigger factor registers 0 to 3 (dtfr0 to dtfr 3) ........................................................... 823 19.3.8 dma interface control register (difc) .....................................................................................826 19.3.9 dmaak width control re gister (d akw)....................................................................................827 19.4 transfer modes................................................................................................................. .... 828 19.4.1 single trans fer m ode ........................................................................................................... ....828 19.4.2 single-step tran sfer mode ...................................................................................................... .830 19.4.3 block trans fer m ode ............................................................................................................ ....831 19.5 transfer types................................................................................................................. ..... 832 19.5.1 2-cycle tr ansfer............................................................................................................... .........832 19.5.2 flyby tr ansfer................................................................................................................. ..........849 19.6 transfer object................................................................................................................ ..... 853 19.6.1 transfer type and tr ansfer ob ject.............................................................................................8 53 19.6.2 external bus cycles dur ing dma tr ansfer .................................................................................854 19.7 dma channel priorities ....................................................................................................... 85 5 19.8 next address setting function..................................... ...................................................... 856 19.9 dma transfer start factors ................................................................................................ 857 19.10 terminal count output u pon dma transfer end.................. ............................................ 858 19.11 forcible interruption .......................................................................................................... .. 859 19.12 forcible termination........................................................................................................... . 860 19.13 times related to dma transfer.......................................................................................... 861 19.14 maximum response time for dma tr ansfer request ..................................................... 862 19.15 cautions ....................................................................................................................... ......... 863 19.15.1 suspension factors ............................................................................................................. .....863 19.16 dma transfer end ............................................................................................................... . 863 chapter 20 interrupt/exception processing function............................................. 864 20.1 features ....................................................................................................................... ......... 864 20.2 non-maskable interrupt s ..................................................................................................... 868 20.2.1 operation...................................................................................................................... ...........870 20.2.2 restore........................................................................................................................ ............871 20.2.3 non-maskable interrupt status fl ag (np) ..................................................................................872 20.3 maskable interrupts ............................................................................................................ . 873 20.3.1 operation...................................................................................................................... ...........873 20.3.2 restore........................................................................................................................ ............875 20.3.3 priorities of ma skable inte rrupts .............................................................................................. 876
user?s manual u16397ej3v0ud 17 20.3.4 interrupt control r egister ( xxlcn)............................................................................................. .880 20.3.5 interrupt mask registers 0 to 3 (imr0 to imr3 ) .......................................................................883 20.3.6 in-service priority register (ispr) ............................................................................................ 884 20.3.7 maskable interrupt st atus flag (id) ..........................................................................................88 4 20.4 external interrupt request inpu pi ns (nmi, intpn)...........................................................885 20.4.1 noise elim ination.............................................................................................................. .......885 20.4.2 edge dete ction ................................................................................................................. .......885 20.5 software exception............................................................................................................. ..892 20.5.1 operation ...................................................................................................................... ..........892 20.5.2 restore ........................................................................................................................ ...........893 20.5.3 exception stat us flag (ep) ..................................................................................................... ..894 20.6 exception trap ................................................................................................................. .....895 20.6.1 illegal opcode ................................................................................................................. .........895 20.6.2 debug trap ..................................................................................................................... .........897 20.7 multiple interrupt servicing contro l ...................................................................................899 20.8 interrupt latency time ......................................................................................................... 901 20.9 periods in which cpu does not acknowledge interr upts ...............................................902 20.10 cautions....................................................................................................................... ..........902 chapter 21 standby function ................................................................................................ .903 21.1 overview ....................................................................................................................... .........903 21.2 control registers.............................................................................................................. ....905 21.3 halt mode ...................................................................................................................... ......906 21.3.1 setting and oper ation status................................................................................................... .906 21.3.2 releasing ha lt mode ............................................................................................................ 906 21.4 idle mode ...................................................................................................................... .......908 21.4.1 setting and oper ation status................................................................................................... .908 21.4.2 releasing id le mode ............................................................................................................ .908 21.5 software stop mode............................................................................................................9 10 21.5.1 setting and oper ation status................................................................................................... .910 21.5.2 releasing softwar e stop mode .............................................................................................910 21.6 securing oscillation stabilization time ..................... ........................................................912 21.7 procedure for setting and restoring from idle and software stop m odes ................913 chapter 22 reset functions................................................................................................. ...915 22.1 overview ....................................................................................................................... .........915 22.2 configuration .................................................................................................................. ......915 22.3 control register............................................................................................................... .....916 22.4 operation ...................................................................................................................... .........917 chapter 23 rom correction function................................................................................919 23.1 overview ....................................................................................................................... .........919 23.2 control registers.............................................................................................................. ....920 23.3 rom correction operation and program flow.......... ........................................................921 chapter 24 on-chip debug function (dcu)........................................................................923
user?s manual u16397ej3v0ud 18 24.1 function overview .............................................................................................................. . 923 24.1.1 on-chip deb ug unit type ........................................................................................................ ..923 24.1.2 debug f unction ................................................................................................................. .......923 24.1.3 rom security function .......................................................................................................... ...925 24.2 selecting on-chip debug function and port function (including al ternate functions)927 24.3 connection with n-wire type emulator ...................... ...................................................... 928 24.3.1 kel conn ector.................................................................................................................. .......928 24.3.2 amp connec tor.................................................................................................................. ......931 24.4 cautions ....................................................................................................................... ......... 935 chapter 25 flash memory .................................................................................................... .... 936 25.1 features ....................................................................................................................... ......... 936 25.2 writing with flash programmer.................................... ...................................................... 936 25.3 programming environment................................................................................................. 943 25.4 communication mode.......................................................................................................... 944 25.5 pin connection ................................................................................................................. .... 947 25.5.1 mode1 pin...................................................................................................................... ........947 25.5.2 serial inte rface pins .......................................................................................................... .......948 25.5.3 reset pin...................................................................................................................... .........950 25.5.4 nmi pin ........................................................................................................................ ............951 25.5.5 mode0, mode 1 pins .............................................................................................................9 51 25.5.6 port pins ...................................................................................................................... ............952 25.5.7 other signa l pi ns .............................................................................................................. .......952 25.5.8 power su pply................................................................................................................... ........952 25.6 programming method .......................................................................................................... 952 25.6.1 flash memory cont rol ........................................................................................................... ...952 25.6.2 flash memory pr ogramming mode ..........................................................................................953 25.6.3 selection of comm unication mode...........................................................................................953 25.6.4 communication command s .....................................................................................................954 25.6.5 turning o ff pow er .............................................................................................................. ......955 chapter 26 electrical specifications ............................................................................... 956 26.1 normal operation mode ...................................................................................................... 956 26.2 power-on/off sequence ...................................................... .............................................. 1003 26.3 flash memory programming mode ( pd70f3134a, 70f3134ay only) ........................ 1004 chapter 27 package drawings ...................................... ...................................................... 1006 chapter 28 recommended soldering conditio ns....................................................... 1008 appendix a register index .................................................................................................. ... 1010 appendix b instruction set list ......................................................................................... 10 19 b.1 conventions.................................................................................................................... .... 1019 b.2 instruction set (in alphabetical order) ...................... ...................................................... 1022
user?s manual u16397ej3v0ud 19 appendix c revision history ................................................................................................ ..1029 c.1 major revisions in this edition .................................. ......................................................1029 c.2 revision history of preceding editions .................. .........................................................1034
20 user?s manual u16397ej3v0ud chapter 1 introduction the v850e/ma3 is a product of the nec electronics v850 se ries of single-chip microcontrollers. this chapter gives a simple outline of the v850e/ma3. 1.1 overview the v850e/ma3 is a 32-bit single-chip microcontroller that integrates the v850e1 cp u, which is a 32-bit risc- type cpu core for asic, newly developed as the cpu core central to system lsi for the current age of system-on- chip. this device incorporates rom, ram, and various peripheral functions such as memory controllers, a dma controller, timers/counters, serial interfaces, an a/d c onverter, a d/a converter, rom correction, and on-chip debugging for realizing high-capacity data proc essing and sophisticated real-time control. (1) v850e1 cpu the v850e1 cpu is a cpu core that enhances the ex ternal bus interface performance of the v850 cpu, which is the cpu core integrated in the v850 series , and has added instructions supporting high-level languages, such as c-language s witch statement processing, tabl e lookup branching, stack frame creation/deletion, and data conversion. this enhances the performance of both data processing and control. it is possible to use the software resources of the v850 cpu integrated system since the instruction codes of the v850e1 are upwardly compatible at the obj ect code level with those of the v850 cpu. (2) external memory interface function the v850e/ma3 features various on-chip external memo ry interfaces including separately configured address (26-bit) and multiplex configured address/data (16-bi t) buses, and sdram and rom interfaces, as well as on- chip memory controllers that can be directly linked to page rom, etc., thereby raising system performance and reducing the number of parts needed for application systems. also, through the dma controller, cpu internal calculations and data transfers can be performed simultaneously with transfers to and from the external memory, so it is possible to process large volumes of image data or voice data, etc., and through high-speed execut ion of instructions using internal rom and ram, motor control, communications control and other r eal-time control tasks can be realized simultaneously. (3) on-chip flash memory (flash memo ry versions only (see table 1-1)) the on-chip flash memory versions have on-chip flash memory, which is capable of high-speed access, and since it is possible to rewrite a pr ogram with the v850e/ma3 mounted as is in the application system, system development time can be reduced a nd system maintainability after sh ipment can be markedly improved.
chapter 1 introduction user?s manual u16397ej3v0ud 21 (4) a full range of middleware and development environment products the v850e/ma3 can execute middleware such as jpeg, jbig, and mh/mr/mmr at high speed. also, middleware that enables speech recognition, voice synth esis, and other such processing is available, and by including these middleware programs, a mu ltimedia system can be easily realized. a development environment system that includes an optimized c compiler, debugger, in-circuit emulator, simulator, system performance analyzer, an d other elements is also available. the following shows the v850e/ma3 product list. table 1-1. v850e/ma3 product list rom maskable interrupts function part number type size ram size i 2 c bus external internal non-maskable interrupts pd703131a none 49 pd703131ay 16 kb on-chip 50 pd703132a none 49 pd703132ay 256 kb 32 kb on-chip 50 pd703133a none 49 pd703133ay 16 kb on-chip 50 pd703134a none 49 pd703134ay 512 kb 32 kb on-chip 50 pd703136a none 49 pd703136ay mask rom 256 kb 8 kb on-chip 50 pd70f3134a none 49 pd70f3134ay flash memory 512 kb 32 kb on-chip 25 50 2 remark the part numbers of the v850e/ma3 are shown as follows in this manual. ? mask rom version pd703131a, 703131ay, 703132a, 703132ay, 703133a, 703133ay, 703134a, 703134ay, 703136a, 703136ay ? flash memory version pd70f3134a, 70f3134ay ? i 2 c bus version (y version) pd703131ay, 703132ay, 703133ay, 703134ay, 703136ay, 70f3134ay
chapter 1 introduction user?s manual u16397ej3v0ud 22 1.2 features { minimum instruction execution time: 12.5 ns (at internal 80 mhz operation) { general-purpose registers: 32 bits 32 { cpu features: multiplication instruction (16 bits 16 bits 32 bits): 1 to 2 clocks multiplication instruction (32 bits 32 bits 64 bits): 1 to 2 clocks saturated operation instructions (wit h overflow/underflow detection function) 32-bit shift instructions: 1 clock bit manipulation instructions load/store instructions with long/short format signed load instructions { memory space: 256 mb of linear address space (common program/data use) chip select output function: 8 spaces memory block division function: 2, 64 mb/block ? internal memory: ram: 8/16/32 kb (see table 1-1 ) mask rom: 256/512 kb (see table 1-1 ) flash memory: 512 kb (see table 1-1 ) ? external bus interface: separat e bus/multiplexed bus output selectable 8-/16-bit data bus sizing function external bus division function: divided by 1, 2, 3, 4 (50 mhz max.) wait function  programmable wait function  external wait function idle state function bus hold function address setup wait function endian control function ? memory access controller dram controller (compatible with sdram) page rom controller { interrupts and exceptions: non-maskable interrupts: 2 sources (external: 1 source, internal: 1 source) maskable interrupts: 74/75 sources (external: 25 sources, internal: 49/50 sources (see table 1-1 ) software exceptions: 32 sources exception trap: 2 sources { dma controller: 4 channels transfer unit: 8 bits/16 bits maximum transfer count: 65,536 (2 16 ) transfer type: flyby (1-cycle)/2-cycle transfer mode: single/single step/block transfer target: memory ? memory, memory ? i/o transfer request: external request/on-chip peripheral i/o/software dma transfer terminate (terminal count) output signal next address setting function
chapter 1 introduction user?s manual u16397ej3v0ud 23 { i/o lines: total: 112 { timer/counter function: up/down counter/general- purpose timer (tmenc) for 16-bit 2-phase encoder input: 1 channel 16-bit interval timer d (tmd): 4 channels 16-bit timer/event counter q (tmq): 1 channel 16-bit timer/event counter p (tmp): 3 channels motor control function (timers used: tm q: 1 channel (tmq0), tmp: 1 channel (tmp2) 16-bit accuracy 6-phase pwm function with dead time: 1 channel high-impedance output control function timer tuning operation function arbitrary cycle setting function arbitrary dead-time setting function watchdog timer: 1 channel { serial interfaces: asynchronous serial interface a (uarta) clocked serial interface b (csib) i 2 c bus interface (i 2 c) (i 2 c bus versions (y products) only) csib/uarta: 3 channels uarta/i 2 c: 1 channel { a/d converter: 10-bit resolution a/d converter: 8 channels { d/a converter: 8-bit resolution: 2 channels { rom correction: four places can be corrected. { on-chip debug function { clock generator: 1.25, 2.5, 5, 10 function via a pll clock synthesizer (input clock: 4 to 8 mhz) external clock input function (input clock: 5 to 25 mhz) { power-save function: halt/idle/software stop mode { package: 144-pin plastic lqfp (fine pitch) (20 20) 161-pin plastic fbga (13 13) { cmos technology: fully static circuits
chapter 1 introduction user?s manual u16397ej3v0ud 24 1.3 applications printers, dvd players, inverters, servos, nc machine tool s, ppc, robot control, digital home electronics, etc. 1.4 ordering information part number package internal rom pd703131agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703131agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703131aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703131aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703132agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703132agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703132aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703132aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703133agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703133agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703133aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703133aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703134agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703134agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703134aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703134aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (512 kb) pd703136agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703136agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703136aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703136aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) mask rom (256 kb) pd703131af1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (256 kb) pd703131ayf1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (256 kb) pd703132af1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (256 kb) pd703132ayf1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (256 kb) pd703133af1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (512 kb) pd703133ayf1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (512 kb) pd703134af1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (512 kb) pd703134ayf1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (512 kb) pd703136af1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (256 kb) pd703136ayf1-xxx-en4 note 161-pin plastic fbga (13 13) mask rom (256 kb) pd70f3134agj-uen 144-pin plastic lqfp (fine pitch) (20 20) flash memory (512 kb) pd70f3134agj-uen-a 144-pin plastic lqfp (fine pitch) (20 20) flash memory (512 kb) pd70f3134aygj-uen 144-pin plasti c lqfp (fine pitch) (20 20) flash memory (512 kb) pd70f3134aygj-uen-a 144-pin plas tic lqfp (fine pitch) (20 20) flash memory (512 kb) pd70f3134af1-en4 note 161-pin plastic fbga (13 13) flash memory (512 kb) pd70f3134af1-en4-a note 161-pin plastic fbga (13 13) flash memory (512 kb) pd70f3134ayf1-en4 note 161-pin plastic fbga (13 13) flash memory (512 kb) pd70f3134ayf1-en4-a note 161-pin plastic fbga (13 13) flash memory (512 kb) note under development remarks 1. xxx indicates rom code suffix. 2. products with -a at the end of the part number are lead-free products.
chapter 1 introduction user?s manual u16397ej3v0ud 25 1.5 pin configuration ? 144-pin plastic lqfp (fine pitch) (20 20) ? pd703131agj-xxx-uen ? pd703133agj-xxx-uen ? pd703136agj-xxx-uen ? pd703131agj-xxx-uen-a ? pd703133agj-xxx-uen-a ? pd703136agj-xxx-uen-a ? pd703131aygj-xxx-uen ? pd703133aygj-xxx-uen ? pd703136aygj-xxx-uen ? pd703131aygj-xxx-uen-a ? pd703133aygj-xxx-uen-a ? pd703136aygj-xxx-uen-a ? pd703132agj-xxx-uen ? pd703134agj-xxx-uen ? pd70f3134agj-uen ? pd703132agj-xxx-uen-a ? pd703134agj-xxx-uen-a ? pd70f3134agj-uen-a ? pd703132aygj-xxx-uen ? pd703134aygj-xxx-uen ? pd70f3134aygj-uen ? pd703132aygj-xxx-uen-a ? pd703134aygj-xxx-uen-a ? pd70f3134aygj-uen-a top view ad14/pdl14 ad13/pdl13 ad12/pdl12 ad11/pdl11 ad10/pdl10 ad9/pdl9 ad8/pdl8 ev dd ev ss ad7/pdl7 ad6/pdl6 ad5/pdl5 ad4/pdl4 ad3/pdl3 ad2/pdl2 ad1/pdl1 ad0/pdl0 intp001/top01/intpp01/p01 intp000/top00/evtp0/tip0/intpp00/p00 intp115/toqb3/evtq/p15 intp114/toqb2/tiq/p14 intp013/toqt3/intpq3/toq3/p13 v dd v ss intp012/toqt2/intpq2/toq2/p12 intp011/toqt1/intpq1/toq1/p11 intp010/toqb1/intpq0/toq0/p10 tdo/tc3/p27 tdi/intp126/tc2/p26 intp125/tc1/tiud10/to10/p25 intp124/tc0/p24 trst intp004/dmarq0/tclr10/intp11/p04 intp005/dmarq1/tcud10/intp10/p05 tms/intp106/dmarq2/p06 tck/intp107/dmarq3/p07 pcd3/sdras pcs0/cs0 pcs1/cs1 pcs2/cs2/iowr pcs3/cs3 pcs4/cs4 pcs5/cs5/iord pcs6/cs6 pcs7/cs7 ev ss ev dd pct0/lbe/lwr/ldqm pct1/ube/uwr/udqm pct4/rd pct5/wr/we pct6/astb pct7/bcyst pcm0/wait pcm1/busclk pcm2/hldak pcm3/hldrq pcm4/refrq p50/intp050/intpp20/top20/evtp2/tip2 p51/intp051/intpp21/top21 p20/nmi p37/intp137/adtrg v ss v dd p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 ev dd ev ss dmaak3/pbd3 dmaak2/pbd2 dmaak1/pbd1 dmaak0/pbd0 intp022/top11/intpp11/p22 intp021/top10/evtp1/tip1/intpp10/p21 intp134/rxd3/scl note /p34 intp133/txd3/sda note /p33 intp132/asck2/sck2/p32 intp131/rxd2/si2/p31 intp130/txd2/so2/p30 asck1/sck1/p45 rxd1/si1/p44 txd1/so1/p43 asck0/sck0/p42 rxd0/si0/p41 txd0/so0/p40 cv dd x2 x1 cv ss cksel psel v dd v ss mode0 mode1 reset av dd1 ano1/p81 ano0/p80 av ss1 av ss0 av dd0 pdl15/ad15 pal0/a0 pal1/a1 pal2/a2 pal3/a3 pal4/a4 pal5/a5 pal6/a6 pal7/a7 ev ss ev dd pal8/a8 pal9/a9 pal10/a10 pal11/a11 pal12/a12 pal13/a13 pal14/a14 pal15/a15 v ss v dd pah0/a16 pah1/a17 pah2/a18 pah3/a19 pah4/a20 pah5/a21 pah6/a22 pah7/a23 pah8/a24 pah9/a25 ev ss ev dd pcd0/sdcke pcd1/sdclk pcd2/sdcas 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 note i 2 c bus versions (y products) only (see table 1-1 )
chapter 1 introduction user?s manual u16397ej3v0ud 26 ? 161-pin plastic fbga (13 13) pd703131af1-xxx-en4 pd703133af1-xxx-en4 pd703136af1-xxx-en4 pd703131ayf1-xxx-en4 pd703133ayf1-xxx-en4 pd703136ayf1-xxx-en4 pd703132af1-xxx-en4 pd703134af1-xxx-en4 pd70f3134af1-en4 pd703132ayf1-xxx-en4 pd703134ayf1-xxx-en4 pd70f3134af1-en4-a pd70f3134ayf1-en4 pd70f3134ayf1-en4-a 14 13 12 11 10 9 8 7 6 5 4 3 2 1 top view bottom view pnmlk jhgfedcba abcdefghj klmnp index mark index mark (1/2) pin number pin name pin number pin name pin number pin name a1 ev ss b10 a21/pah5 d5 a6/pal6 a2 ad15/pdl15 b11 a25/pah9 d6 a10/pal10 a3 a2/pal2 b12 sdclk/pcd1 d7 a14/pal14 a4 a5/pal5 b13 cs1/pcs1 d8 a16/pah0 a5 ev ss b14 ev ss d9 a20/pah4 a6 a9/pal9 c1 ev ss d10 a23/pah7 a7 a12/pal12 c2 ad9/pdl9 d11 sdcke/pcd0 a8 a15/pal15 c3 ad13/pdl13 d12 cs0/pcs0 a9 a17/pah1 c4 a1/pal1 d13 cs5/iord/pcs5 a10 ? c5 a7/pal7 d14 ev ss a11 a24/pah8 c6 ev dd e1 ad5/pdl5 a12 ev dd c7 a11/pal11 e2 ad7/pdl7 a13 sdcas/pcd2 c8 v dd e3 ad8/pdl8 a14 sdras/pcd3 c9 a19/pah3 e4 ad11/pdl11 b1 ev ss c10 a22/pah6 e5 ? b2 ad12/pdl12 c11 ev ss e11 cs6/pcs6 b3 a0/pal0 c12 cs3/pcs3 e12 cs4/pcs4 b4 a4/pal4 c13 cs2/iowr/pcs2 e13 cs7/pcs7 b5 ev ss c14 ev ss e14 ev ss b6 a8/pal8 d1 ev ss f1 ad2/pdl2 b7 a13/pal13 d2 ad10/pdl10 f2 ad3/pdl3 b8 v ss d3 ad14/pdl14 f3 ad4/pdl4 b9 a18/pah2 d4 a3/pal3 f4 ev dd
chapter 1 introduction user?s manual u16397ej3v0ud 27 (2/2) pin number pin name pin number pin name pin number pin name f11 rd/pct4 l6 asck2/sck2/intp132/p32 p5 ev ss f12 ev dd l7 asck1/sck1/p45 p6 rxd1/si1/p44 f13 lbe/lwr/ldqm/pct0 l8 txd0/so0/p40 p7 rxd0/si0/p41 f14 ube/uwr/udqm/pct1 l9 mode0 p8 psel g1 top01/intp001/intpp01/p01 l10 av dd0 p9 cv dd g2 top00/intp000/evtp0/tip0/intpp00/p00 l11 ani7/p77 p10 x1 g3 ad0/pdl0 l12 ani4/p74 p11 ? g4 ad6/pdl6 l13 ani3/p73 p12 reset g11 wait/pcm0 l14 ani2/p72 p13 ano0/p80 g12 wr/we/pct5 m1 ev ss p14 ? g13 bcyst/pct7 m2 dmarq1/tcud10/intp10/intp005/p05 g14 astb/pct6 m3 dmarq0/intp11/tclr10/intp004/p04 h1 toqb3/intp115/evtq/p15 m4 dmaak2/pbd2 h2 toqb2/intp114/tiq/p14 m5 rxd3/scl note /intp134/p34 h3 toqt3/intp013/intpq3/toq3/p13 m6 rxd2/si2/intp131/p31 h4 ad1/pdl1 m7 txd1/so1/p43 h11 refrq/pcm4 m8 v dd h12 hldrq/pcm3 m9 cksel h13 hldak/pcm2 m10 mode1 h14 busclk/pcm1 m11 av ss0 j1 v dd m12 ani6/p76 j2 toqt2/intp012/intpq2/toq2/p12 m13 ani5/p75 j3 toqb1/intp010/intpq0/toq0/p10 m14 ? j4 v ss n1 ev ss j11 adtrg/intp137/p37 n2 dmarq3/tck/intp107/p07 j12 top21/intpp21/intp051/p51 n3 dmaak3/pbd3 j13 top20/intpp20/evtp2 /tip2/intp050/p50 n4 dmaak0/pbd0 j14 nmi/p20 n5 txd3/sda note /intp133/p33 k1 toqt1/intp011/intpq1/toq1/p11 n6 txd2/so2/intp130/p30 k2 tc3/tdo/p27 n7 asck0/sck0/p42 k3 tc0/intp124/p24 n8 v ss k4 tc2/tdi/intp126/p26 n9 x2 k11 ani1/p71 n10 cv ss k12 ani0/p70 n11 ano1/p81 k13 v ss n12 av ss1 k14 v dd n13 av dd1 l1 ev ss n14 ? l2 tc1/tiud10/to10 /intp125/p25 p1 ev dd l3 dmarq2/tms/intp106/p06 p2 ev ss l4 trst p3 dmaak1/pbd1 l5 top11/intpp11/intp022/p22 p4 top10/intpp10/evtp1 /tip1/intp021/p21 note i 2 c bus versions (y products) only (see table 1-1 ) remark leave the a10, e5, m14, n 14, p11, and p14 pins open.
chapter 1 introduction user?s manual u16397ej3v0ud 28 pin identification a0 to a25: address bus ldqm: lower dq mask enable ad0 to ad15: address/data bus lwr: lower byte write strobe adtrg: a/d trigger input mode0, mode1: mode ani0 to ani7: analog input nmi: non-maskable interrupt request ano0, ano1: analog output p00, p01, p04 to p07: port 0 asck0 to asck2: asynchronous seri al clock p10 to p15: port 1 astb: address strobe p20 to p22, p24 to p27: port 2 av dd0 , av dd1 : analog power supply p30 to p34, p37: port 3 av ss0 , av ss1 : analog ground p40 to p45: port 4 bcyst: bus cycle start timing p50, p51: port 5 busclk: bus clock output p70 to p77: port 7 p80, p81: port 8 cksel: clock generator operating mode select pah0 to pah9: port ah cs0 to cs7: chip select pal0 to pal15: port al cv dd : power supply for clock generator pbd0 to pbd3: port bd cv ss : ground for clock generator pcd0 to pcd3: port cd dmaak0 to dmaak3: dma acknowledge pcm0 to pcm4: port cm dmarq0 to dmarq3: dma reques t pcs0 to pcs7: port cs ev dd : power supply for extern al pins pct0, pct1, ev ss : ground for external pins pct4 to pct7: port ct evtp0 to evtp2, evtq: timer event co unt input pdl0 to pdl15: port dl hldak: hold acknowledge psel: pll select hldrq: hold request rd: read strobe intp000, intp001, refrq: refresh request intp004, intp005, reset: reset intp010 to intp013, rxd0 to rxd3: receive data intp021, intp022, sck0 to sck2: serial clock intp050, intp051, scl: serial clock intp106, intp107, sda: serial data intp114 to intp115, sdcas: sdram column address strobe intp124 to intp126, sdcke: sdram clock enable intp130 to intp134, sdclk: sdram clock output intp137: external interrupt input sdras: sdram row address strobe intp10, intp11, si0 to si2: serial input intpp00, intpp01, so0 to so2: serial output intpp10, intpp11, tc0 to tc3: terminal count signal intpp20, intpp21, tck: debug clock intpq0 to intpq3: timer input tclr10: timer clear iord: i/o read strobe tcud10: timer control pulse input iowr: i/o write strobe tdi: debug data input lbe: lower byte enable tdo: debug data output
chapter 1 introduction user?s manual u16397ej3v0ud 29 tip0 to tip3, tiq: timer trigger input tiud10: timer count pulse input tms: debug mode select to10, top00, top01, top10, top11, top20, top21, toq0 to toq3, toqt1 to toqt3, toqb1 to toqb3: timer output trst: debug reset txd0 to txd3: transmit data ube: upper byte enable udqm: upper dq mask enable uwr: upper byte write strobe v dd : power supply v ss : ground wait: wait we: write enable wr: write strobe x1, x2: crystal
chapter 1 introduction user?s manual u16397ej3v0ud 30 1.6 function blocks 1.6.1 internal block diagram nmi toq0 to toq3, toqt1 to toqt3, toqb1 to toqb3 ani0 to ani7 ano0, ano1 tclr10, tiud10, tcud10 intp10, intp11 to10 intp000, intp001, intp004, intp005 intp010 to intp013, intp114, intp115 intp021, intp022, intp124 to intp126 intp130 to intp134, intp137, intp050, intp051, intp106, intp107 intc tmenc 1 ch tmd 4 ch tmq0 1 ch tmp 3 ch uarta0/csib0 uarta1/csib1 adc 8 ch dac 2 ch rom ram note 2 cpu 32-bit barrel shifter pc system registers general- purpose registers (32 bits 32) alu multiplier (32 32 64) ports cg dcu system controller bcu psel cksel x1 x2 cv dd cv ss reset mode0, mode1 v dd v ss ev dd ev ss tck tms trst tdo tdi tiq, evtq, intpq0 to intpq3 evtp0 to evtp2, tip0 to tip2, intpp00, intpp01 intpp10, intpp11, intpp20, intpp21 top00, top01, top10, top11, top20, top21 txd2/so2 rxd2/si2 asck2/sck2 uarta2/csib2 adtrg txd0/so0 rxd0/si0 asck0/sck0 txd1/so1 rxd1/si1 asck1/sck1 av dd0 av ss 0 av dd1 av ss 1 instruction queue memc wait hldrq hldak busclk a0 to a25 ad0 to ad15 cs0 to cs7 bcyst rd uwr, lwr/ube, lbe wr astb iord iowr sdclk sdcke sdras sdcas we ldqm, udqm refrq sram rom dmac sdram wdt uarta3/i 2 c note 3 txd3/sda note 3 rxd3/scl note 3 dmarq0 to dmarq3 dmaak0 to dmaak3 tc0 to tc3 p00, p01, p04 to p07 p10 to p15 p20 p21, p22, p24 to p27 p30 to p34, p37 p40 to p45 p50, p51 p70 to p77 p80, p81 pal0 to pal15 pah0 to pah9 pdl0 to pdl15 pcs0 to pcs7 pct0 to pct7 pcm0 to pcm4 pcd0 to pcd3 pbd0 to pbd3 rom correction note 1 pll notes 1. 256/512 kb (mask rom) (see table 1-1 ) 512 kb (flash memory) (see table 1-1 ) 2. 8/16/32 kb (see table 1-1 ) 3. i 2 c bus versions (y products) only (see table 1-1 )
chapter 1 introduction user?s manual u16397ej3v0ud 31 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable sing le-clock execution of address calculations, arithmetic logic operations, data transfers, and almo st all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits or 32 bits 32 bits 64 bits) and a barrel shifter (32 bits), help accelerate complex processing. (2) bus control unit (bcu) the bcu starts the required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory area and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the pref etched instruction code is stored in an instruction queue in the cpu. the bcu controls a memory controller (memc) and dm a controller (dmac) and performs external memory access and dma transfer. (a) memory controller (memc) controls access to sram, external rom, external i/o, page rom, and sdram. (i) sram, external rom, external i/o interface supports access to sram, external rom, and external i/o. separate bus mode or multiplexed bus mode can be selected for the sram and external rom interface. (ii) sdram controller the sdram controller generates the sdras, s dcas, udqm, and ldqm signals and controls access to sdram. cas latency 1, 2, and 3 are supported, and the burst length is fixed to 1. (iii) page rom controller this controller supports accessing rom that includes a page access function. it performs address comparisons with the immediat ely preceding bus cycle and controls wait for normal access (off-page)/page access (on-page). (b) dma controller (dmac) this controller controls data transfer between memory and i/o instead of the cpu. there are two address modes: flyby (1-cycle) transfer, and 2-cycle transfer. there are three bus modes: single transfer, single-step transfer, and block transfer. (3) rom this is mask rom or flash memory of 256/51 2 kb mapped to a ddresses x0000000h to x003ffffh/ x0000000h to x007ffffh. during instruction fetch, mask rom/flash memo ry can be accessed from the cpu in 1 clock.
chapter 1 introduction user?s manual u16397ej3v0ud 32 (4) ram this is ram of 8/16/32 kb m apped from addresses xfffd000h to xfffefffh/xfffb000h to xfffefffh/xfff7000h to xfffefffh. during instruction fetch or data access, dat a can be accessed from the cpu in 1 clock. (5) interrupt controller (intc) this controller handles hardware interrupt requests (n mi, intpn) from on-chip peripheral hardware and external hardware (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137). eight levels of interrupt priorities can be specified for these interrupt requests, and multiple- interrupt servicing control can be performed. (6) clock generator (cg) the clock generator includes two basic operation modes: pll mode and clock-through mode. it generates four types of clocks (f xx , f xx /2, f xx /4, f xx /8), and supplies one of them as the operating clock for the cpu (f cpu ). (7) timer/counters (tmq, tmp, tmd, tmenc) this unit incorporates one 16-bit timer/event count er q (tmq) channel, three 16-bit timer/event counter p (tmp) channels, four 16-bit interval timer d (tmd) channels, and one up/down counter/general-purpose timer (tmenc) channel for 16-bit 2-phase encoder input, and can measure pulse interval widths or frequency, enable an inverter function for motor c ontrol, and output a programmable pulse. (8) watchdog timer (wdt) a watchdog timer is equipped to detect program loops, system abnormalities, etc. it can also be used as an interval timer. when used as a watchdog timer, it generates a non-ma skable interrupt request signal (intwdt) after an overflow occurs. when used as an interval timer, it generates a maskable interrupt request signal (intwdtm) after an overflow occurs. (9) serial interface the v850e/ma3 includes serial interface channels for asyn chronous serial interface a (uarta), clocked serial interface b (csib), and the i 2 c bus interface (i 2 c). three of these channels are switchable between uarta and csib and another is switchable between uarta and i 2 c. for uarta, data is transferred via the txdn and rxdn pins (n = 0 to 3). for csib, data is transferred via the son, sin, and sckn pins (n = 0 to 2). for i 2 c, data is transferred via the scl and sda pins. (10) a/d converter (adc) this high-speed 10-bit a/d converter includes 8 analog input pins. (11) d/a converter (dac) two 8-bit-resolution d/a converter channels that use the r-2r ladder method are provided on chip. (12) rom correction a rom correction function that replaces part of a progr am in the mask rom or flash memory with a program in the internal ram is provided. up to four correction addresses can be specified.
chapter 1 introduction user?s manual u16397ej3v0ud 33 (13) on-chip debug function (dcu) an on-chip debug function via an n-wire type emulator is provided. (14) ports as shown below, the following ports have general -purpose port functions and control pin functions. port port function alternate function port 0 6-bit i/o timer/counter i/o, external interrupt input, dma controller input, debug input port 1 6-bit i/o timer/counter i/o, external interrupt input port 2 1-bit input, 6-bit i/o nmi inpu t, timer/counter i/o, external interrupt input, dma controller output, debug i/o port 3 6-bit i/o serial interface i/o, external in terrupt input, a/d converter external trigger input port 4 6-bit i/o serial interface i/o port 5 2-bit i/o timer/counter i/o, external interrupt input port 7 8-bit input a/d converter input port 8 2-bit input d/a converter output port al 16-bit i/o external address bus port ah 10-bit i/o external address bus port dl 16-bit i/o external address/data bus port cs 8-bit i/o external bus interface control signal output port ct 6-bit i/o external bus interface control signal output port cm 5-bit i/o wait insertion signal i nput, external bus interface control signal i/o port cd 4-bit i/o external bus interface control signal output port bd 4-bit i/o dma controller output
user?s manual u16397ej3v0ud 34 chapter 2 pin functions the names and functions of the pins in the v850e/ma3 are listed below. these pins can be divided into port pins and non-port pins according to their functions. 2.1 list of pin functions (1) port pins (1/4) pin no. pin name gj f1 i/o function alternate function p00 19 g2 top00/intp000/evtp0/tip0/intpp00 p01 18 g1 top01/intp001/intpp01 p04 33 m3 dmarq0/intp11/tclr10/intp004 p05 34 m2 dmarq1/tcud10/intp10/intp005 p06 35 l3 dmarq2/tms/intp106 p07 36 n2 i/o port 0 6-bit i/o port input data can be read/output data can be written in 1-bit units. dmarq3/tck/intp107 p10 27 j3 toqb1/intp010/intpq0/toq0 p11 26 k1 toqt1/intp011/intpq1/toq1 p12 25 j2 toqt2/intp012/intpq2/toq2 p13 22 h3 toqt3/intp013/intpq3/toq3 p14 21 h2 toqb2/intp114/tiq p15 20 h1 i/o port 1 6-bit i/o port input data can be read/output data can be written in 1-bit units. toqb3/intp115/evtq p20 84 j14 input nmi p21 44 p4 top10/intpp10/evtp1/tip1/intp021 p22 43 l5 top11/intpp11/intp022 p24 31 k3 tc0/intp124 p25 30 l2 tc1/tiud10/to10/intp125 p26 29 k4 tc2/tdi/intp126 p27 28 k2 i/o port 2 p20 is an input-only port. if a valid edge is input, it operates as an nmi input. also, the status of the nmi input is shown by bit 0 of the p2 register. p21, p22, p24 to p27 are 6-bit i/o port pins. input data can be read/output data can be written in 1-bit units. tc3/tdo p30 49 n6 txd2/so2/intp130 p31 48 m6 rxd2/si2/intp131 p32 47 l6 asck2/sck2/intp132 p33 46 n5 txd3/sda note /intp133 p34 45 m5 rxd3/scl note /intp134 p37 83 j11 i/o port 3 6-bit i/o port input data can be read/output data can be written in 1-bit units. adtrg/intp137 note i 2 c bus versions (y products) only (see table 1-1 ) remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 35 (2/4) pin no. pin name gj f1 i/o function alternate function p40 55 l8 txd0/so0 p41 54 p7 rxd0/si0 p42 53 n7 asck0/sck0 p43 52 m7 txd1/so1 p44 51 p6 rxd1/si1 p45 50 l7 i/o port 4 6-bit i/o port input data can be read/output data can be written in 1-bit units. asck1/sck1 p50 86 j13 top20/intpp20/evtp2/tip2/intp050 p51 85 j12 i/o port 5 2-bit i/o port input data can be read/output data can be written in 1-bit units. top21/intpp21/intp051 p70 80 k12 ani0 p71 79 k11 ani1 p72 78 l14 ani2 p73 77 l13 ani3 p74 76 l12 ani4 p75 75 m13 ani5 p76 74 m12 ani6 p77 73 l11 input port 7 8-bit input-only port ani7 p80 69 p13 ano0 p81 68 n11 input port 8 2-bit input-only port ano1 pal0 143 b3 a0 pal1 142 c4 a1 pal2 141 a3 a2 pal3 140 d4 a3 pal4 139 b4 a4 pal5 138 a4 a5 pal6 137 d5 a6 pal7 136 c5 a7 pal8 133 b6 a8 pal9 132 a6 a9 pal10 131 d6 a10 pal11 130 c7 a11 pal12 129 a7 a12 pal13 128 b7 a13 pal14 127 d7 a14 pal15 126 a8 i/o port al 8-/16-bit i/o port input data can be read/output data can be written in 1-bit units. a15 remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 36 (3/4) pin no. pin name gj f1 i/o function alternate function pah0 123 d8 a16 pah1 122 a9 a17 pah2 121 b9 a18 pah3 120 c9 a19 pah4 119 d9 a20 pah5 118 b10 a21 pah6 117 c10 a22 pah7 116 d10 a23 pah8 115 a11 a24 pah9 114 b11 i/o port ah 8-/10-bit i/o port input data can be read/output data can be written in 1-bit units. a25 pdl0 17 g3 ad0 pdl1 16 h4 ad1 pdl2 15 f1 ad2 pdl3 14 f2 ad3 pdl4 13 f3 ad4 pdl5 12 e1 ad5 pdl6 11 g4 ad6 pdl7 10 e2 ad7 pdl8 7 e3 ad8 pdl9 6 c2 ad9 pdl10 5 d2 ad10 pdl11 4 e4 ad11 pdl12 3 b2 ad12 pdl13 2 c3 ad13 pdl14 1 d3 ad14 pdl15 144 a2 i/o port dl 8-/16-bit i/o port input data can be read/output data can be written in 1-bit units. ad15 pcs0 107 d12 cs0 pcs1 106 b13 cs1 pcs2 105 c13 cs2/iowr pcs3 104 c12 cs3 pcs4 103 e12 cs4 pcs5 102 d13 cs5/iord pcs6 101 e11 cs6 pcs7 100 e13 i/o port cs 8-bit i/o port input data can be read/output data can be written in 1-bit units. cs7 remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 37 (4/4) pin no. pin name gj f1 i/o function alternate function pct0 97 f13 lbe/lwr/ldqm pct1 96 f14 ube/uwr/udqm pct4 95 f11 rd pct5 94 g12 wr/we pct6 93 g14 astb pct7 92 g13 i/o port ct 6-bit i/o port input data can be read/output data can be written in 1-bit units. bcyst pcm0 91 g11 wait pcm1 90 h14 busclk pcm2 89 h13 hldak pcm3 88 h12 hldrq pcm4 87 h11 i/o port cm 5-bit i/o port input data can be read/output data can be written in 1-bit units. refrq pcd0 111 d11 sdcke pcd1 110 b12 sdclk pcd2 109 a13 sdcas pcd3 108 a14 i/o port cd 4-bit i/o port input data can be read/output data can be written in 1-bit units. sdras pbd0 42 n4 dmaak0 pbd1 41 p3 dmaak1 pbd2 40 m4 dmaak2 pbd3 39 n3 i/o port bd 4-bit i/o port input data can be read/output data can be written in 1-bit units. dmaak3 remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 38 (2) non-port pins (1/6) pin no. pin name gj f1 i/o function alternate function a0 143 b3 pal0 a1 142 c4 pal1 a2 141 a3 pal2 a3 140 d4 pal3 a4 139 b4 pal4 a5 138 a4 pal5 a6 137 d5 pal6 a7 136 c5 pal7 a8 133 b6 pal8 a9 132 a6 pal9 a10 131 d6 pal10 a11 130 c7 pal11 a12 129 a7 pal12 a13 128 b7 pal13 a14 127 d7 pal14 a15 126 a8 pal15 a16 123 d8 pah0 a17 122 a9 pah1 a18 121 b9 pah2 a19 120 c9 pah3 a20 119 d9 pah4 a21 118 b10 pah5 a22 117 c10 pah6 a23 116 d10 pah7 a24 115 a11 pah8 a25 114 b11 output 26-bit address bus for external memory pah9 ad0 17 g3 pdl0 ad1 16 h4 pdl1 ad2 15 f1 pdl2 ad3 14 f2 pdl3 ad4 13 f3 pdl4 ad5 12 e1 pdl5 ad6 11 g4 pdl6 ad7 10 e2 pdl7 ad8 7 e3 pdl8 ad9 6 c2 pdl9 ad10 5 d2 pdl10 ad11 4 e4 i/o 16-bit address/data bus for external memory pdl11 remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 39 (2/6) pin no. pin name gj f1 i/o function alternate function ad12 3 b2 pdl12 ad13 2 c3 pdl13 ad14 1 d3 pdl14 ad15 144 a2 i/o 16-bit address/data bus for external memory pdl15 adtrg 83 j11 input a/d converter external trigger input intp137/p37 ani0 80 k12 p70 ani1 79 k11 p71 ani2 78 l14 p72 ani3 77 l13 p73 ani4 76 l12 p74 ani5 75 m13 p75 ani6 74 m12 p76 ani7 73 l11 input analog inputs for a/d converter p77 ano0 69 p13 p80 ano1 68 n11 output analog outputs for d/a converter p81 asck0 53 n7 sck0/p42 asck1 50 l7 sck1/p45 asck2 47 l6 input uarta0 to uarta2 serial baud rate clock input sck2/intp132/p32 astb 93 g14 output address strobe output of external data bus pct6 av dd0 72 l10 ? positive power supply for a/d converter (3.3 v) ? av dd1 67 n13 ? positive power supply for d/a converter (3.3 v) ? av ss0 71 m11 ? ground potential for a/d converter ? av ss1 70 n12 ? ground potential for d/a converter ? bcyst 92 g13 output bus cycle start output pct7 busclk 90 h14 output bus clock output pcm1 cksel 60 m9 input clock generator operating mode specification ? cs0 107 d12 pcs0 cs1 106 b13 pcs1 cs2 105 c13 pcs2/iowr cs3 104 c12 pcs3 cs4 103 e12 pcs4 cs5 102 d13 pcs5/iord cs6 101 e11 pcs6 cs7 100 e13 output chip select output pcs7 cv dd 56 p9 ? positive power supply for osc pin (3.3 v) ? cv ss 59 n10 ? ground potential for osc pin ? dmaak0 42 n4 pbd0 dmaak1 41 p3 pbd1 dmaak2 40 m4 pbd2 dmaak3 39 n3 output dma transfer acknowledge output pbd3 remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 40 (3/6) pin no. pin name gj f1 i/o function alternate function dmarq0 33 m3 intp11/tclr10/intp004/p04 dmarq1 34 m2 tcud10/intp10/intp005/p05 dmarq2 35 l3 tms/intp106/p06 dmarq3 36 n2 input dma transfer request input tck/intp107/p07 ev dd note 1 note 1 ? positive power supply for external pin (3.3 v) ? ev ss note 2 note 2 ? ground potential for external pin ? evtp0 19 g2 top00/intp000/tip0/intpp00/p00 evtp1 44 p4 top10/intpp10/tip1/intp021/p21 evtp2 86 j13 input tmp0 to tmp2 external event count input top20/intpp20/tip2/intp050/p50 evtq 20 h1 input tmq0 external ev ent count input toqb3/intp115/p15 hldak 89 h13 output bus hold acknowledge output pcm2 hldrq 88 h12 input bus hold request input pcm3 intp10 34 m2 dmarq1/tcud10/intp005/p05 intp11 33 m3 input tmenc10 external capture trigger input dmarq0/tclr10/intp004/p04 intp000 19 g2 top00/evtp0/tip0/intpp00/p00 intp001 18 g1 top01/intpp01/p01 intp004 33 m3 dmarq0/intp11/tclr10/p04 intp005 34 m2 dmarq1/tcud10/intp10/p05 intp106 35 l3 dmarq2/tms/p06 intp107 36 n2 dmarq3/tck/p07 intp010 27 j3 toqb1/intpq0/toq0/p10 intp011 26 k1 toqt1/intpq1/toq1/p11 intp012 25 j2 toqt2/intpq2/toq2/p12 intp013 22 h3 toqt3/intpq3/toq3/p13 intp114 21 h2 toqb2/tiq/p14 intp115 20 h1 toqb3/evtq/p15 intp021 44 p4 top10/intpp10/evtp1/tip1/p21 intp022 43 l5 top11/intpp11/p22 intp124 31 k3 tc0/p24 intp125 30 l2 tc1/tiud10/to10/p25 intp126 29 k4 tc2/tdi/p26 intp130 49 n6 txd2/so2/p30 intp131 48 m6 rxd2/si2/p31 intp132 47 l6 input external maskable interrupt request input asck2/sck2/p32 notes 1. gj: 8, 37, 98, 112, 134 f1: a12, c6, f4, f12, p1 2. gj: 9, 38, 99, 113, 135 f1: a1, a5, b1, b5, b14, c1, c11, c1 4, d1, d14, e14, l1, m1, n1, p2, p5 remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 41 (4/6) pin no. pin name gj f1 i/o function alternate function intp133 46 n5 txd3/sda note /p33 intp134 45 m5 rxd3/scl note /p34 intp137 83 j11 adtrg/p37 intp050 86 j13 top20/intpp20/evtp2/tip2/p50 intp051 85 j12 input external maskable interrupt request input top21/intpp21/p51 intpp00 19 g2 top00/intp000/evtp0/tip0/p00 intpp01 18 g1 top01/intp001/p01 intpp10 44 p4 top10/evtp1/tip1/intp021/p21 intpp11 43 l5 top11/intp022/p22 intpp20 86 j13 top20/evtp2/tip2/intp050/p50 intpp21 85 j12 input tmp0 to tmp2 external capture trigger input top21/intp051/p51 intpq0 27 j3 toqb1/intp010/toq0/p10 intpq1 26 k1 toqt1/intp011/toq1/p11 intpq2 25 j2 toqt2/intp012/toq2/p12 intpq3 22 h3 input tmq0 external capture trigger input toqt3/intp013/toq3/p13 iord 102 d13 output i/o read strobe output pcs5/cs5 iowr 105 c13 output i/o write strobe output pcs2/cs2 lbe 97 f13 output external data bus byte enable output (d0 to d7) pct0/lwr/ldqm ldqm 97 f13 output i/o mask signal output for sdram (d0 to d7) pct0/lbe/lwr lwr 97 f13 output external data bus write strobe output (d0 to d7) pct0/lbe/ldqm mode0 64 l9 ? mode1 65 m10 input operation mode specification ? nmi 84 j14 input non-maskable interrupt request input p20 psel 61 p8 input input frequency select signal input in pll mode ? rd 95 f11 output external data bus read strobe output pct4 refrq 87 h11 output refresh request output for sdram pcm4 reset 66 p12 input system reset input ? rxd0 54 p7 si0/p41 rxd1 51 p6 si1/p44 rxd2 48 m6 si2/intp131/p31 rxd3 45 m5 input uarta0 to uarta3 serial receive data input scl note /intp134/p34 sck0 53 n7 asck0/p42 sck1 50 l7 asck1/p45 sck2 47 l6 i/o csib0 to csib2 serial clock i/o asck2/intp132/p32 scl note 45 m5 i/o i 2 c serial clock i/ o rxd3/intp134/p34 sda note 46 n5 i/o i 2 c data i/o txd3/intp133/p33 sdcas 109 a13 output column address strobe output for sdram pcd2 sdcke 111 d11 output clock enable output for sdram pcd0 sdclk 110 b12 output clock output for sdram pcd1 note i 2 c bus versions (y products) only (see table 1-1 ) remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 42 (5/6) pin no. pin name gj f1 i/o function alternate function sdras 108 a14 output row address strobe output for sdram pcd3 si0 54 p7 rxd0/p41 si1 51 p6 rxd1/p44 si2 48 m6 input csib0 to csib2 serial receive data input rxd2/intp131/p31 so0 55 l8 txd0/p40 so1 52 m7 txd1/p43 so2 49 n6 output csib0 to csib2 serial transmit data output txd2/intp130/p30 tc0 31 k3 intp124/p24 tc1 30 l2 tiud10/to10/intp125/p25 tc2 29 k4 tdi/intp126/p26 tc3 28 k2 output dma transfer end (terminal count) output tdo/p27 tck 36 n2 input debug clock input for n-wi re type emulator dmarq3/intp107/p07 tclr10 33 m3 input clear signal input to tmenc10 dmarq0/intp11/intp004/p04 tcud10 34 m2 input count operation switching signal for tmenc10 dmarq1/intp10/intp005/p05 tdi 29 k4 input debug data input for n-wire type emulator tc2/intp126/p26 tdo 28 k2 output debug data output for n-wire type emulator tc3/p27 tip0 19 g2 top00/intp000/evtp0/intpp00/p00 tip1 44 p4 top10/intpp10/evtp1/intp021/p21 tip2 86 j13 input tmp0 to tmp2 external timer trigger input top20/intpp20/evtp2/intp050/p50 tiq 21 h2 input tmq0 external ti mer trigger input toqb2/intp114/p14 tiud10 30 l2 input external count clock input of tmenc10 tc1/to10/intp125/p25 tms 35 l3 input debug mode select for n-wire type emulator dmarq2/intp106/p06 to10 30 l2 output tmenc10 pulse signal output tc1/tiud10/intp125/p25 top00 19 g2 intp000/evtp0/tip0/intpp00/p00 top01 18 g1 intp001/intpp01/p01 top10 44 p4 intpp10/evtp1/tip1/intp021/p21 top11 43 l5 intpp11/intp022/p22 top20 86 j13 intpp20/evtp2/tip2/intp050/p50 top21 85 j12 output tmp0 to tmp2 pulse signal output intpp21/intp051/p51 toq0 27 j3 toqb1/intp010/intpq0/p10 toq1 26 k1 toqt1/intp011/intpq1/p11 toq2 25 j2 toqt2/intp012/intpq2/p12 toq3 22 h3 output tmq0 pulse signal output toqt3/intp013/intpq3/p13 remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 43 (6/6) pin no. pin name gj f1 i/o function alternate function toqb1 27 j3 intp010/intpq0/toq0/p10 toqb2 21 h2 intp114/tiq/p14 toqb3 20 h1 intp115/evtq/p15 toqt1 26 k1 intp011/intpq1/toq1/p11 toqt2 25 j2 intp012/intpq2/toq2/p12 toqt3 22 h3 output pulse signal output for 6-phase pwm intp013/intpq3/toq3/p13 trst 32 l4 input debug reset input for n-wire type emulator ? txd0 55 l8 so0/p40 txd1 52 m7 so1/p43 txd2 49 n6 so2/intp130/p30 txd3 46 n5 output uarta0 to uarta3 serial transmit data output sda note 1 /intp133/p33 ube 96 f14 output external data bus byte enable output (d8 to d15) pct1/uwr/udqm udqm 96 f14 output i/o mask signal output for sdram (d8 to d15) pct1/ube/uwr uwr 96 f14 output external data bus write strobe output (d8 to d15) pct1/ube/udqm v dd note 2 note 2 ? positive power supply for internal units (2.5 v) ? v ss note 3 note 3 ? ground potential for internal units ? wait 91 g11 input external wait request input pcm0 we 94 g12 output write enable output for sdram pct5/wr wr 94 g12 output write strobe output for external data bus pct5/we x1 58 p10 input ? x2 57 n9 ? crystal connection for system clock oscillator/external clock input (x2 is open when external clock is input) ? notes 1. i 2 c bus versions (y products) only (see table 1-1 ) 2. gj: 23, 62, 81, 124 f1: c8, j1, k14, m8 3. gj: 24, 63, 82, 125 f1: b8, j4, k13, n8 remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 44 2.2 pin status the status of each pin after reset, in power-save mode (halt, idle, or software stop mode), and during dma transfer, refresh, and bus hold (th) is shown below. operating status pin reset (single-chip mode) idle mode/software stop mode halt mode/during dma transfer/ refresh bus hold (th) note 2 a0 to a15 (pal0 to pal15) hi-z hi-z operating hi-z a16 to a25 (pah0 to pah9) hi-z hi-z operating hi-z ad0 to ad15 (pdl0 to pdl15) hi-z hi-z operating hi-z cs0 to cs7 (pcs0 to pcs7) hi-z self operating hi-z iowr (pcs2) ? h operating hi-z iord (pcs5) ? h operating hi-z lwr, uwr (pct0, pct1) hi-z h operating hi-z lbe, ube (pct0, pct1) ? h operating hi-z ldqm, udqm (pct0, pct1) ? h operating hi-z rd (pct4) hi-z h operating hi-z wr (pct5) hi-z h operating hi-z we (pct5) ? h operating hi-z astb (pct6) hi-z h operating hi-z bcyst (pct7) hi-z h operating hi-z wait (pcm0) hi-z input not sampled operating input not sampled busclk (pcm1) hi-z l operating operating hldak (pcm2) hi-z h operating l hldrq (pcm3) hi-z input not sampled operating operating refrq (pcm4) hi-z l note 1 operating operating sdcke (pcd0) hi-z l operating h sdclk (pcd1) hi-z l operating operating sdcas (pcd2) hi-z self operating hi-z sdras (pcd3) hi-z self operating hi-z dmaak0 to dmaak3 (pbd0 to pbd3) hi-z h operating h notes 1. high-level output when the sdram controller is not used. 2. the pin set in the port mode hold s the status immediately before. remark hi-z: high-impedance h: high-level output l: low-level output self: self-refresh state when pins are connected to sdram
chapter 2 pin functions user?s manual u16397ej3v0ud 45 2.3 pin i/o circuits and recomme nded connection of unused pins it is recommended that 1 to 10 k ? resistors be used when connecting to v dd or v ss via resistors. (1/4) pin no. pin name alternate-function pin name gj f1 i/o circuit type recommended connection p00 top00/intp000/evtp0/tip0/intpp00 19 g2 p01 top01/intp001/intpp01 18 g1 p04 dmarq0/intp11/tclr10/intp004 33 m3 p05 dmarq1/tcud10/intp10/intp005 34 m2 p06 dmarq2/tms/intp106 35 l3 p07 dmarq3/tck/intp107 36 n2 p10 toqb1/intp010/intpq0/toq0 27 j3 p11 toqt1/intp011/intpq1/toq1 26 k1 p12 toqt2/intp012/intpq2/toq2 25 j2 p13 toqt3/intp013/intpq3/toq3 22 h3 p14 toqb2/intp114/tiq 21 h2 p15 toqb3/intp115/evtq 20 h1 5-k input: independently connect to ev dd or ev ss via a resistor. output: leave open. p20 nmi 84 j14 2 independently connect to ev ss via a resistor. p21 top10/intpp10/evtp1/tip1/intp021 44 p4 p22 top11/intpp11/intp022 43 l5 p24 tc0/intp124 31 k3 p25 tc1/tiud10/to10/intp125 30 l2 p26 tc2/tdi/intp126 29 k4 5-k p27 tc3/tdo 28 k2 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. p30 txd2/so2/intp130 49 n6 p31 rxd2/si2/intp131 48 m6 p32 asck2/sck2/intp132 47 l6 p33 txd3/sda note /intp133 46 n5 p34 rxd3/scl note /intp134 45 m5 p37 adtrg/intp137 83 j11 5-k input: independently connect to ev dd or ev ss via a resistor. output: leave open. p40 txd0/so0 55 l8 5 p41 rxd0/si0 54 p7 p42 asck0/sck0 53 n7 5-k p43 txd1/so1 52 m7 5 p44 rxd1/si1 51 p6 p45 asck1/sck1 50 l7 5-k input: independently connect to ev dd or ev ss via a resistor. output: leave open. note i 2 c bus versions (y products) only (see table 1-1 ) remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 46 (2/4) pin no. pin name alternate-function pin name gj f1 i/o circuit type recommended connection p50 top20/intpp20/evtp2/tip2/intp050 86 j13 p51 top21/intpp21/intp051 85 j12 5-k input: independently connect to ev dd or ev ss via a resistor. output: leave open. p70 ani0 80 k12 p71 ani1 79 k11 p72 ani2 78 l14 p73 ani3 77 l13 p74 ani4 76 l12 p75 ani5 75 m13 p76 ani6 74 m12 p77 ani7 73 l11 9 independently connect to av dd0 or av ss0 via a resistor. p80 ano0 69 p13 p81 ano1 68 n11 34 independently connect to av dd1 or av ss1 via a resistor. pal0 a0 143 b3 pal1 a1 142 c4 pal2 a2 141 a3 pal3 a3 140 d4 pal4 a4 139 b4 pal5 a5 138 a4 pal6 a6 137 d5 pal7 a7 136 c5 pal8 a8 133 b6 pal9 a9 132 a6 pal10 a10 131 d6 pal11 a11 130 c7 pal12 a12 129 a7 pal13 a13 128 b7 pal14 a14 127 d7 pal15 a15 126 a8 pah0 a16 123 d8 pah1 a17 122 a9 pah2 a18 121 b9 pah3 a19 120 c9 pah4 a20 119 d9 pah5 a21 118 b10 pah6 a22 117 c10 pah7 a23 116 d10 pah8 a24 115 a11 pah9 a25 114 b11 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 47 (3/4) pin no. pin name alternate-function pin name gj f1 i/o circuit type recommended connection pdl0 ad0 17 g3 pdl1 ad1 16 h4 pdl2 ad2 15 f1 pdl3 ad3 14 f2 pdl4 ad4 13 f3 pdl5 ad5 12 e1 pdl6 ad6 11 g4 pdl7 ad7 10 e2 pdl8 ad8 7 e3 pdl9 ad9 6 c2 pdl10 ad10 5 d2 pdl11 ad11 4 e4 pdl12 ad12 3 b2 pdl13 ad13 2 c3 pdl14 ad14 1 d3 pdl15 ad15 144 a2 pcs0 cs0 107 d12 pcs1 cs1 106 b13 pcs2 cs2/iowr 105 c13 pcs3 cs3 104 c12 pcs4 cs4 103 e12 pcs5 cs5/iord 102 d13 pcs6 cs6 101 e11 pcs7 cs7 100 e13 pct0 lbe/lwr/ldqm 97 f13 pct1 ube/uwr/udqm 96 f14 pct4 rd 95 f11 pct5 wr/we 94 g12 pct6 astb 93 g14 pct7 bcyst 92 g13 pcm0 wait 91 g11 pcm1 busclk 90 h14 pcm2 hldak 89 h13 pcm3 hldrq 88 h12 pcm4 refrq 87 h11 pcd0 sdcke 111 d11 pcd1 sdclk 110 b12 pcd2 sdcas 109 a13 pcd3 sdras 108 a14 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 48 (4/4) pin no. pin name alternate-function pin name gj f1 i/o circuit type recommended connection pbd0 dmaak0 42 n4 pbd1 dmaak1 41 p3 pbd2 dmaak2 40 m4 pbd3 dmaak3 39 n3 5 input: independently connect to ev dd or ev ss via a resistor. output: leave open. trst ? 32 l4 independently connect to ev ss via a resistor. reset ? 66 p12 ? mode0 ? 64 l9 ? mode1 ? 65 m10 ? psel ? 61 p8 ? cksel ? 60 m9 2 ? x2 ? 57 n9 ? leave open. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 2 pin functions user?s manual u16397ej3v0ud 49 2.4 pin i/o circuits type 2 type 5 type 5-k in schmitt-triggered input with hysteresis characteristics p-ch n-ch v dd in/out data output disable input enable type 9 type 34 in comparator + v ref (threshold voltage) p-ch n-ch input enable p-ch n-ch v dd in/out data output disable input enable input enable p-ch n-ch in/out analog output voltage caution type 2 or 5-k pins have hysteresis character istics when their alternate function is used in the input mode, but do not have hyst eresis characteristics when they are used in the port mode.
user?s manual u16397ej3v0ud 50 chapter 3 cpu function the cpu of the v850e/ma3 is based on risc architecture and executes almost all the instructions in one clock cycle using 5-stage pipeline control. 3.1 features ? minimum instruction execution time: 12.5 ns (@80 mhz internal operation) ? memory space program space: 64 mb linear data space: 4 gb linear ? thirty-two 32-bit general-purpose registers ? internal 32-bit architecture ? five-stage pipeline control ? multiply/divide instructions ? saturated operation instructions ? one-clock 32-bit shift instruction ? load/store instruction with long/short instruction format ? four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1
chapter 3 cpu function user?s manual u16397ej3v0ud 51 3.2 cpu register set the registers of the v850e/ma3 can be classified into tw o categories: a general-purpose program register set and a dedicated system register set. a ll the registers have a 32-bit width. for details, refer to v850e1 architecture user?s manual . figure 3-1. cpu register set (1) program register set (2) system register set r0 (zero register) r1 (assembler-reserved register) r2 r3 (stack pointer (sp)) r4 (global pointer (gp)) r5 (text pointer (tp)) r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (element pointer (ep)) r31 (link pointer (lp)) 31 0 pc (program counter) 31 0 eipc (status saving register during interrupt) eipsw (status saving register during interrupt) fepc (status saving register during nmi) fepsw (status saving register during nmi) ecr (interrupt source register) psw (program status word) ctpc (status saving register during callt execution) ctpsw (status saving register during callt execution) dbpc (status saving register during exception/debug trap) dbpsw (status saving register during exception/debug trap) ctbp (callt base pointer) asid (program id register) 31 0
chapter 3 cpu function user?s manual u16397ej3v0ud 52 3.2.1 program register set the program register set includes general -purpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. any of these registers can be used as a data variable or address variable. however, r0 and r30 are implicitly used by instru ctions, and care must be exercised when using these registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used, by means of the sld and sst instructions, as a base pointer for when memory is accessed. also, r1, r3 to r5, and r31 are implicitly used by the assembler a nd c compiler. therefore, before using these registers, their contents must be saved so that th ey are not lost. the contents must be restored to the registers after the registers have been used. r2 may be used by the real-tim e os. if the real-time os does not use r2, it can be used as a variable register. table 3-1. general-purpose registers name usage operation r0 zero register always holds 0 r1 assembler-reserved register working register for genera ting 32-bit immediate data r2 address/data variable register (when r2 is not used by the real-time os) r3 stack pointer used to generate stack frame when function is called r4 global pointer used to acce ss global variable in data area r5 text pointer register to indicate the start of the text area (where program code is located) r6 to r29 address/dat a variable registers r30 element pointer base pointer when memory is accessed r31 link pointer used by compiler when calling function (2) program counter (pc) this register holds the instruction address during program execution. the lower 26 bi ts of this register are valid, and bits 31 to 26 are fixed to 0. if a carry occurs from bit 25 to 26, it is ignored. bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 after reset 00000000h
chapter 3 cpu function user?s manual u16397ej3v0ud 53 3.2.2 system register set system registers control the status of the cpu and hold interrupt information. to read/write these system r egisters, specify a system register number indicated below using the system register load/store instruction (lds r or stsr instruction). table 3-2. system register numbers operand specification no. system register name ldsr instruction stsr instruction 0 status saving register during interrupt (eipc) note 1 { { 1 status saving register during interrupt (eipsw) note 1 { { 2 status saving register during nmi (fepc) { { 3 status saving register during nmi (fepsw) { { 4 interrupt source register (ecr) { 5 program status word (psw) { { 6 to 15 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). 16 status saving register du ring callt execution (ctpc) { { 17 status saving register du ring callt execution (ctpsw) { { 18 status saving register du ring exception/debug trap (dbpc) { note 2 { note 2 19 status saving register during exception/debug trap (dbpsw) { note 2 { note 2 20 callt base pointer (ctbp) { { 21, 22 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). 23 program id register (asid) { { 24 to 31 reserved for future function ex pansion (operations that access these register numbers cannot be guaranteed). notes 1. because this register has only one set, to enable multip le interrupts, it is necessary to save this register by program. 2. these registers can be read/written in the per iod between dbtrap instruction or illegal opcode execution and dbret instruction execution. caution even if bit 0 of eipc, fepc, or ctpc is set to 1 by the ldsr instruction, bit 0 will be ignored when the program is returned by the reti instruction after in terrupt servicing (because bit 0 of the pc is fixed to 0). when setting the value of eipc, fepc, and ctpc, use an even value (bit 0 = 0). remark { : access allowed : access prohibited
chapter 3 cpu function user?s manual u16397ej3v0ud 54 (1) interrupt status saving registers (eipc, eipsw) there are two interrupt status sa ving registers, eipc and eipsw. upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (pc) are saved to eipc and the contents of the program status word (psw) are saved to eipsw (upon occurrence of a non-maskable interrupt (nmi), the contents are saved to the nm i status saving registers (fepc, fepsw)). the address of the next instruction fo llowing the instruction executed wh en a software exception or maskable interrupt occurs is saved to eipc, except for some instructions (see 20.9 period in which cpu does not acknowledge interrupts ). the current psw contents are saved to eipsw. since there is only one set of interrupt status saving r egisters, the contents of thes e registers must be saved by the program when multiple interrupt servicing is enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are rese rved (fixed to 0) for future function expansion. when the reti instruction is execut ed, the values in eipc and eipsw are restored to the pc and psw, respectively. 31 0 eipc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu function user?s manual u16397ej3v0ud 55 (2) nmi status saving registers (fepc, fepsw) there are two nmi status saving registers, fepc and fepsw. upon occurrence of a non-maskable interrupt (nmi), t he contents of the program co unter (pc) are saved to fepc and the contents of the program status word (psw) are saved to fepsw. the address of the next instruction fo llowing the instruction executed when a non-maskable interrupt occurs is saved to fepc, except fo r some instructions. the current psw contents are saved to fepsw. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served (fixed to 0) for future function expansion. when the reti instruction has been ex ecuted, the values of fepc and fepsw are restored to the pc and psw, respectively. 31 0 fepc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (3) interrupt source register (ecr) upon occurrence of an interrupt or an exception, the interrupt source register (ecr) holds the source of an interrupt or an exception. the value held by ecr is the exception code coded for each interrupt source. this register is a read-only register, and thus data cannot be written to it using the ldsr instruction. 31 0 ecr fecc eicc after reset 00000000h 16 15 bit position bit name description 31 to 16 fecc non-maskable interrupt (nmi) exception code 15 to 0 eicc exception, maskable interrupt exception code
chapter 3 cpu function user?s manual u16397ej3v0ud 56 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the program st atus (instruction execution result) and the cpu status. when the contents of this register are changed using the ldsr instruction, the new contents become valid immediately following completion of ldsr instruction ex ecution. interrupt request acknowledgment is held pending while a write to the psw is being executed by the ldsr instruction. bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 0 psw rfu after reset 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name description 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that non-maskable interrupt (nmi) servic ing is in progress. this flag is set to 1 when an nmi request is acknowledged, and disables multiple interrupts. 0: nmi servicing not in progress 1: nmi servicing in progress 6 ep indicates that exception processing is in prog ress. this flag is set to 1 when an exception occurs. moreover, interrupt requests can be acknowledged even when this bit is set. 0: exception processing not in progress 1: exception processing in progress 5 id indicates whether maskable interrupt r equest acknowledgment is enabled. 0: interrupt enabled (ei) 1: interrupt disabled (di) 4 sat note indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. this flag is neither set nor cleared when arithmetic operation instructions are executed. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow occu rred as the result of an operation. 0: no carry or borrow occurred 1: carry or borrow occurred 2 ov note indicates whether overflow o ccurred during an operation. 0: no overflow occurred 1: overflow occurred. 1 s note indicates whether the result of an operation is negative. 0: operation result is positive or 0. 1: operation result is negative. 0 z indicates whether operation result is 0. 0: operation result is not 0. 1: operation result is 0. remark note is explained on the following page.
chapter 3 cpu function user?s manual u16397ej3v0ud 57 (2/2) note during saturated operation, the saturated operation results are det ermined by the contents of the ov flag and s flag. the sat flag is set (to 1) only when t he ov flag is set (to 1) during saturated operation. flag status operation result status sat ov s saturated operation result maximum positive value exceeded 1 1 0 7fffffffh maximum negative value exceeded 1 1 1 80000000h positive (maximum value not exceeded) 0 negative (maximum value not exceeded) holds value before operation 0 1 actual operation result (5) callt execution status saving registers (ctpc, ctpsw) there are two callt execut ion status saving registers, ctpc and ctpsw. when the callt instruction is execut ed, the contents of the program co unter (pc) are saved to ctpc, and the program status word (psw) contents are saved to ctpsw. the contents saved to ctpc consist of the address of the next instructi on after the callt instruction. the current psw contents are saved to ctpsw. bits 31 to 26 ctpc and bits 31 to 8 of ctpsw are reserv ed (fixed to 0) for future function expansion. 31 0 ctpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7
chapter 3 cpu function user?s manual u16397ej3v0ud 58 (6) exception/debug trap status saving registers (dbpc, dbpsw) there are two exception/de bug trap status saving registers, dbpc and dbpsw. upon occurrence of an exception trap or debug trap, th e contents of the program co unter (pc) are saved to dbpc, and the program status word (psw) contents are saved to dbpsw. the contents saved to dbpc consist of the address of the next instructi on after the instruction executed when an exception trap or debug trap occurs. the current psw contents are saved to dbpsw. these registers can be read or written only in t he period between dbtrap instruction or illegal opcode execution and dbret instruction execution. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are re served (fixed to 0) for future function expansion. when the dbret instruction has been executed, the values of dbpc and dbpsw are restored to the pc and psw, respectively. 31 0 dbpc (pc contents saved) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (psw contents saved) 0 0 after reset 000000xxh (x: undefined) 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify t able addresses and generate target addresses (bit 0 is fixed to 0). bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 0 ctbp (base address) 0 0 after reset 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 (8) program id register (asid) the asid register sets the id of the program in progress. bits 31 to 8 of this register are reserved for future function expansion (fixed to 0). caution to use the v850e/ma3, initialize the asid re gister to 00h in its initialization routine. 31 0 7 8 asid asid 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 after reset 000000xxh (x: undefined) bit position bit name function 7 to 0 asid id of program under execution
chapter 3 cpu function user?s manual u16397ej3v0ud 59 3.3 operating modes 3.3.1 operating modes the v850e/ma3 has the following operating modes. m ode specification is carri ed out using the mode0 and mode1 pins. (1) normal operation mode (a) single-chip mode access to the internal rom is enabled. in the single-chip mode, after system reset is cleared, each pin related to the bus interface enters the port mode, program execution branches to the reset ent ry address of the internal rom, and instruction processing starts. by setting the pmcal, pm cah, pmcdl, pmccs, pmcct, pmccm, and pmccd registers to the alternate function by instruction, an external device can be connected to the external memory area. (2) flash memory programming mode (flash memory versions only (see table 1-1)) if this mode is specified, programming the on-chip flash memory by the flash programmer is enabled. 3.3.2 operating mode specification the operating mode is specified accordin g to the status of the mode0 and mo de1 pins. in an application system, fix the specification of these pins and do not change them durin g operation. operation is not guaranteed if these pins are changed during operation. mode1 mode0 operation mode remarks l l normal operation mode (single-chip mode) inter nal rom area is allocated from address 000000h. h l flash memory programming mode note ? other than above setting prohibited note flash memory versions only (see table 1-1 ) remark l: low-level input h: high-level input
chapter 3 cpu function user?s manual u16397ej3v0ud 60 3.4 address space 3.4.1 cpu address space the cpu of the v850e/ma3 has 32-bit architecture and supports up to 4 gb of linear address space (data space) during operand addressing (data access). also, in instru ction address addressing, a maximum of 64 mb of linear address space (program space) is supported. figure 3-2 shows the cpu address space. figure 3-2. cpu address space ffffffffh 04000000h 03ffffffh 00000000h data area (4 gb linear) program area (64 mb linear) cpu address space
chapter 3 cpu function user?s manual u16397ej3v0ud 61 3.4.2 image a 256 mb physical address space is seen as 16 images in the 4 gb cpu address space. in actuality, the same 256 mb physical address space is accessed regardless of the va lues of bits 31 to 28 of the cpu address. figure 3-3 shows the image of the virtual addressing space. physical address x0000000h can be seen as cpu address 00000000h, and in addition, can be seen as address 10000000h, address 20000000h, ? , address e0000000h, or address f0000000h. figure 3-3. images on address space ffffffffh f0000000h efffffffh 00000000h internal rom image image image internal ram on-chip peripheral i/o external memory physical address space fffffffh 0000000h image image e0000000h dfffffffh 20000000h 1fffffffh 10000000h 0fffffffh cpu address space
chapter 3 cpu function user?s manual u16397ej3v0ud 62 3.4.3 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counte r), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. even if a carry or borrow occurs from bit 25 to 26 as a re sult of a branch address calculation, the higher 6 bits ignore the carry or borrow. therefore, the upper-limit address of the program space, address 03ffffffh, and the lower-limit address 00000000h become contiguous addresses. wraparound refers to a situation like this whereby the upper-limit address and lower-limit address become contiguous. caution the 4 kb area of 03 fff000h to 03ffffffh can be seen as an image of 0ffff000h to 0fffffffh. this area is access-prohibited. the refore, do not execute any branch address calculation in which the result will r eside in any part of this area. 03fffffeh 03ffffffh 00000000h 00000001h program space program space (+) direction (?) direction (2) data space the result of an operand address calculation that exceeds 32 bits is ignored. therefore, the upper-limit address of the program space, address ffff ffffh, and the lower-limit address 00000000h are contiguous addresses, and the data sp ace is wrapped around at the boundary of these addresses. fffffffeh ffffffffh 00000000h 00000001h data space data space (+) direction (?) direction
chapter 3 cpu function user?s manual u16397ej3v0ud 63 3.4.4 memory map the v850e/ma3 reserves areas as shown in figure 3-4. figure 3-4. memory map on-chip peripheral i/o area internal ram area access prohibited note internal rom area 256 mb 1 mb 4 kb 60 kb xfffffffh xffff000h xfffefffh xfff0000h xffeffffh x0100000h x00fffffh x0000000h note by setting the pmcal, pmcah, pmcdl, pm ccs, pmcct, pmccm, and pmccd registers to the alternate function, this area can be used as external memory area.
chapter 3 cpu function user?s manual u16397ej3v0ud 64 3.4.5 area (1) internal rom area 1 mb of addresses 0000000h to 00fffffh is reserved as an internal rom area. (a) internal rom (256 kb) 256 kb are allocated to addre sses 0000000h to 003ffffh in the following versions. accessing addresses 0040000h to 00fffffh is prohibited. ? pd703131a, 703131ay, 703132a, 703132ay, 703136a, 703136ay figure 3-5. internal rom area (256 kb) access-prohibited area internal rom (256 kb) 0040000h 003ffffh 0000000h 00fffffh (b) internal rom (512 kb) 512 kb are allocated to addre sses 0000000h to 007ffffh in the following versions. accessing addresses 0080000h to 00fffffh is prohibited. ? pd703133a, 703133ay, 703134a, 703134ay, 70f3134a, 70f3134ay figure 3-6. internal rom area (512 kb) access-prohibited area internal rom (512 kb) 0080000h 007ffffh 0000000h 00fffffh
chapter 3 cpu function user?s manual u16397ej3v0ud 65 (2) internal ram area 60 kb of addresses fff0000h to fffefffh are reserved as the internal ram area. (a) internal ram (8 kb) 8 kb are allocated to addresses fffd000h to fffefffh of the following versions. accessing addresses fff0000h to fffcfffh is prohibited. ? pd703136a, 703136ay figure 3-7. internal ram area (8 kb) access-prohibited area internal ram (8 kb) fffd000h fffcfffh fff0000h fffefffh (b) internal ram (16 kb) 16 kb are allocated to addresses fffb000h to fffefffh of the following versions. accessing addresses fff0000h to fffafffh is prohibited. ? pd703131a, 703131ay, 703133a, 703133ay figure 3-8. internal ram area (16 kb) access-prohibited area internal ram (16 kb) fffb000h fffafffh fff0000h fffefffh
chapter 3 cpu function user?s manual u16397ej3v0ud 66 (c) internal ram (32 kb) 32 kb are allocated to addresses fff7000h to fffefffh of the following versions. accessing addresses fff0000h to fff6fffh is prohibited. ? pd703132a, 703132ay, 703134a, 703134ay, 70f3134a, 70f3134ay figure 3-9. internal ram area (32 kb) access-prohibited area internal ram (32 kb) fff7000h fff6fffh fff0000h fffefffh
chapter 3 cpu function user?s manual u16397ej3v0ud 67 (3) on-chip peripheral i/o area 4 kb of memory, addresses ffff000h to fffffffh, is provided as an on-chip peripheral i/o area. an image of addresses ffff000h to fffffffh can be seen at addresses 3fff000h to 3ffffffh note . note addresses 3fff000h to 3ffffffh are access-prohib ited. to access the on-chip peripheral i/o, specify addresses ffff000h to fffffffh. fffffffh ffff000h on-chip peripheral i/o area (4 kb) on-chip peripheral i/o registers associ ated with the operating mode specification and th e state monitoring for the on-chip peripheral i/o are all memo ry-mapped to the on-chip peripheral i/o area. program fetches cannot be executed from this area. cautions 1. in the v850e/ma3, if a register is word accessed, halfword access is performed twice in the order of lower address, then higher addr ess of the word area, disregarding the lower 2 bits of the address. 2. for registers in which byte access is possi ble, if halfword access is executed, the higher 8 bits become undefined during the read opera tion, and the lower 8 bits of data are written to the register during the write operation. 3. addresses that are not defined as registers are reserved for future expansion. if these addresses are accessed, the operation is undefined and not guaranteed. addresses 3fff000h to 3ffffffh cannot be specified as the source/destination address of dma transfer. be sure to use addresses ffff000h to fffffffh for the source/destination address of dma transfer. (4) external memory area 256 mb are available for external memory area. the lower 64 mb can be used as program/data area and the higher 192 mb as data area. access to the external memory area uses the chip sele ct signal assigned to each memory block (access is carried out in the cs unit set by the csc0 and csc1 registers). note that the internal ro m, internal ram, and on-chip peripheral i/o areas cannot be accessed as external memory areas.
chapter 3 cpu function user?s manual u16397ej3v0ud 68 3.4.6 external memory expansion by setting the pmcn register to the al ternate function, an external memory dev ice can be connected to the external memory space using each pin of ports al, ah, dl, cs, ct, cm, and cd. each register is set by selecting the alternate function for each pin of these ports using th e pmcn register (n = al, ah, dl, cs, ct, cm, cd). after reset, since the internal rom area is accessed, each pin of ports al, ah, dl, cs, ct, cm, and cd enters the port mode and external devices cannot be used. to use external memory, set the pmcn register. 3.4.7 recommended use of address space the architecture of the v850e/ma3 r equires that a register that serves as a pointer be secured for address generation in operand data accessing of data space. o perand data access from an in struction can be directly executed at the address in this pointer register 32 kb. however, because the gener al-purpose registers that can be used as a pointer register are limited, by minimizing the deterioration of address calculation performance when changing the pointer value, the number of usable general-pur pose registers for handling variables is maximized, and the program size can be saved. (1) program space of the 32 bits of the program counter (p c), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. therefore, a contiguous 64 mb space, starting from address 00000000h, unconditionally corresponds to the memory map of the program space. (2) data space with the v850e/ma3, a 256 mb physical address spac e is seen as 16 images in the 4 gb cpu address space. the highest bit (bit 25) of this 26-bit address is assigned as an address sign-extended to 32 bits. (a) application of wraparound when r = r0 (zero register) is s pecified by the ld/st disp16 [r] in struction, an addressing range of 00000000h 32 kb can be referenced by the sign-extended disp16. the zero register (r0) is a register set to 0 by the hardware, and eliminates the nee d for additional registers for the pointer. example for pd703132a internal rom area on-chip peripheral i/o area internal ram area 32 kb 28 kb 4 kb 0003ffffh 00007fffh (r =) 00000000h fffff000h ffffefffh ffff8000h ffff7fffh ffff7000h
chapter 3 cpu function user?s manual u16397ej3v0ud 69 figure 3-10. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram external memory internal rom external memory external memory internal ram on-chip peripheral i/o note 1 access prohibited note 2 access prohibited note 2 access prohibited note 2 program space 64 mb internal rom internal rom ffffffffh fffffd92h fffffd91h fffff000h ffffefffh ffff0000h fffeffffh xfffffffh xffffd92h xffffd91h xffff000h xfffefffh xfff0000h xffeffffh x0100000h x00fffffh x0080000h x0000000h x007ffffh xfff7000h xfff6fffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ff7000h 03ff6fffh 03ff0000h 03feffffh 00100000h 000fffffh 00080000h 00000000h 0007ffffh notes 1. this area is access-prohibited. to access t he on-chip peripheral i/o, specify addresses ffff000h to fffffffh. 2. the operation is not guaranteed if an a ccess-prohibited area is accessed. remarks 1. the arrows indicate the recommended area. 2. this is a recommended memory map when the pd703134a is set to the single-chip mode, and used in external expansion mode.
chapter 3 cpu function user?s manual u16397ej3v0ud 70 3.4.8 on-chip peripheral i/o registers (1/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff000h port al register pal r/w undefined fffff000h port all register pall r/w undefined fffff001h port alh register palh r/w undefined fffff002h port ah register pah r/w undefined fffff002h port ahl register pahl r/w undefined fffff003h port ahh register pahh r/w undefined fffff004h port dl register pdl r/w undefined fffff004h port dll register pdll r/w undefined fffff005h port dlh register pdlh r/w undefined fffff008h port cs register pcs r/w undefined fffff00ah port ct register pct r/w undefined fffff00ch port cm register pcm r/w undefined fffff00eh port cd register pcd r/w undefined fffff012h port bd register pbd r/w undefined fffff020h port al mode register pmal r/w ffffh fffff020h port al mode register l pmall r/w ffh fffff021h port al mode register h pmalh r/w ffh fffff022h port ah mode register pmah r/w ffffh fffff022h port ah mode register l pmahl r/w ffh fffff023h port ah mode register h pmahh r/w ffh fffff024h port dl mode register pmdl r/w ffffh fffff024h port dl mode register l pmdll r/w ffh fffff025h port dl mode register h pmdlh r/w ffh fffff028h port cs mode register pmcs r/w ffh fffff02ah port ct mode register pmct r/w ffh fffff02ch port cm mode register pmcm r/w ffh fffff02eh port cd mode register pmcd r/w ffh fffff032h port bd mode register pmbd r/w ffh fffff040h port al mode control register pmcal r/w 0000h fffff040h port al mode control register l pmcall r/w 00h fffff041h port al mode control register h pmcalh r/w 00h fffff042h port ah mode control register pmcah r/w 0000h fffff042h port ah mode control register l pmcahl r/w 00h fffff043h port ah mode control register h pmcahh r/w 00h fffff044h port dl mode control register pmcdl r/w 0000h fffff044h port dl mode control register l pmcdll r/w 00h fffff045h port dl mode control register h pmcdlh r/w 00h
chapter 3 cpu function user?s manual u16397ej3v0ud 71 (2/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff048h port cs mode control register pmccs r/w 00h fffff049h port cs function control register pfccs r/w 00h fffff04ah port ct mode control register pmcct r/w 00h fffff04bh port ct function control register pfcct r/w 00h fffff04ch port cm mode control register pmccm r/w 00h fffff04eh port cd mode control register pmccd r/w 00h fffff052h port bd mode control register pmcbd r/w 00h fffff060h chip area select control register 0 csc0 r/w 2c11h fffff062h chip area select control register 1 csc1 r/w 2c11h fffff068h endian configuration register bec r/w 0000h fffff06eh system wait control register vswc r/w 77h fffff080h dma source address register 0l dsa0l r/w undefined fffff082h dma source address register 0h dsa0h r/w undefined fffff084h dma destination address register 0l dda0l r/w undefined fffff086h dma destination address register 0h dda0h r/w undefined fffff088h dma source address register 1l dsa1l r/w undefined fffff08ah dma source address register 1h dsa1h r/w undefined fffff08ch dma destination address register 1l dda1l r/w undefined fffff08eh dma destination address register 1h dda1h r/w undefined fffff090h dma source address register 2l dsa2l r/w undefined fffff092h dma source address register 2h dsa2h r/w undefined fffff094h dma destination address register 2l dda2l r/w undefined fffff096h dma destination address register 2h dda2h r/w undefined fffff098h dma source address register 3l dsa3l r/w undefined fffff09ah dma source address register 3h dsa3h r/w undefined fffff09ch dma destination address register 3l dda3l r/w undefined fffff09eh dma destination address register 3h dda3h r/w undefined fffff0c0h dma transfer count register 0 dbc0 r/w undefined fffff0c2h dma transfer count register 1 dbc1 r/w undefined fffff0c4h dma transfer count register 2 dbc2 r/w undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined fffff0d0h dma addressing control register 0 dadc0 r/w 0000h fffff0d2h dma addressing control register 1 dadc1 r/w 0000h fffff0d4h dma addressing control register 2 dadc2 r/w 0000h fffff0d6h dma addressing control register 3 dadc3 r/w 0000h fffff0e0h dma channel control register 0 dchc0 r/w 00h fffff0e2h dma channel control register 1 dchc1 r/w 00h fffff0e4h dma channel control register 2 dchc2 r/w 00h fffff0e6h dma channel control register 3 dchc3 r/w 00h
chapter 3 cpu function user?s manual u16397ej3v0ud 72 (3/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff100h interrupt mask register 0 imr0 r/w ffffh fffff100h interrupt mask register 0l imr0l r/w ffh fffff101h interrupt mask register 0h imr0h r/w ffh fffff102h interrupt mask register 1 imr1 r/w ffffh fffff102h interrupt mask register 1l imr1l r/w ffh fffff103h interrupt mask register 1h imr1h r/w ffh fffff104h interrupt mask register 2 imr2 r/w ffffh fffff104h interrupt mask register 2l imr2l r/w ffh fffff105h interrupt mask register 2h imr2h r/w ffh fffff106h interrupt mask register 3 imr3 r/w ffffh fffff106h interrupt mask register 3l imr3l r/w ffh fffff107h interrupt mask register 3h imr3h r/w ffh fffff110h interrupt control register 0 wdtic r/w 47h fffff112h interrupt control register 1 p00ic0 r/w 47h fffff114h interrupt control register 2 p00ic1 r/w 47h fffff116h interrupt control register 3 p00ic4 r/w 47h fffff118h interrupt control register 4 p00ic5 r/w 47h fffff11ah interrupt control register 5 p10ic6 r/w 47h fffff11ch interrupt control register 6 p10ic7 r/w 47h fffff11eh interrupt control register 7 p01ic0 r/w 47h fffff120h interrupt control register 8 p01ic1 r/w 47h fffff122h interrupt control register 9 p01ic2 r/w 47h fffff124h interrupt control register 10 p01ic3 r/w 47h fffff126h interrupt control register 11 p11ic4 r/w 47h fffff128h interrupt control register 12 p11ic5 r/w 47h fffff12ah interrupt control register 13 p02ic1 r/w 47h fffff12ch interrupt control register 14 p02ic2 r/w 47h fffff12eh interrupt control register 15 p12ic4 r/w 47h fffff130h interrupt control register 16 p12ic5 r/w 47h fffff132h interrupt control register 17 p12ic6 r/w 47h fffff134h interrupt control register 18 p13ic0 r/w 47h fffff136h interrupt control register 19 p13ic1 r/w 47h fffff138h interrupt control register 20 p13ic2 r/w 47h fffff13ah interrupt control register 21 p13ic3 r/w 47h fffff13ch interrupt control register 22 p13ic4 r/w 47h fffff13eh interrupt control register 23 p13ic7 r/w 47h fffff140h interrupt control register 24 p05ic0 r/w 47h
chapter 3 cpu function user?s manual u16397ej3v0ud 73 (4/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff142h interrupt control register 25 p05ic1 r/w 47h fffff144h interrupt control register 26 cmicd0 r/w 47h fffff146h interrupt control register 27 cmicd1 r/w 47h fffff148h interrupt control register 28 cmicd2 r/w 47h fffff14ah interrupt control register 29 cmicd3 r/w 47h fffff14ch interrupt control register 30 cm10ic0 r/w 47h fffff14eh interrupt control register 31 cm10ic1 r/w 47h fffff150h interrupt control register 32 ovpic0 r/w 47h fffff152h interrupt control register 33 ovqic r/w 47h fffff154h interrupt control register 34 ovpic1 r/w 47h fffff156h interrupt control register 35 ovpic2 r/w 47h fffff158h interrupt control register 36 dmaic0 r/w 47h fffff15ah interrupt control register 37 dmaic1 r/w 47h fffff15ch interrupt control register 38 dmaic2 r/w 47h fffff15eh interrupt control register 39 dmaic3 r/w 47h fffff160h interrupt control register 40 seic0 r/w 47h fffff162h interrupt control register 41 sric0 r/w 47h fffff164h interrupt control register 42 stic0 r/w 47h fffff166h interrupt control register 43 seic1 r/w 47h fffff168h interrupt control register 44 sric1 r/w 47h fffff16ah interrupt control register 45 stic1 r/w 47h fffff16ch interrupt control register 46 seic2 r/w 47h fffff16eh interrupt control register 47 sric2 r/w 47h fffff170h interrupt control register 48 stic2 r/w 47h fffff172h interrupt control register 49 seic3 r/w 47h fffff174h interrupt control register 50 sric3 r/w 47h fffff176h interrupt control register 51 stic3 r/w 47h fffff178h interrupt control register 52 adic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc r/w 00h fffff200h a/d converter mode register 0 adm0 r/w 00h fffff201h a/d converter mode register 1 adm1 r/w 07h fffff202h a/d converter mode register 2 adm2 r/w 02h fffff210h a/d conversion result register 0 (10bit) adcr0 r 0000h fffff212h a/d conversion result register 1 (10bit) adcr1 r 0000h fffff214h a/d conversion result register 2 (10bit) adcr2 r 0000h fffff216h a/d conversion result register 3 (10bit) adcr3 r 0000h fffff218h a/d conversion result register 4 (10bit) adcr4 r 0000h
chapter 3 cpu function user?s manual u16397ej3v0ud 74 (5/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff21ah a/d conversion result register 5 (10bit) adcr5 r 0000h fffff21ch a/d conversion result register 6 (10bit) adcr6 r 0000h fffff21eh a/d conversion result register 7 (10bit) adcr7 r 0000h fffff220h a/d conversion result register 0h (8bit) adcr0h r 00h fffff221h a/d conversion result register 1h (8bit) adcr1h r 00h fffff222h a/d conversion result register 2h (8bit) adcr2h r 00h fffff223h a/d conversion result register 3h (8bit) adcr3h r 00h fffff224h a/d conversion result register 4h (8bit) adcr4h r 00h fffff225h a/d conversion result register 5h (8bit) adcr5h r 00h fffff226h a/d conversion result register 6h (8bit) adcr6h r 00h fffff227h a/d conversion result register 7h (8bit) adcr7h r 00h fffff288h a/d trigger select register adts r/w 01h fffff2c0h d/a conversion value setting register 0 da0cs0 r/w 00h fffff2c1h d/a conversion value setting register 1 da0cs1 r/w 00h fffff2c2h d/a converter mode register da0m r/w 00h fffff400h port 0 register p0 r/w undefined fffff402h port 1 register p1 r/w undefined fffff404h port 2 register p2 r/w undefined fffff406h port 3 register p3 r/w undefined fffff408h port 4 register p4 r/w undefined fffff40ah port 5 register p5 r/w undefined fffff40eh port 7 register p7 r undefined fffff410h port 8 register p8 r undefined fffff420h port 0 mode register pm0 r/w ffh fffff422h port 1 mode register pm1 r/w ffh fffff424h port 2 mode register pm2 r/w ffh fffff426h port 3 mode register pm3 r/w ffh fffff428h port 4 mode register pm4 r/w ffh fffff42ah port 5 mode register pm5 r/w ffh fffff440h port 0 mode control register pmc0 r/w 00h fffff442h port 1 mode control register pmc1 r/w 00h fffff444h port 2 mode control register pmc2 r/w 01h fffff446h port 3 mode control register pmc3 r/w 00h fffff448h port 4 mode control register pmc4 r/w 00h fffff44ah port 5 mode control register pmc5 r/w 00h fffff44eh port 7 mode control register pmc7 r/w 00h fffff460h port 0 function control register pfc0 r/w 00h fffff462h port 1 function control register pfc1 r/w 00h
chapter 3 cpu function user?s manual u16397ej3v0ud 75 (6/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff464h port 2 function control register pfc2 r/w 00h fffff466h port 3 function control register pfc3 r/w 00h fffff468h port 4 function control register pfc4 r/w 00h fffff46ah port 5 function control register pfc5 r/w 00h fffff480h bus cycle type configuration register 0 bct0 r/w 8888h fffff482h bus cycle type configuration register 1 bct1 r/w 8888h fffff484h data wait control register 0 dwc0 r/w 7777h fffff486h data wait control register 1 dwc1 r/w 7777h fffff488h bus cycle control register bcc r/w ffffh fffff48ah address setup wait control register asc r/w ffffh fffff48ch bus cycle period control register bcp r/w 00h fffff48eh local bus sizing control register lbs r/w 5555h fffff494h dma flyby transfer wait control register fwc r/w 7777h fffff496h dma flyby transfer idle control register fic r/w 3333h fffff498h bus mode control register bmc r/w 01h fffff49ah page rom configuration register prc r/w 7000h fffff49ch write access synchronization control register was w 00h fffff49eh address hold wait control register ahc r/w ffffh fffff4a4h sdram configuration register 1 scr1 r/w 30c0h fffff4a6h sdram refresh control register 1 rfs1 r/w 0000h fffff4ach sdram configuration register 3 scr3 r/w 30c0h fffff4aeh sdram refresh control register 3 rfs3 r/w 0000h fffff4b0h sdram configuration register 4 scr4 r/w 30c0h fffff4b2h sdram refresh control register 4 rfs4 r/w 0000h fffff4b8h sdram configuration register 6 scr6 r/w 30c0h fffff4bah sdram refresh control register 6 rfs6 r/w 0000h fffff540h timer d0 tmd0 r 0000h fffff542h compare register d0 cmd0 r/w 0000h fffff544h timer mode control register d0 tmcd0 r/w 00h fffff550h timer d1 tmd1 r 0000h fffff552h compare register d1 cmd1 r/w 0000h fffff554h timer mode control register d1 tmcd1 r/w 00h fffff560h timer d2 tmd2 r 0000h fffff562h compare register d2 cmd2 r/w 0000h fffff564h timer mode control register d2 tmcd2 r/w 00h fffff570h timer d3 tmd3 r 0000h fffff572h compare register d3 cmd3 r/w 0000h
chapter 3 cpu function user?s manual u16397ej3v0ud 76 (7/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff574h timer mode control register d3 tmcd3 r/w 00h fffff5c0h timer enc10 tmenc10 r/w 0000h fffff5c2h compare register 100 cm100 r/w 0000h fffff5c4h compare register 101 cm101 r/w 0000h fffff5c6h capture/compare register 100 cc100 r/w 0000h fffff5c8h capture/compare register 101 cc101 r/w 0000h fffff5cah capture/compare control register 10 ccr10 r/w 00h fffff5cbh timer unit mode register 10 tum10 r/w 00h fffff5cch timer control register 10 tmc10 r/w 00h fffff5cdh valid edge select register 10 sesa10 r/w 00h fffff5ceh prescaler mode register 10 prm10 r/w 07h fffff5cfh status register 10 status10 r 00h fffff600h tmq0 control register 0 tq0ctl0 r/w 00h fffff601h tmq0 control register 1 tq0ctl1 r/w 00h fffff602h tmq0 i/o control register 0 tq0ioc0 r/w 00h fffff603h tmq0 i/o control register 1 tq0ioc1 r/w 00h fffff604h tmq0 i/o control register 2 tq0ioc2 r/w 00h fffff605h tmq0 option register 0 tq0opt0 r/w 00h fffff606h tmq0 capture/compare register 0 tq0ccr0 r/w 0000h fffff608h tmq0 capture/compare register 1 tq0ccr1 r/w 0000h fffff60ah tmq0 capture/compare register 2 tq0ccr2 r/w 0000h fffff60ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff60eh tmq0 counter read buffer register tq0cnt r 0000h fffff620h tmq0 option register 1 tq0opt1 r/w 00h fffff621h tmq0 option register 2 tq0opt2 r/w 00h fffff622h tmq0 i/o control register 3 tq0ioc3 r/w a8h fffff624h tmq0 dead time compare register tq0dtc r/w 0000h fffff630h high-impedance output control register 0 hza0ctl0 r/w 00h fffff631h high-impedance output control register 1 hza0ctl1 r/w 00h fffff640h tmp0 control register 0 tp0ctl0 r/w 00h fffff641h tmp0 control register 1 tp0ctl1 r/w 00h fffff642h tmp0 i/o control register 0 tp0ioc0 r/w 00h fffff643h tmp0 i/o control register 1 tp0ioc1 r/w 00h fffff644h tmp0 i/o control register 2 tp0ioc2 r/w 00h fffff645h tmp0 option register 0 tp0opt0 r/w 00h fffff646h tmp0 capture/compare register 0 tp0ccr0 r/w 0000h fffff648h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff64ah tmp0 counter read buffer register tp0cnt r 0000h
chapter 3 cpu function user?s manual u16397ej3v0ud 77 (8/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffff660h tmp1 control register 0 tp1ctl0 r/w 00h fffff661h tmp1 control register 1 tp1ctl1 r/w 00h fffff662h tmp1 i/o control register 0 tp1ioc0 r/w 00h fffff663h tmp1 i/o control register 1 tp1ioc1 r/w 00h fffff664h tmp1 i/o control register 2 tp1ioc2 r/w 00h fffff665h tmp1 option register 0 tp1opt0 r/w 00h fffff666h tmp1 capture/compare register 0 tp1ccr0 r/w 0000h fffff668h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff66ah tmp1 counter read buffer register tp1cnt r 0000h fffff680h tmp2 control register 0 tp2ctl0 r/w 00h fffff681h tmp2 control register 1 tp2ctl1 r/w 00h fffff682h tmp2 i/o control register 0 tp2ioc0 r/w 00h fffff683h tmp2 i/o control register 1 tp2ioc1 r/w 00h fffff684h tmp2 i/o control register 2 tp2ioc2 r/w 00h fffff685h tmp2 option register 0 tp2opt0 r/w 00h fffff686h tmp2 capture/compare register 0 tp2ccr0 r/w 0000h fffff688h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff68ah tmp2 counter read buffer register tp2cnt r 0000h fffff6c0h oscillation stabilization time select register osts r/w 01h fffff6c1h watchdog timer clock se lect register wdcs r/w 00h fffff6c2h watchdog timer mode register wdtm r/w 00h fffff700h port 0 function control expansion register pfce0 r/w 00h fffff702h port 1 function control expansion register pfce1 r/w 00h fffff704h port 2 function control expansion register pfce2 r/w 00h fffff706h port 3 function control expansion register pfce3 r/w 00h fffff70ah port 5 function control expansion register pfce5 r/w 00h fffff802h system status register sys r/w 00h fffff804h chip select signal delay control register csdc r/w 00h fffff810h dma trigger factor register 0 dtfr0 r/w note 1 00h fffff812h dma trigger factor register 1 dtfr1 r/w note 1 00h fffff814h dma trigger factor register 2 dtfr2 r/w note 1 00h fffff816h dma trigger factor register 3 dtfr3 r/w note 1 00h fffff820h power save mode register psmr r/w 00h fffff822h clock control register ckc r/w 00h fffff828h processor clock control register pcc r/w 00h fffff82ah watchdog timer reset status register wdres r/w note 2 00h notes 1. only the seventh bit can be manipulated in bit units. 2. this register can be manipulated in bit units only when it is read.
chapter 3 cpu function user?s manual u16397ej3v0ud 78 (9/11) bit units for manipulation address function register name symbol r/w 1 8 16 32 after reset fffff840h correction address register 0 corad0 r/w 00000000h fffff840h correction address register 0l corad0l r/w 0000h fffff842h correction address register 0h corad0h r/w 0000h fffff844h correction address register 1 corad1 r/w 00000000h fffff844h correction address register 1l corad1l r/w 0000h fffff846h correction address register 1h corad1h r/w 0000h fffff848h correction address register 2 corad2 r/w 00000000h fffff848h correction address register 2l corad2l r/w 0000h fffff84ah correction address regi ster 2h corad2h r/w 0000h fffff84ch correction address register 3 corad3 r/w 00000000h fffff84ch correction address register 3l corad3l r/w 0000h fffff84eh correction address regi ster 3h corad3h r/w 0000h fffff880h correction control register corcn r/w 00h fffff8a0h dma terminal count output control register dtoc r/w 01h fffff8a8h dma interface control register difc r/w 00h fffff8ach dmaak width control register dakw r/w 00h fffffa00h uarta0 control register 0 ua0ctl0 r/w 10h fffffa01h uarta0 control register 1 ua0ctl1 r/w 00h fffffa02h uarta0 control register 2 ua0ctl2 r/w ffh fffffa03h uarta0 option control register 0 ua0opt0 r/w 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx r/w ffh fffffa10h uarta1 control register 0 ua1ctl0 r/w 10h fffffa11h uarta1 control register 1 ua1ctl1 r/w 00h fffffa12h uarta1 control register 2 ua1ctl2 r/w ffh fffffa13h uarta1 option control register 0 ua1opt0 r/w 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 transmit data register ua1tx r/w ffh fffffa20h uarta2 control register 0 ua2ctl0 r/w 10h fffffa21h uarta2 control register 1 ua2ctl1 r/w 00h fffffa22h uarta2 control register 2 ua2ctl2 r/w ffh fffffa23h uarta2 option control register 0 ua2opt0 r/w 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx r/w ffh fffffa30h uarta3 control register 0 ua3ctl0 r/w 10h
chapter 3 cpu function user?s manual u16397ej3v0ud 79 (10/11) bit units for manipulation address function register name symbol r/w 1 8 16 32 after reset fffffa31h uarta3 control register 1 ua3ctl1 r/w 00h fffffa32h uarta3 control register 2 ua3ctl2 r/w ffh fffffa33h uarta3 option control register 0 ua3opt0 r/w 14h fffffa34h uarta3 status register ua3str r/w 00h fffffa36h uarta3 receive data register ua3rx r ffh fffffa37h uarta3 transmit data register ua3tx r/w ffh fffffc00h external interrupt falling edge specification register 0 intf0 r/w f3h fffffc02h external interrupt falling edge specification register 1 intf1 r/w 3fh fffffc04h external interrupt falling edge specification register 2 intf2 r/w 76h fffffc06h external interrupt falling edge specification register 3 intf3 r/w 9fh fffffc0ah external interrupt falling edge specification register 5 intf5 r/w 03h fffffc1eh nmi falling edge specification register nmif r/w 00h fffffc20h external interrupt rising edge specification register 0 intr0 r/w 00h fffffc22h external interrupt rising edge specification register 1 intr1 r/w 00h fffffc24h external interrupt rising edge specification register 2 intr2 r/w 00h fffffc26h external interrupt rising edge specification register 3 intr3 r/w 00h fffffc2ah external interrupt rising edge specification register 5 intr5 r/w 00h fffffc3eh nmi rising edge specification register nmir r/w 00h fffffd00h csib0 control register 0 cb0ctl0 r/w 01h fffffd01h csib0 control register 1 cb0ctl1 r/w 00h fffffd02h csib0 control register 2 cb0ctl2 r/w 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register (16 bits) cb0rx r 0000h fffffd04h csib0 receive data register l (8 bits) cb0rxl r 00h fffffd06h csib0 transmit data register (16 bits) cb0tx r/w 0000h fffffd06h csib0 transmit data register l (8 bits) cb0txl r/w 00h fffffd10h csib1 control register 0 cb1ctl0 r/w 01h fffffd11h csib1 control register 1 cb1ctl1 r/w 00h fffffd12h csib1 control register 2 cb1ctl2 r/w 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register (16 bits) cb1rx r 0000h fffffd14h csib1 receive data register l (8 bits) cb1rxl r 00h fffffd16h csib1 transmit data register (16 bits) cb1tx r/w 0000h fffffd16h csib1 transmit data register l (8 bits) cb1txl r/w 00h fffffd20h csib2 control register 0 cb2ctl0 r/w 01h fffffd21h csib2 control register 1 cb2ctl1 r/w 00h fffffd22h csib2 control register 2 cb2ctl2 r/w 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register (16 bits) cb2rx r 0000h fffffd24h csib2 receive data register l (8 bits) cb2rxl r 00h fffffd26h csib2 transmit data register (16 bits) cb2tx r/w 0000h fffffd26h csib2 transmit data register l (8 bits) cb2txl r/w 00h
chapter 3 cpu function user?s manual u16397ej3v0ud 80 (11/11) bit units for manipulation address function register name symbol r/w 1 8 16 after reset fffffd80h iic shift register note iic r/w 00h fffffd82h iic control register note iicc r/w 00h fffffd83h slave address register note sva r/w 00h fffffd84h iic clock select register note iiccl r/w 00h fffffd85h iic function expansion register note iicx r/w 00h fffffd86h iic status register note iics r 00h fffffd8ah iic flag register note iicf r/w 00h fffffd90h prescaler mode register note prsm r/w 00h fffffd91h prescaler compare register note prscm r/w 00h note i 2 c bus versions (y products) only (see table 1-1)
chapter 3 cpu function user?s manual u16397ej3v0ud 81 3.4.9 special registers special registers are registers that ar e protected from being written with illegal data due to a program hang-up. the v850e/ma3 has the following five special registers. ? power save control register (psc) ? processor clock control register (pcc) ? clock control register (ckc) ? watchdog timer mode register (wdtm) ? watchdog timer reset status register (wdres) in addition, a command register (prcdm) is provided to pr otect against a write access to the special registers so that the application system d oes not inadvertently stop due to a progra m hang-up. a write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the s ystem status register (sys). (1) setting data to special registers set data to the special registers in the following sequence. <1> prepare the data to be set to the spec ial register in a general-purpose register. <2> write the data prepared in step <1> to the prcmd register. <3> write the setting data to the special re gister (using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) [example] when using ckc register (system clock setting) <1> mov 0x03, r10 <2> st.b r10, prcmd[r0] ; write prcmd register. <3> st.b r10, ckc[r0] ; set ckc register. (next instruction) no special sequence is necessary for reading a specific register. cautions 1. a store instruction for the prcmd register does not acknowledge interrupts. this coding is made on assumption that <2> and <3> above are executed by the program with consecutive store instructions. if another in struction is set between <2> and <3>, the above sequence may become ineffective when the interrupt is acknowledged by that instruction, and a malfunction of the program may result. 2. although the data written to the prcmd re gister is dummy data, use the same register as the general-purpose register u sed in setting the special regi ster (<3> in [example]) by using the store instruction for writing to th e prcmd register (<2> in [example]). the same method should be applied when using a general-purpose register for addressing. an example of setting the special register (< 3> in example) by using the bit manipulation instruction is shown below. clr1 0, wdres[r0] 3. before executing this processing, terminate all dma tr ansfer operations. 4. to set the idle mode or software stop m ode (psc.stb bit = 1), se e 21.7 procedure for setting or restoring from idle and software stop modes.
chapter 3 cpu function user?s manual u16397ej3v0ud 82 (2) command register (prcmd) the prcmd register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. the first write access to a special register (psc register) is valid after data has been written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch
chapter 3 cpu function user?s manual u16397ej3v0ud 83 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 protection error did not occur. protection error occurred. prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <3> is executed without executing <2> in 3.4.9 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o register other than a spec ial register (including execution of a bit manipulation instruction) afte r writing data to the prcmd register (if <3> in 3.4.9 (1) setting data to special registers is not the setting of a special register) (iii) when 1 is written to the prerr flag remark even if an on-chip peripheral i/o register is r ead (including execution of a bit manipulation instruction) between a write access to the p rcmd register and a write access to a special register other than the wdtm register (pcc , psc, ckc, and wdres registers) (such as an access to the internal ram), the prerr flag is not set and data can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcmd register, the pr err bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd register, which is not a special re gister, immediately after a write access to the prcmd regist er, the prerr bit is set to 1.
chapter 3 cpu function user?s manual u16397ej3v0ud 84 3.4.10 system wait control register (vswc) the vswc register is a register that controls the bus access wait for the on-chip peripheral i/o registers. access to on-chip peripheral i/o registers of the v850e1 cp u core is basically made in 3 clocks; however, in the v850e/ma3, waits may be required in addition to those 3 clocks. set the values shown below to the vswc register according to the operating frequency that is used. this register can be read or written in 8-bit units (address: fffff06eh, initial value: 77h). operating frequency (f cpu ) set value of vswc number of waits for on-chip peripheral i/o register access 5 mhz f cpu 33 mhz 11h 2 33 mhz < f cpu 50 mhz 12h 3 50 mhz < f cpu 80 mhz 24h 6 remark when a register the includes status flags that indi cate the statuses of the on-chip peripheral functions (register such as the status10 regist er) or a register (tmenc10, etc.) that indicates the count value of a timer is accessed, a register access retry operat ion takes place if the ti ming at which the flag and count value changes and the timing of the register ac cess overlap. consequently, access to the on-chip peripheral i/o register ma y take a long time. 3.4.11 cautions (1) registers to be set first when using the v850e/ma3, the following registers must be set in the beginning. ? system wait control register (vswc) (see 3.4.10 system wait control register (vswc) ) ? clock control register (ckc) (see 7.3 (2) clock control register (ckc) ) ? program id register (asid) (see 3.2.2 (8) program id register (asid) .) after setting vswc, ckc, and asid set other registers as necessary. to use the external bus, initialize each register in the following sequence after setting the above registers. <1> set each pin to the alternate-function mode by setting each port-related register. <2> select a chip select space by using cscn register (n = 0, 1). <3> specify the type of memory of each ch ip select space by using bctn register.
chapter 3 cpu function user?s manual u16397ej3v0ud 85 (2) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an in terrupt request before the instruction in <1> is complete, the execution result of the instru ction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mov instruction immediately before the sld instruction and an interrupt reques t conflict before execution of the ld instruction is complete, the executio n result of instruction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 (b) countermeasure <1> when compiler (ca850) is used use ca850 ver. 2.61 or later because generation of the corresponding instruction sequence can be automatically suppressed. <2> for assembler when executing the sld instruction immediately afte r instruction , avoid the above operation using either of the following methods. ? insert a nop instruction immediat ely before the sld instruction. ? do not use the same register as the sld instruct ion destination register in the above instruction executed immediately befor e the sld instruction. ? ? ?
user?s manual u16397ej3v0ud 86 chapter 4 port functions 4.1 features ? i/o ports: 112 ? input and output can be specified in 1-bit units.
chapter 4 port functions user?s manual u16397ej3v0ud 87 4.2 port basic configuration the v850e/ma3 incorporates a total of 112 i/o ports labeled ports 0 to 5, 7, 8, al, ah, dl, cs, ct, cm, cd, and bd. the port configuration is shown below. figure 4-1. port configuration port 0 p00 port 1 p10 p15 port 2 p21 p34 p01 p04 p07 p20 p22 p27 port 3 p30 p37 port 4 p40 p45 port 5 p50 p51 port 7 p70 p77 port al port ah pal0 pal15 pah0 pah9 port dl port cs port ct port cm pdl0 pdl15 pcs0 pcs7 pct0 pct1 pct4 pct7 pcm0 pcm4 port cd pcd0 pcd3 port bd pbd0 pbd3 port 8 p80 p81 p24
chapter 4 port functions user?s manual u16397ej3v0ud 88 4.3 port configuration table 4-1. port configuration item configuration control registers port n register (pn: n = 0 to 5, 7, 8, al, ah, dl, cs, ct, cm, cd, bd) port n mode register (pmn: n = 0 to 5, al, ah, dl, cs, ct, cm, cd, bd) port n mode control register (pmcn: n = 0 to 5, 7, al, ah, dl, cs, ct, cm, cd, bd) port n function control register (pfcn: n = 0 to 5, cs, ct) port 1 function control expansion register (pfcen: n = 0 to 3, 5) ports input-only: 11 i/o: 101 (1) port n register (pn) data is input from or output to an external device by writing or reading the pn register. the pn register consists of a port latch that holds output data, and a circ uit that reads the status of pins. each bit of the pn register corresponds to one pin of port n, and can be read or written in 1-bit units. pn7 output 0. output 1. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: undefined r/w data is written to or read from the pn register as follows, according to each register setting. table 4-2. writing/reading pn register setting of pmcn register setting of pmn register writing to pn register reading from pn register output mode (pmnm bit = 0) data is written to the output latch note . the contents of the output latch are output from the pins. the value of the output latch is read. port mode (pmcnm bit = 0) input mode (pmnm bit = 1) data is written to the output latch note . the pin status is not affected. the pin status is read. output mode (pmnm bit = 0) the output status of the alternate function is read. alternate-function mode (pmcnm bit = 1) input mode (pmnm bit = 1) data is written to the output latch note . the pin status is not affected. the pin operates as an alternate- function pin. the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch.
chapter 4 port functions user?s manual u16397ej3v0ud 89 (2) port n mode register (pmn) the pmn register specifies the input or output mode of the corresponding port pin. each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of input/output mode (in port mode) pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the pmcn register specifies the port mode or alternate function. each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. port mode alternate function pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h note r/w note 01h for pmc2 register
chapter 4 port functions user?s manual u16397ej3v0ud 90 (4) port n function control expansion register (pfcen) the pfcen register specifies the alte rnate function of a port pin to be used if the pin has three or more alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 (5) port n function control register (pfcn) the pfcn register specifies the alternat e function of a port pin to be used if the pin has two alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function
chapter 4 port functions user?s manual u16397ej3v0ud 91 (6) port settings set the ports as follows. figure 4-2. register settings and pin functions pmcn register output mode input mode pmn register "0" "1" "0" "1" "0" "1" (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark for switching to the alternate function, see 4.6.1 (1) procedure to ch ange mode fr om port mode to alternate-function mode .
chapter 4 port functions user?s manual u16397ej3v0ud 92 4.3.1 port 0 port 0 can be set to the input or output mode in 1-bit units. port 0 has an alternate function as the following pins. table 4-3. alternate-function pins of port 0 pin no. pin name gj f1 alternate-function pin i/o p00 19 g2 intp000/top00/evtp0/tip0/intpp00 p01 18 g1 intp001/top01/intpp01 p04 33 m3 intp004/dmarq0/intp11/tclr10 p05 34 m2 intp005/dmarq1/intp10/tcud10 p06 35 l3 intp106/dmarq2/tms note p07 36 n2 intp107/dmarq3/tck note i/o note the tms and tck pins are for on-chip debugging. to use the p06 and p07 pins as p06/intp106/dmarq2 and p07/intp107/dmarq3, be sure to input a low level to the trst pin. if a high level is input to the trst pin, the values set to the p0, pm0, pmc0, and pfc0 registers become invalid, and the p06 and p07 pins function as the tms and tck pins. caution p00, p01, and p04 to p07 have hysteresi s characteristics when th eir alternate function is used in the input mode, but not when they are used in the port mode. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 4 port functions user?s manual u16397ej3v0ud 93 (1) registers (a) port 0 register (p0) p07 output 0. output 1. p0n 0 1 control of output data (in output mode) ( n = 0, 1, 4 to 7) p0 p06 p05 p04 0 0 p01 p00 after reset: undefined r/w address: fffff400h (b) port 0 mode register (pm0) pm07 output mode input mode pm0n 0 1 control of input/output mode (in port mode) ( n = 0, 1, 4 to 7) pm0 pm06 pm05 pm04 1 1 pm01 pm00 after reset: ffh r/w address: fffff420h
chapter 4 port functions user?s manual u16397ej3v0ud 94 (c) port 0 mode control register (pmc0) pmc07 pmc0 pmc06 pmc05 pmc04 0 0 pmc01 pmc00 i/o port intp107 input/dmarq3 input pmc07 0 1 specification of operation mode of p07 pin specification of operation mode of p06 pin specification of operation mode of p05 pin specification of operation mode of p04 pin specification of operation mode of p01 pin specification of operation mode of p00 pin i/o port intp106 input/dmarq2 input pmc06 0 1 i/o port intp005 input/dmarq1 input/intp10 input/tcud10 input pmc05 0 1 i/o port intp004 input/dmarq0 input/intp11 input/tclr10 input pmc04 0 1 i/o port intp001 input/top01 output/intpp01 input pmc01 0 1 i/o port intp000 input/top00 output/evtp0 input/tip0 input/intpp00 input pmc00 0 1 after reset: 00h r/w address: fffff440h caution the p06/intp106/dmarq2 pin functions alternately as the n-wire control signal tms, and the p07/intp107/dmarq3 pin functions alternately as the n-wire control signal tck. these alternate functions cannot be debugged when the n-wire type emulator is used.
chapter 4 port functions user?s manual u16397ej3v0ud 95 (d) port 0 function contro l expansion register (pfce0) 0 pfce0 0 pfce05 pfce04 0 0 pfce01 pfce00 after reset: 00h r/w address: fffff700h remark for the specification of the alternate function, see 4.3.1 (1) (f) setting of alternate functions of port 0 pins . (e) port 0 function control register (pfc0) pfc07 pfc0 pfc06 pfc05 pfc04 0 0 pfc01 pfc00 after reset: 00h r/w address: fffff460h remark for the specification of the alternate function, see 4.3.1 (1) (f) setting of alternate functions of port 0 pins .
chapter 4 port functions user?s manual u16397ej3v0ud 96 (f) setting of alternate functions of port 0 pins pfc07 specification of alternate function of p07 pin 0 intp107 input 1 dmarq3 input pfc06 specification of alternate function of p06 pin 0 intp106 input 1 dmarq2 input pfce05 pfc05 specification of al ternate function of p05 pin 0 0 intp005 input 0 1 dmarq1 input 1 0 intp10 input/tcud10 input 1 1 setting prohibited pfce04 pfc04 specification of al ternate function of p04 pin 0 0 intp004 input 0 1 dmarq0 input 1 0 intp11 input/tclr10 input 1 1 setting prohibited pfce01 pfc01 specification of al ternate function of p01 pin 0 0 intp001 input 0 1 top01 output 1 0 intpp01 input 1 1 setting prohibited pfce00 pfc00 specification of al ternate function of p00 pin 0 0 intp000 input 0 1 top00 output 1 0 evtp0 input/tip0 input/intpp00 input 1 1 setting prohibited
chapter 4 port functions user?s manual u16397ej3v0ud 97 (2) block diagram figure 4-3. block diagram of p00 pin internal bus address intp000 input (to hi-z control) selector selector selector rd wr port p00 p0 wr pmc pmc00 pmc0 wr intf intf00 intf0 wr pfce pfce00 pfce0 wr intr intr00 intr0 wr pm wr pfc pfc00 pfc0 pm00 pm0 p00/intp000/top00/ evtp0/tip0/intpp00 edge detection level detection noise elimination intp000 input evtp0/tip0/intpp00 input top00 output
chapter 4 port functions user?s manual u16397ej3v0ud 98 figure 4-4. block diagram of p01 pin internal bus address intp001 input intpp01 input top01 output top01 output enable signal selector selector selector rd wr port p01 p0 wr pmc pmc01 pmc0 wr intf intf01 intf0 wr pfce pfce01 pfce0 wr intr intr01 intr0 wr pm wr pfc pfc01 pfc0 pm01 pm0 p01/intp001/ top01/intpp01 edge detection level detection noise elimination
chapter 4 port functions user?s manual u16397ej3v0ud 99 figure 4-5. block diagram of p04 and p05 pins internal bus address intp004, intp005 inputs dmarq0, dmarq1 inputs intp11/tclr10, intp10/tcud10 inputs selector selector rd wr port p0n p0 wr pmc pmc0n pmc0 wr intf intf0n intf0 wr pfce pfce0n pfce0 wr intr intr0n intr0 wr pm wr pfc pfc0n pfc0 pm0n pm0 p04/intp004/dmarq0/ intp11/tclr10, p05/intp005/dmarq1/ intp10/tcud10 noise elimination edge detection level detection digital noise elimination remark n = 4, 5
chapter 4 port functions user?s manual u16397ej3v0ud 100 figure 4-6. block diagram of p06 and p07 pins internal bus address intp106, intp107 inputs dmarq2, damrq3 inputs selector selector rd wr port p0n p0 wr pmc pmc0n pmc0 wr intf intf0n intf0 wr pfc pfc0n pfc0 wr intr intr0n intr0 wr pm pm0n pm0 p06/intp106/dmarq2/tms, p07/intp107/dmarq3/tck trst input trst input tms, tck input noise elimination edge detection level detection remark n = 6, 7
chapter 4 port functions user?s manual u16397ej3v0ud 101 4.3.2 port 1 port 1 can be set to the input or output mode in 1-bit units. port 1 has an alternate function as the following pins. table 4-4. alternate-function pins of port 1 pin no. pin name gj f1 alternate-function pin i/o p10 27 j3 intp010/toqb1/intpq0/toq0 p11 26 k1 intp011/toqt1/intpq1/toq1 p12 25 j2 intp012/toqt2/intpq2/toq2 p13 22 h3 intp013/toqt3/intpq3/toq3 p14 21 h2 intp114/toqb2/tiq p15 20 h1 intp115/toqb3/evtq i/o caution p10 to p15 have h ysteresis characteristics when their alternate f unction is used in the input mode, but not when they are used in the port mode. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port 1 register (p1) 0 p1 0 p15 p14 p13 p12 p11 p10 after reset: undefined r/w address: fffff402h output 0. output 1. p1n 0 1 control of output data (in output mode) (n = 0 to 5) (b) port 1 mode register (pm1) 1 output mode input mode pm1n 0 1 control of input/output mode (in port mode) ( n = 0 to 5) pm1 1 pm15 pm14 pm13 pm12 pm11 pm10 after reset: ffh r/w address: fffff422h
chapter 4 port functions user?s manual u16397ej3v0ud 102 (c) port 1 mode control register (pmc1) 0 pmc1 0 pmc15 pmc14 pmc13 pmc12 pmc11 pmc10 i/o port intp115 input/toqb3 output/evtq input pmc15 0 1 specification of operation mode of p15 pin specification of operation mode of p14 pin specification of operation mode of p13 pin specification of operation mode of p12 pin specification of operation mode of p11 pin specification of operation mode of p10 pin i/o port intp114 input/toqb2 output/tiq input pmc14 0 1 i/o port intp013 input/toqt3 output/intpq3 input/toq3 output pmc13 0 1 i/o port intp012 input/toqt2 output/intpq2 input/toq2 output pmc12 0 1 i/o port intp011 input/toqt1 output/intpq1 input/toq1 output pmc11 0 1 i/o port intp010 input/toqb1 output/intpq0 input/toq0 output pmc10 0 1 after reset: 00h r/w address: fffff442h
chapter 4 port functions user?s manual u16397ej3v0ud 103 (d) port 1 function contro l expansion register (pfce1) 0 pfce1 0 pfce15 pfce14 pfce13 pfce12 pfce11 pfce10 after reset: 00h r/w address: fffff702h remark for the specification of the alternate function, see 4.3.2 (1) (f) setting of alternate functions of port 1 pins . (e) port 1 function control register (pfc1) 0 pfc1 0 pfc15 pfc14 pfc13 pfc12 pfc11 pfc10 after reset: 00h r/w address: fffff462h remark for the specification of the alternate function, see 4.3.2 (1) (f) setting of alternate functions of port 1 pins .
chapter 4 port functions user?s manual u16397ej3v0ud 104 (f) setting of alternate functions of port 1 pins pfce15 pfc15 specification of al ternate function of p15 pin 0 0 intp115 input 0 1 toqb3 output 1 0 evtq input 1 1 setting prohibited pfce14 pfc14 specification of al ternate function of p14 pin 0 0 intp114 input 0 1 toqb2 output 1 0 tiq input 1 1 setting prohibited pfce13 pfc13 specification of al ternate function of p13 pin 0 0 intp013 input 0 1 toqt3 output 1 0 intpq3 input 1 1 toq3 output pfce12 pfc12 specification of al ternate function of p12 pin 0 0 intp012 input 0 1 toqt2 output 1 0 intpq2 input 1 1 toq2 output pfce11 pfc11 specification of alternate function of p11 pin 0 0 intp011 input 0 1 toqt1 output 1 0 intpq1 input 1 1 toq1 output pfce10 pfc10 specification of al ternate function of p10 pin 0 0 intp010 input 0 1 toqb1 output 1 0 intpq0 input 1 1 toq0 output
chapter 4 port functions user?s manual u16397ej3v0ud 105 (2) block diagram figure 4-7. block diagram of p10 to p13 pins address intp010 to intp013 inputs toq0 to toq3 outputs toqb1, toqt1 to toqt3 outputs toqb1, toqt1 to toqt3, toq0 to toq3 output enable signals intpq0 to intpq3 inputs rd wr port p1n p1 wr pmc pmc1n pmc1 wr intf intf1n intf1 wr pfce pfce1n pfce1 wr intr intr1n intr1 wr pm wr pfc pfc1n pfc1 pm1n pm1 p10/intp010/toqb1/ intpq0/toq0, p11/intp011/toqt1/ intpq1/toq1, p12/intp012/toqt2/ intpq2/toq2, p13/intp013/toqt3/ intpq3/toq3 edge detection level detection noise elimination internal bus selector selector selector remark n = 0 to 3
chapter 4 port functions user?s manual u16397ej3v0ud 106 figure 4-8. block diagram of p14 and p15 pins internal bus address intp114, intp115 inputs evtq, tiq inputs toqb2, toqb3 outputs toqb2, toqb3 output enable signals selector selector selector rd wr port p1n p1 wr pmc pmc1n pmc1 wr intf intf1n intf1 wr pfce pfce1n pfce1 wr intr intr1n intr1 wr pm pfc1n pfc1 pm1n pm1 p14/intp114/ toqb2/tiq, p15/intp115/ toqb3/evtq edge detection level detection noise elimination wr pfc remark n = 4, 5
chapter 4 port functions user?s manual u16397ej3v0ud 107 4.3.3 port 2 port 2 can be set in the input or output mode in 1-bit units, except p20, which is input-only. p20 always functions as an nmi pin. the level of the nmi pin can be read by reading the p2.p20 bit. port 2 functions alternately as the following pins. port 2 has an alternate function as the following pins. table 4-5. alternate-function pins of port 2 pin no. pin name gj f1 alternate-function pin i/o p20 84 j14 nmi input p21 44 p4 intp021/top10/evtp1/tip1/intpp10 p22 43 l5 intp022/top11/intpp11 p24 31 k3 intp124/tc0 p25 30 l2 intp125/tc1/tiud10/to10 p26 29 k4 intp126/tc2/tdi note p27 28 k2 tc3/tdo note i/o note the tdi and tdo pins are for on-chip debugging. to use the p26 and p27 pins as p26/intp126/tc2 and p27/tc3, be sure to input a low level to the trst pin. if a high level is input to the trst pin, the values set to the p2, pm2, pmc2, and pfc2 registers become invalid, and the p26 and p27 pins function as the tdi and tdo pins. caution p20 to p22 and p24 to p26 have hysteres is characteristics when their alternate function is used in the input mode, but not when they are used in the port mode. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 4 port functions user?s manual u16397ej3v0ud 108 (1) registers (a) port 2 register (p2) p27 p2 p26 p25 p24 0 p22 p21 p20 after reset: undefined r/w address: fffff404h output 0. output 1. p2n 0 1 control of output data (in output mode) ( n = 0 to 2, 4 to 7) (b) port 2 mode register (pm2) pm27 output mode input mode pm2n 0 1 control of input/output mode (in port mode) ( n = 1, 2, 4 to 7) pm2 pm26 pm25 pm24 1 pm22 pm21 1 after reset: ffh r/w address: fffff424h
chapter 4 port functions user?s manual u16397ej3v0ud 109 (c) port 2 mode control register (pmc2) pmc27 pmc2 pmc26 pmc25 pmc24 0 pmc22 pmc21 1 i/o port tc3 output pmc27 0 1 specification of operation mode of p27 pin specification of operation mode of p26 pin specification of operation mode of p25 pin specification of operation mode of p24 pin specification of operation mode of p22 pin specification of operation mode of p21 pin i/o port intp126 input/tc2 output pmc26 0 1 i/o port intp125 input/tc1 output/tiud10 input/to10 output pmc25 0 1 i/o port intp124 input/tc0 output pmc24 0 1 i/o port intp022 input/top11 output/intpp11 input pmc22 0 1 i/o port intp021 input/top10 output/evtp1 input/tip1 input/intpp10 input pmc21 0 1 after reset: 01h r/w address: fffff444h caution the p26/intp126/tc2 pin f unctions alternately as the n-wi re control signal tdi, and the p27/tc3 pin functions alternatel y as the n-wire control signal tdo. these alternate functions cannot be debugged when the n-wi re type emulator is used.
chapter 4 port functions user?s manual u16397ej3v0ud 110 (d) port 2 function contro l expansion register (pfce2) 0 pfce2 0 pfce25 0 0 pfce22 pfce21 0 after reset: 00h r/w address: fffff704h remark for the specification of the alternate function, see 4.3.3 (1) (f) setting of alternate functions of port 2 pins . (e) port 2 function control register (pfc2) 0 pfc2 pfc26 pfc25 pfc24 0 pfc22 pfc21 0 after reset: 00h r/w address: fffff464h remark for the specification of the alternate function, see 4.3.3 (1) (f) setting of alternate functions of port 2 pins .
chapter 4 port functions user?s manual u16397ej3v0ud 111 (f) setting of alternate functions of port 2 pins pfc26 specification of alternate function of p26 pin 0 intp126 input 1 tc2 output pfce25 pfc25 specification of al ternate function of p25 pin 0 0 intp125 input 0 1 tc1 output 1 0 tiud10 input 1 1 to10 output pfc24 specification of alternate function of p24 pin 0 intp124 input 1 tc0 output pfce22 pfc22 specification of al ternate function of p22 pin 0 0 intp022 input 0 1 top11 output 1 0 intpp11 input 1 1 setting prohibited pfce21 pfc21 specification of al ternate function of p21 pin 0 0 intp021 input 0 1 top10 output 1 0 evtp1 input/tip1 input/intpp10 input 1 1 setting prohibited
chapter 4 port functions user?s manual u16397ej3v0ud 112 (2) block diagram figure 4-9. block diagram of p20 pin internal bus address 0 1 nmi input selector rd wr nmir nmir0 nmir wr nmif nmif0 nmif p20/nmi noise elimination edge detection
chapter 4 port functions user?s manual u16397ej3v0ud 113 figure 4-10. block diagram of p21 and p22 pins internal bus address intp021, intp022 inputs top10, top11 outputs evtp1/tip1/intpp10, intpp11 inputs selector selector selector rd wr port p2n p2n wr pmc pmc2n pmc2 wr intf intf2n intf2 wr pfce pfce2n pfce2 wr intr intr2n intr2 wr pm wr pfc pfc2n pfc2 pm2n pm2 p21/intp021/top10/ evtp1/tip1/intpp10, p22/intp022/top11/intpp11 edge detection level detection noise elimination remark n = 1, 2
chapter 4 port functions user?s manual u16397ej3v0ud 114 figure 4-11. block diagram of p24 pin internal bus address intp124 input tc0 output selector selector selector rd wr port p24 p2 wr pmc pmc24 pmc2 wr intf intf24 intf2 wr pfc pfc24 pfc2 wr intr intr24 intr2 wr pm pm24 pm2 p24/intp124/tc0 noise elimination edge detection level detection
chapter 4 port functions user?s manual u16397ej3v0ud 115 figure 4-12. block diagram of p25 pin internal bus address intp125 input to10 output tc1 output tiud10 input selector selector selector rd wr port p25 p2 wr pmc pmc25 pmc2 wr intf intf25 intf2 wr pfce pfce25 pfce2 wr intr intr25 intr2 wr pm wr pfc pfc25 pfc2 pm25 pm2 p25/intp125/tc1/ tiud10/to10 digital noise eliminator noise elimination edge detection level detection
chapter 4 port functions user?s manual u16397ej3v0ud 116 figure 4-13. block diagram of p26 pin internal bus address intp126 input tdi input trst input selector selector selector rd wr port p26 p2 wr pmc pmc26 pmc2 wr intf intf26 intf2 wr pfc pfc26 pfc2 wr intr intr26 intr2 wr pm pm26 pm2 p26/intp126/tc2/tdi trst input tc2 output noise elimination edge detection level detection
chapter 4 port functions user?s manual u16397ej3v0ud 117 figure 4-14. block diagram of p27 pin wr pmc wr pm wr port rd pmc27 pmc2 pm27 pm2 p27 p2 tc3 output tdo output p27/tc3/tdo address selector selector selector selector trst input internal bus
chapter 4 port functions user?s manual u16397ej3v0ud 118 4.3.4 port 3 port 3 can be set to the input or output mode in 1-bit units. port 3 has an alternate function as the following pins. table 4-6. alternate-function pins of port 3 pin no. pin name gj f1 alternate-function pin i/o p30 49 n6 intp130/txd2/so2 p31 48 m6 intp131/rxd2/si2 p32 47 l6 intp132/asck2/sck2 p33 46 n5 intp133/txd3/sda note p34 45 m5 intp134/rxd3/scl note p37 83 j11 intp137/adtrg i/o note i 2 c bus versions (y products) only (see table 1-1 ) when the p33 and p34 pins are used as the sda and scl pins, respectively, they function as dummy open-drain output pins (p-ch is always off). caution p30 to p34 and p37 have hysteresis characteristics when their alternate function is used in the input mode, but not when they are used in the port mode. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 4 port functions user?s manual u16397ej3v0ud 119 (1) registers (a) port 3 register (p3) p37 p3 0 0 p34 p33 p32 p31 p30 after reset: undefined r/w address: fffff406h output 0. output 1. p3n 0 1 control of output data (in output mode) ( n = 0 to 4, 7) (b) port 3 mode register (pm3) pm37 output mode input mode pm3n 0 1 control of input/output mode (in port mode) ( n = 0 to 4, 7) pm3 1 1 pm34 pm33 pm32 pm31 pm30 after reset: ffh r/w address: fffff426h
chapter 4 port functions user?s manual u16397ej3v0ud 120 (c) port 3 mode control register (pmc3) pmc37 pmc3 0 0 pmc34 pmc33 pmc32 pmc31 pmc30 i/o port intp137 input/adtrg output pmc37 0 1 specification of operation mode of p37 pin specification of operation mode of p34 pin specification of operation mode of p33 pin specification of operation mode of p32 pin specification of operation mode of p31 pin specification of operation mode of p30 pin i/o port intp134 input/rxd3 input/scl note i/o pmc34 0 1 i/o port intp133 input/txd3 output/sda note i/o pmc33 0 1 i/o port intp132 input/asck2 input/sck2 i/o pmc32 0 1 i/o port intp131 input/rxd2 input/si2 input pmc31 0 1 i/o port intp130 input/txd2 output/so2 output pmc30 0 1 after reset: 00h r/w address: fffff446h note i 2 c bus versions (y products) only (see table 1-1 ) when the p33 and p34 pins are used as the sda an d scl pins, respectively, they function as dummy open-drain output pins (p-ch is always off).
chapter 4 port functions user?s manual u16397ej3v0ud 121 (d) port 3 function contro l expansion register (pfce3) 0 pfce3 0 0 pfce34 pfce33 pfce32 pfce31 pfce30 after reset: 00h r/w address: fffff706h remark for the specification of the alternate function, see 4.3.4 (1) (f) setting of alternate functions of port 3 pins . (e) port 3 function control register (pfc3) 0 pfc3 0 0 pfc34 pfc33 pfc32 pfc31 pfc30 after reset: 00h r/w address: fffff466h remark for the specification of the alternate function, see 4.3.4 (1) (f) setting of alternate functions of port 3 pins .
chapter 4 port functions user?s manual u16397ej3v0ud 122 (f) setting of alternate functions of port 3 pins pfce34 pfc34 specification of al ternate function of p34 pin 0 0 intp134 input 0 1 rxd3 input 1 0 scl note i/o 1 1 setting prohibited pfce33 pfc33 specification of al ternate function of p33 pin 0 0 intp133 input 0 1 txd3 output 1 0 sda note i/o 1 1 setting prohibited pfce32 pfc32 specification of al ternate function of p32 pin 0 0 intp132 input 0 1 asck2 input 1 0 sck2 i/o 1 1 setting prohibited pfce31 pfc31 specification of al ternate function of p31 pin 0 0 intp131 input 0 1 rxd2 input 1 0 si2 input 1 1 setting prohibited pfce30 pfc30 specification of al ternate function of p30 pin 0 0 intp130 input 0 1 txd2 output 1 0 so2 output 1 1 setting prohibited note i 2 c bus versions (y products) only (see table 1-1 ) when the p33 and p34 pins are used as the sda and scl pins, respectively, they function as dummy open-drain output pins (p-ch is always off).
chapter 4 port functions user?s manual u16397ej3v0ud 123 (2) block diagram figure 4-15. block diagram of p30 pin internal bus address intp130 input selector selector selector rd wr port p30 p3 wr pmc pmc30 pmc3 wr intf intf30 intf3 wr pfce pfce30 pfce3 wr intr intr30 intr3 wr pm wr pfc pfc30 pfc3 pm30 pm3 p30/intp130/txd2/so2 so2 output txd2 output noise elimination edge detection level detection
chapter 4 port functions user?s manual u16397ej3v0ud 124 figure 4-16. block diagram of p31 pin internal bus address intp131 input selector selector rd wr port p31 p3 wr pmc pmc31 pmc3 wr intf intf31 intf3 wr pfce pfce31 pfce3 wr intr intr31 intr3 wr pm wr pfc pfc31 pfc3 pm31 pm3 p31/intp131/rxd2/si2 rxd2 input si2 input noise elimination edge detection level detection
chapter 4 port functions user?s manual u16397ej3v0ud 125 figure 4-17. block diagram of p32 pin internal bus address intp132 input selector selector selector rd wr port p32 p3 wr pmc pmc32 pmc3 wr intf intf32 intf3 wr pfce pfce32 pfce3 wr intr intr32 intr3 wr pm wr pfc pfc32 pfc3 pm32 pm3 p32/intp132/asck2/sck2 asck2 input intp132, asck2, sck2 input enable signal sck2 output sck2 output enable signal sck2 input noise elimination edge detection level detection
chapter 4 port functions user?s manual u16397ej3v0ud 126 figure 4-18. block diagram of p33 pin rd wr port p33 p3 wr pmc pmc33 pmc3 wr intf intf33 intf3 wr pfce pfce33 pfce3 wr intr intr33 intr3 wr pm wr pfc pfc33 pfc3 pm33 pm3 p33/intp133/ txd3/sda note txd3 output sda note output internal bus address selector selector selector noise elimination edge detection level detection intp133 input sda note input note i 2 c bus versions (y products) only (see table 1-1 )
chapter 4 port functions user?s manual u16397ej3v0ud 127 figure 4-19. block diagram of p34 pin internal bus address selector selector selector rd wr port p34 p3 wr pmc pmc34 pmc3 wr intf intf34 intf3 wr pfce pfce34 pfce3 wr intr intr34 intr3 wr pm wr pfc pfc34 pfc3 pm34 pm3 p34/intp134/ rxd3/scl note intp134 input rxd3 input scl note input scl note output noise elimination edge detection level detection note i 2 c bus versions (y products) only (see table 1-1 )
chapter 4 port functions user?s manual u16397ej3v0ud 128 figure 4-20. block diagram of p37 pin internal bus wr pmc rd address wr port p37/intp137/adtrg pmc37 pmc3 wr intf intf37 intf3 selector selector wr pm pm37 pm3 wr intr intr37 intr3 p37 p3 intp137, adtrg inputs noise elimination edge detection level detection
chapter 4 port functions user?s manual u16397ej3v0ud 129 4.3.5 port 4 port 4 can be set to the input or output mode in 1-bit units. port 4 has an alternate function as the following pins. table 4-7. alternate-function pins of port 4 pin no. pin name gj f1 alternate-function pin i/o p40 55 l8 so0/txd0 p41 54 p7 si0/rxd0 p42 53 n7 sck0/asck0 p43 52 m7 so1/txd1 p44 51 p6 si1/rxd1 p45 50 l7 sck1/asck1 i/o caution p41, p42, p44, and p45 have hysteresis characteristics wh en their alternate function is used in the input mode, but not when they are used in the port mode. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port 4 register (p4) 0 p4 0 p45 p44 p43 p42 p41 p40 after reset: undefined r/w address: fffff408h output 0. output 1. p4n 0 1 control of output data (in output mode) ( n = 0 to 5) (b) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 control of input/output mode (in port mode) ( n = 0 to 5) pm4 1 pm45 pm44 pm43 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h
chapter 4 port functions user?s manual u16397ej3v0ud 130 (c) port 4 mode control register (pmc4) 0 pmc4 0 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 i/o port sck1 i/o/asck1 input pmc45 0 1 specification of operation mode of p45 pin specification of operation mode of p44 pin specification of operation mode of p43 pin specification of operation mode of p42 pin specification of operation mode of p41 pin specification of operation mode of p40 pin i/o port si1 input/rxd1 input pmc44 0 1 i/o port so1 output/txd1 output/ pmc43 0 1 i/o port sck0 i/o/asck0 input pmc42 0 1 i/o port si0 input/rxd0 input pmc41 0 1 i/o port so0 output/txd0 output pmc40 0 1 after reset: 00h r/w address: fffff448h
chapter 4 port functions user?s manual u16397ej3v0ud 131 (d) port 4 function control register (pfc4) 0 pfc4 0 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 sck1 i/o asck1 input pfc45 0 1 specification of alternate function of p40 pin specification of alternate function of p41 pin specification of alternate function of p42 pin specification of alternate function of p43 pin specification of alternate function of p44 pin specification of alternate function of p45 pin si1 input rxd1 input pfc44 0 1 so1 output txd1 output pfc43 0 1 sck0 i/o asck0 input pfc42 0 1 si0 input rxd0 input pfc41 0 1 so0 output txd0 output pfc40 0 1 after reset: 00h r/w address: fffff468h
chapter 4 port functions user?s manual u16397ej3v0ud 132 (2) block diagram figure 4-21. block diagram of p40 and p43 pins wr pmc rd address so0, so1 outputs txd0, txd1 outputs wr port p40/so0/txd0, p43/so1/txd1 pmc4n pmc4 wr pfc pfc4n pfc4 wr pm pm4n pm4 p4n p4 internal bus selector selector selector selector remark n = 0, 3
chapter 4 port functions user?s manual u16397ej3v0ud 133 figure 4-22. block diagram of p41 and p44 pins address wr pfc wr pmc wr pm wr port rd pfc4n pfc4 pmc4n pmc4 pm4n pm4 p4n p4 p41/si0/rxd0 p44/si1/rxd1 rxd0, rxd1 inputs si0, si1 inputs internal bus selector selector remark n = 1, 4
chapter 4 port functions user?s manual u16397ej3v0ud 134 figure 4-23. block diagram of p42 and p45 pins wr pfc wr pmc wr pm wr port rd pfc4n pfc4n pmc4n pmc4n pm4n pm4n p4n p4 p42/sck0/asck0, p45/sck1/asck1 address sck0, sck1 inputs sck0, sck1 outputs sck0, sck1 input enable signals sck0, sck1 output enable signals asck0, asck1 inputs internal bus selector selector selector remark n = 2, 5
chapter 4 port functions user?s manual u16397ej3v0ud 135 4.3.6 port 5 port 5 can be set to the input or output mode in 1-bit units. port 5 has an alternate function as the following pins. table 4-8. alternate-function pins of port 5 pin no. pin name gj f1 alternate-function pin i/o p50 86 j13 intp050/top20/evtp2/tip2/intpp20 p51 85 j12 intp051/top21/intpp21 i/o caution p50 and p51 have hysteresis characteristics when their alternate functi on is used in the input mode, but not when they are used in the port mode. remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port 5 register (p5) 0 p5 0 0 0 0 0 p51 p50 after reset: undefined r/w address: fffff40ah output 0. output 1. p5n 0 1 control of output data (in output mode) ( n = 0, 1) (b) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 control of input/output mode (in port mode) (( n = 0, 1) pm5 1 1 1 1 1 pm51 pm50 after reset: ffh r/w address: fffff42ah
chapter 4 port functions user?s manual u16397ej3v0ud 136 (c) port 5 mode control register (pmc5) 0 pmc5 0 0 0 0 0 pmc51 pmc50 i/o port intp050 input/top20 output/evtp2 input/tip2 input/intpp20 input pmc51 0 1 specification of operation mode of p51 pin specification of operation mode of p51 pin i/o port intp051 input/top21 output/intpp21 input pmc50 0 1 after reset: 00h r/w address: fffff44ah (d) port 5 function contro l expansion register (pfce5) 0 pfce5 0 0 0 0 0 pfce51 pfce50 after reset: 00h r/w address: fffff70ah remark for the specification of the alternate function, see 4.3.6 (1) (f) setting of alternate functions of port 5 pins . (e) port 5 function control register (pfc5) 0 pfc5 0 0 0 0 0 pfc51 pfc50 after reset: 00h r/w address: fffff46ah remark for the specification of the alternate function, see 4.3.6 (1) (f) setting of alternate functions of port 5 pins .
chapter 4 port functions user?s manual u16397ej3v0ud 137 (f) setting of alternate functions of port 5 pins pfce51 pfc51 specification of alternate function of p51 0 0 intp051 input 0 1 top21 output 1 0 intpp21 input 1 1 setting prohibited pfce50 pfc50 specification of alternate function of p50 0 0 intp050 input 0 1 top20 output 1 0 evtp2 input/tip2 input/intpp20 input 1 1 setting prohibited
chapter 4 port functions user?s manual u16397ej3v0ud 138 (2) block diagram figure 4-24. block diagram of p50 and p51 pins address intp050, intp051 inputs top20, top21 outputs evtp2/tip2/intpp20, intpp21 inputs rd wr port p5n p5n wr pmc pmc5n pmc5 wr intf intf5n intf5 wr pfce pfce5n pfce5 wr intr intr5n intr5 wr pm wr pfc pfc5n pfc5 pm5n pm5 p50/intp050/top20/ evtp2/tip2/intpp20, p51/intp051/top21/intpp21 edge detection level detection noise elimination internal bus selector selector selector remark n = 0, 1
chapter 4 port functions user?s manual u16397ej3v0ud 139 4.3.7 port 7 all of the port 7 pins are fixed to the input mode. port 7 has an alternate function as the following pins. table 4-9. alternate-function pins of port 7 pin no. pin name gj f1 alternate-function pin i/o p70 80 k12 ani0 p71 79 k11 ani1 p72 78 l14 ani2 p73 77 l13 ani3 p74 76 l12 ani4 p75 75 m13 ani5 p76 74 m12 ani6 p77 73 l11 ani7 input remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 4 port functions user?s manual u16397ej3v0ud 140 (1) registers (a) port 7 register (p7) p77 p7 p76 p75 p74 p73 p72 p71 p70 after reset: undefined r address: fffff40eh input 0. input 1. p7n 0 1 input data read (n = 0 to 7) caution do not read the p7 re gister during a/d conversion. (b) port 7 mode control register (pmc7) pmc77 pmc7 pmc76 pmc75 pmc74 pmc73 pmc72 pmc71 pmc70 input port anin input pmc7n 0 1 specification of operation mode of p7n pin (n = 0 to 7) after reset: 00h r/w address: fffff44eh caution do not change to the port mode during a/d conversion.
chapter 4 port functions user?s manual u16397ej3v0ud 141 (2) block diagram figure 4-25. block diagram of p70 to p77 pins rd ani0 to ani7 inputs wr pmc pmc7n pmc7 p70/ani0 to p77/ani7 internal bus remark n = 0 to 7
chapter 4 port functions user?s manual u16397ej3v0ud 142 4.3.8 port 8 both the port 8 pins are fixed to the input mode. port 8 has an alternate function as the following pins. table 4-10. alternate-function pins of port 8 pin no. pin name gj f1 alternate-function pin i/o p80 69 p13 ano0 p81 68 n11 ano1 input remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port 8 register (p8) 0 p8 0 0 0 0 0 p81 p80 after reset: undefined r address: fffff410h input 0. input 1. p8n 0 1 input data read (n = 0, 1) caution do not read the p8 register during d/a con version. when using port 8 as an input port, be sure to stop the d/a conversion operation.
chapter 4 port functions user?s manual u16397ej3v0ud 143 (2) block diagram figure 4-26. block diagram of p80 and p81 pins rd p80/ano0, p81/ano1 ano0, ano1 outputs p-ch av dd1 av ss1 n-ch internal bus remark n = 0, 1
chapter 4 port functions user?s manual u16397ej3v0ud 144 4.3.9 port al port al can be set to the input or output mode in 1-bit units. port al has an alternate function as the following pins. table 4-11. alternate-function pins of port al pin no. pin name gj f1 alternate-function pin i/o pal0 143 b3 a0 pal1 142 c4 a1 pal2 141 a3 a2 pal3 140 d4 a3 pal4 139 b4 a4 pal5 138 a4 a5 pal6 137 d5 a6 pal7 136 c5 a7 pal8 133 b6 a8 pal9 132 a6 a9 pal10 131 d6 a10 pal11 130 c7 a11 pal12 129 a7 a12 pal13 128 b7 a13 pal14 127 d7 a14 pal15 126 a8 a15 i/o remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 4 port functions user?s manual u16397ej3v0ud 145 (1) registers (a) port al register (pal) pal (palh note ) after reset: undefined r/w address: pal7 pal6 pal5 pal4 pal3 pal2 pal1 pal0 pal15 pal14 pal13 pal12 pal11 pal10 pal9 pal8 8 9 10 11 12 13 14 15 output 0. output 1. paln 0 1 control of output data (in output mode) ( n = 0 to 15) (pall) pal fffff000h, pall fffff000h, palh fffff001h note to read/write bits 8 to 15 of the pal register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the palh register. remark the pal register can be read or written in 16-bit units. when the higher 8 bits of the pal register are used as the palh register, and the lower 8 bits, as the pall register, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16397ej3v0ud 146 (b) port al mode register (pmal) output mode input mode pmaln 0 1 specification of input/output mode (in port mode) ( n = 0 to 15) pmal (pmalh note ) after reset: ffffh r/w address: pmal7 pmal6 pmal5 pmal4 pmal3 pmal2 pmal1 pmal0 pmal15 pmal14 pmal13 pmal12 pmal11 pmal10 pmal9 pmal8 8 9 10 11 12 13 14 15 (pmall) pmal fffff020h, pmall fffff020h, pmalh fffff021h note to read/write bits 8 to 15 of the pmal register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmalh register. remark the pmal register can be read or written in 16-bit units. when the higher 8 bits of the pmal register are used as the pmalh register, and the lower 8 bits, as the pmall register, these registers can be read or written in 8-bit or 1-bit units. (c) port al mode control register (pmcal) i/o port an output pmcaln 0 1 specification of operation mode of paln pin ( n = 0 to 15) pmcal (pmcalh note ) after reset: 0000h r/w address: pmcal7 pmcal6 pmcal5 pmcal4 pmcal3 pmcal2 pmcal1 pmcal0 pmcal15 pmcal14 pmcal13 pmcal12 pmcal11 pmcal10 pmcal9 pmcal8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 (pmcall) pmcal fffff040h, pmcall fffff040h, pmcalh fffff041h note to read/write bits 8 to 15 of the pmca l register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcalh register. remark the pmcal register can be read or written in 16-bit units. when the higher 8 bits of the pmcal register ar e used as the pmcalh register, and the lower 8 bits, as the pmcall register, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16397ej3v0ud 147 (2) block diagram figure 4-27. block diagram of pal0 to pal15 pins wr pmc wr pm wr port rd pmcaln pmcal pmaln pmal paln pal output buffer off signal note pal0/a0 to pal15/a15 a0 to a15 outputs address mode0, mode1 internal bus selector selector selector note signal that is active in the idle and software stop modes, or during bus hold. remark n = 0 to 15
chapter 4 port functions user?s manual u16397ej3v0ud 148 4.3.10 port ah port ah can be set to the input or output mode in 1-bit units. port ah has an alternate function as the following pins. table 4-12. alternate-function pins of port ah pin no. pin name gj f1 alternate-function pin i/o pah0 123 d8 a16 pah1 122 a9 a17 pah2 121 b9 a18 pah3 120 c9 a19 pah4 119 d9 a20 pah5 118 b10 a21 pah6 117 c10 a22 pah7 116 d10 a23 pah8 115 a11 a24 pah9 114 b11 a25 i/o remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port ah register (pah) pah (pahh note ) after reset: undefined r/w address: pah7 pah6 pah5 pah4 pah3 pah2 pah1 pah0 0 0 0 0 0 0 pah9 pah8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 output 0. output 1. pahn 0 1 control of output data (in output mode) ( n = 0 to 9) (pahl) pah fffff002h, pahl fffff002h, pahh fffff003h note to read/write bits 8 to 15 of the pah register in 8-bi t or 1-bit units, specify them as bits 0 to 7 of the pahh register. remark the pah register can be read or written in 16-bit units. when the higher 8 bits of the pah register are used as the pahh register, and the lower 8 bits, as the pahl register, these registers can be re ad or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16397ej3v0ud 149 (b) port ah mode register (pmah) output mode input mode pmahn 0 1 control of input/output mode (in port mode) ( n = 0 to 9) pmah (pmahh note ) after reset: ffffh r/w address: pmah7 pmah6 pmah5 pmah4 pmah3 pmah2 pmah1 pmah0 1 1 1 1 1 1 pmah9 pmah8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 (pmahl) pmah fffff022h, pmahl fffff022h, pmahh fffff023h note to read/write bits 8 to 15 of the pm ah register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmahh register. remark the pmah register can be read or written in 16-bit units. when the higher 8 bits of the pmah register are used as the pmahh register, and the lower 8 bits, as the pmahl register, these registers can be read or written in 8-bit or 1-bit units. (c) port ah mode control register (pmcah) i/o port am output (m = 16 to 25) pmcahn 0 1 specification of operation mode of pahn pin ( n = 0 to 9) pmcah (pmcahh note ) after reset: 0000h r/w address: pmcah7 pmcah6 pmcah5 pmcah4 pmcah3 pmcah2 pmcah1 pmcah0 0 0 0 0 0 0 pmcah9 pmcah8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 (pmcahl) pmcah fffff042h, pmcahl fffff042h, pmcahh fffff043h note to read/write bits 8 to 15 of the pmca h register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcahh register. remark the pmcah register can be read or written in 16-bit units. when the higher 8 bits of the pmcah register are used as the pmcahh register, and the lower 8 bits, as the pmcahl register, these registers c an be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16397ej3v0ud 150 (2) block diagram figure 4-28. block diagram of pah0 to pah9 pins wr pmc wr pm rd pmcahn pmcah pmahn pmah pahn pah output buffer off signal note pah0/a16 to pah9/a25 a16 to a25 outputs address mode0, mode1 wr port internal bus selector selector selector note signal that is active in the idle and software stop modes, or during bus hold. remark n = 0 to 9
chapter 4 port functions user?s manual u16397ej3v0ud 151 4.3.11 port dl port dl can be set to the input or output mode in 1-bit units. port dl has an alternate function as the following pins. table 4-13. alternate-function pins of port dl pin no. pin name gj f1 alternate-function pin i/o pdl0 17 g3 ad0 pdl1 16 h4 ad1 pdl2 15 f1 ad2 pdl3 14 f2 ad3 pdl4 13 f3 ad4 pdl5 12 e1 ad5 pdl6 11 g4 ad6 pdl7 10 e2 ad7 pdl8 7 e3 ad8 pdl9 6 c2 ad9 pdl10 5 d2 ad10 pdl11 4 e4 ad11 pdl12 3 b2 ad12 pdl13 2 c3 ad13 pdl14 1 d3 ad14 pdl15 144 a2 ad15 i/o remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 4 port functions user?s manual u16397ej3v0ud 152 (1) registers (a) port dl register (pdl) pdl (pdlh note ) after reset: undefined r/w address: pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 pdl15 pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 output 0. output 1. pdln 0 1 control of output data (in output mode) ( n = 0 to 15) (pdll) pdl fffff004h, pdll fffff004h, pdlh fffff005h note to read/write bits 8 to 15 of the pdl register in 8-bi t or 1-bit units, specify them as bits 0 to 7 of the pdlh register. remark the pdl register can be read or written in 16-bit units. when the higher 8 bits of the pdl register are used as the pdlh register, and the lower 8 bits, as the pdll register, these registers can be re ad or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16397ej3v0ud 153 (b) port dl mode register (pmdl) output mode input mode pmdln 0 1 control of input/output mode (in port mode) ( n = 0 to 15) pmdl (pmdlh note ) after reset: ffffh r/w address: pmdl7 pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 pmdl15 pmdl14 pmdl13 pmdl12 pdal11 pdal10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 (pmdll) pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h note to read/write bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register. remark the pmdl register can be read or written in 16-bit units. when the higher 8 bits of the pmdl register ar e used as the pmdlh register, and the lower 8 bits, as the pmdll register, these registers can be read or written in 8-bit or 1-bit units. (c) port dl mode control register (pmcdl) i/o port adn i/o pmcdln 0 1 specification of operation mode of pdln pin ( n = 0 to 15) pmcdl (pmcdlh note ) after reset: 0000h r/w address: pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 pmcdl15 pmcdl14 pmcdl13 pmcdl12 pmcdl11 pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 (pmcdll) pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h note to read/write bits 8 to 15 of the pm cdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register. remark the pmcdl register can be read or written in 16-bit units. when the higher 8 bits of the pmcdl register ar e used as the pmcdlh register, and the lower 8 bits, as the pmcdll register, these registers can be read or written in 8-bit or 1-bit units.
chapter 4 port functions user?s manual u16397ej3v0ud 154 (2) block diagram figure 4-29. block diagram of pdl0 to pdl15 pins wr pmc wr pm wr port rd pmcdln pmcdl pmdln pmdl pdln pdl ad0 to ad15 input enable signals ad0 to ad15 outputs ad0 to ad15 output enable signals ad0 to ad15 inputs output buffer off signal note pdl0/ad0 to pdl15/ad15 address mode0, mode1 internal bus selector selector selector note signal that is active in the idle and software stop modes, or during bus hold. remark n = 0 to 15
chapter 4 port functions user?s manual u16397ej3v0ud 155 4.3.12 port cs port cs can be set to the input or output mode in 1-bit units. port cs has an alternate function as the following pins. table 4-14. alternate-function pins of port cs pin no. pin name gj f1 alternate-function pin i/o pcs0 107 d12 cs0 pcs1 106 b13 cs1 pcs2 105 c13 cs2/iowr pcs3 104 c12 cs3 pcs4 103 e12 cs4 pcs5 102 d13 cs5/iord pcs6 101 e11 cs6 pcs7 100 e13 cs7 i/o remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port cs register (pcs) pcs after reset: undefined r/w address: fffff008h pcs7 pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 0 1 2 3 4 5 6 7 output 0. output 1. pcsn 0 1 control of output data (in output mode) ( n = 0 to 7) (b) port cs mode register (pmcs) output mode input mode pmcsn 0 1 control of input/output mode (in port mode) ( n = 0 to 7) pmcs after reset: ffh r/w address: fffff028h pmcs7 pmcs6 pmcs5 pmcs4 pmcs3 pmcs2 pmcs1 pmcs0
chapter 4 port functions user?s manual u16397ej3v0ud 156 (c) port cs mode control register (pmccs) pmccs7 pmccs pmccs6 pmccs5 pmccs4 pmccs3 pmccs2 pmccs1 pmccs0 i/o port cs7 output pmccs7 0 1 specification of operation mode of pcs7 pin specification of operation mode of pcs6 pin specification of operation mode of pcs5 pin specification of operation mode of pcs4 pin specification of operation mode of pcs3 pin specification of operation mode of pcs2 pin i/o port cs6 output pmccs6 0 1 i/o port cs5 output/iord output pmccs5 0 1 i/o port cs4 output pmccs4 0 1 i/o port cs3 output pmccs3 0 1 i/o port cs2 output/iowr output pmccs2 0 1 after reset: 00h r/w address: fffff048h specification of operation mode of pcs1 pin i/o port cs1 output pmccs1 0 1 specification of operation mode of pcs0 pin i/o port cs0 output pmccs0 0 1
chapter 4 port functions user?s manual u16397ej3v0ud 157 (d) port cs function control register (pfccs) 0 pfccs 0 pfccs5 0 0 pfccs2 0 0 cs5 output iord output pfccs5 0 1 specification of alternate function of pcs5 pin specification of alternate function of pcs2 pin cs2 output iowr output pfccs2 0 1 after reset: 00h r/w address: fffff049h
chapter 4 port functions user?s manual u16397ej3v0ud 158 (2) block diagram figure 4-30. block diagram of pcs0, pc s1, pcs3, pcs4, pcs6 , and pcs7 pins wr pmc wr pm wr port rd pmccsn pmccs pmcsn pmcs pcsn pcs output buffer off signal note pcs0/cs0, pcs1/cs1, pcs3/cs3, pcs4/cs4, pcs6/cs6, pcs7/cs7 cs0, cs1, cs3, cs4, cs6, cs7 outputs address mode0, mode1 internal bus selector selector selector note signal that is active during bus hold. remark n = 0, 1, 3, 4, 6, 7
chapter 4 port functions user?s manual u16397ej3v0ud 159 figure 4-31. block diagram of pcs2 and pcs5 pins wr pmc rd address output buffer off signal note cs2, cs5 outputs iowr, iord outputs wr port pcs2/cs2/iowr, pcs5/cs5/iord pmc cs n pmc cs wr pfc pfccsn pfccs mode0, mode1 wr pm pmcsn pmcs pcsn pcs internal bus selector selector selector selector note signal that is active during bus hold. remark n = 2, 5
chapter 4 port functions user?s manual u16397ej3v0ud 160 4.3.13 port ct port ct can be set to the input or output mode in 1-bit units. port ct has an alternate function as the following pins. table 4-15 alternate-function pins of port ct pin no. pin name gj f1 alternate-function pin i/o pct0 97 f13 lwr/ldqm/lbe pct1 96 f14 uwr/udqm/ube pct4 95 f11 rd pct5 94 g12 wr/we pct6 93 g14 astb pct7 92 g13 bcyst i/o remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port ct register (pct) pct after reset: undefined r/w address: fffff00ah pct7 pct6 pct5 pct4 0 0 pct1 pct0 output 0. output 1. pctn 0 1 control of output data (in output mode) ( n = 0, 1, 4 to 7) (b) port ct mode register (pmct) output mode input mode pmctn 0 1 control of input/output mode (in port mode) ( n = 0, 1, 4 to 7) pmct after reset: ffh r/w address: fffff02ah pmct7 pmct6 pmct5 pmct4 1 1 pmct1 pmct0
chapter 4 port functions user?s manual u16397ej3v0ud 161 (c) port ct mode control register (pmcct) pmcct7 pmcct pmcct6 pmcct5 pmcct4 0 0 pmcct1 pmcct0 i/o port bcyst output pmcct7 0 1 specification of operation mode of pct7 pin specification of operation mode of pct6 pin specification of operation mode of pct5 pin specification of operation mode of pct4 pin specification of operation mode of pct1 pin specification of operation mode of pct0 pin i/o port astb output pmcct6 0 1 i/o port wr output/we output pmcct5 0 1 i/o port rd output pmcct4 0 1 i/o port uwr output/udqm output/ube output pmcct1 0 1 i/o port lwr output/ldqm output/lbe output pmcct0 0 1 after reset: 00h r/w address: fffff04ah
chapter 4 port functions user?s manual u16397ej3v0ud 162 (d) port ct function control register (pfcct) 0 pfcct 0 0 0 0 0 pfcct1 pfcct0 uwr output/udqm output note 1 ube output/udqm output note 1 pfcct1 0 1 specification of alternate function of pct1 pin specification of alternate function of pct0 pin lwr output/ldqm output note 2 lbe output/ldqm output note 2 pfcct0 0 1 after reset: 00h r/w address: fffff04bh notes 1. the uwr output or udqm outpu t, and ube output or udqm output are automatically selected when target memory is accessed. 2. the lwr output or ldqm output, and lbe output or ldqm output are automatically selected when the target memory is accessed. caution the xdqm signal differs in timing between when xwr output/xdqm output is selected and when xbe output/xdqm output is selected. how ever, this signal can be connected to sdram without problem regardless of which output is selected. for the output timing of the xdqm signal, see timing charts of 6.3.5 sdra m access (figure 6-12) (x = u or l).
chapter 4 port functions user?s manual u16397ej3v0ud 163 (2) block diagram figure 4-32. block diagram of pct0 and pct1 pins wr pmc rd address output buffer off signal note lwr/ldqm, uwr/udqm outputs lbe, ube outputs wr port pct0/lwr/ldqm/lbe, pct1/uwr/udqm/ube pmc ct n pmc ct wr pfc pfcctn pfcct mode0, mode1 mode0, mode1 wr pm pmctn pmct pctn pct internal bus selector selector selector selector note signal that is active during bus hold. remark n = 0, 1
chapter 4 port functions user?s manual u16397ej3v0ud 164 figure 4-33. block diagram of pct4 to pct7 pins wr pmc wr pm wr port rd pmcctn pmcct pmctn pmct pctn pct output buffer off signal note pct4/rd, pct5/wr/we, pct6/astb, pct7/bcyst rd, wr/we, astb, bcyst outputs address mode0, mode1 internal bus selector selector selector note signal that is active during bus hold. remark n = 4 to 7
chapter 4 port functions user?s manual u16397ej3v0ud 165 4.3.14 port cm port cm can be set to the input or output mode in 1-bit units. port cm has an alternate function as the following pins. table 4-16. alternate-function pins of port cm pin no. pin name gj f1 alternate-function pin i/o pcm0 91 g11 wait pcm1 90 h14 busclk pcm2 89 h13 hldak pcm3 88 h12 hldrq pcm4 87 h11 refrq i/o remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port cm register (pcm) pcm after reset: undefined r/w address: fffff00ch 0 0 0 pcm4 pcm3 pcm2 pcm1 pcm0 output 0. output 1. pcmn 0 1 control of output data (in output mode) ( n = 0 to 4) (b) port cm mode register (pmcm) output mode input mode pmcmn 0 1 control of input/output mode (in port mode) ( n = 0 to 4) pmcm after reset: ffh r/w address: fffff02ch 1 1 1 pmcm4 pmcm3 pmcm2 pmcm1 pmcm0
chapter 4 port functions user?s manual u16397ej3v0ud 166 (c) port cm mode control register (pmccm) 0 pmccm 0 0 pmccm4 pmccm3 pmccm2 pmccm1 pmccm0 i/o port refrq output pmccm4 0 1 specification of operation mode of pcm4 pin specification of operation mode of pcm3 pin specification of operation mode of pcm2 pin specification of operation mode of pcm1 pin specification of operation mode of pcm0 pin i/o port hldrq input pmccm3 0 1 i/o port hldak output pmccm2 0 1 i/o port busclk output pmccm1 0 1 i/o port wait input pmccm0 0 1 after reset: 00h r/w address: fffff04ch
chapter 4 port functions user?s manual u16397ej3v0ud 167 (2) block diagram figure 4-34. block diagram of pcm0 and pcm3 pins wr pmc wr pm wr port rd in pmccmn pmccm mode0, mode1 pmcmn pmcm pcmn pcm pcm0/wait, pcm3/hldrq address wait, hldrq inputs internal bus selector selector remark n = 0, 3
chapter 4 port functions user?s manual u16397ej3v0ud 168 figure 4-35. block diagram of pcm1 pin wr pmc rd address wr port pcm1/busclk busclk output pmc cm1 pmc cm mode0, mode1 wr pm pmcm1 pmcm pcm1 pcm internal bus selector selector selector
chapter 4 port functions user?s manual u16397ej3v0ud 169 figure 4-36. block diagram of pcm2 and pcm4 pins wr pmc wr pm wr port rd pmccmn pmccm pmcmn pmcm pcmn pcm pcm2/hldak, pcm4/refrq address mode0, mode1 hldak, refrq outputs internal bus selector selector selector remark n = 2, 4
chapter 4 port functions user?s manual u16397ej3v0ud 170 4.3.15 port cd port cd can be set to the input or output mode in 1-bit units. port cd has an alternate function as the following pins. table 4-17. alternate-function pins of port cd pin no. pin name gj f1 alternate-function pin i/o pcd0 111 d11 sdcke pcd1 110 b12 sdclk pcd2 109 a13 sdcas pcd3 108 a14 sdras i/o remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port cd register (pcd) pcd after reset: undefined r/w address: fffff00eh 0 0 0 0 pcd3 pcd2 pcd1 pcd0 output 0. output 1. pcdn 0 1 control of output data (in output mode) ( n = 0 to 3) (b) port cd mode register (pmcd) output mode input mode pmcdn 0 1 control of input/output mode (in port mode) ( n = 0 to 3) pmcd after reset: ffh r/w address: fffff02eh 1 1 1 1 pmcd3 pmcd2 pmcd1 pmcd0
chapter 4 port functions user?s manual u16397ej3v0ud 171 (c) port cd mode control register (pmccd) 0 pmccd 0 0 0 pmccd3 pmccd2 pmccd1 pmccd0 specification of operation mode of pcd3 pin specification of operation mode of pcd2 pin specification of operation mode of pcd1 pin specification of operation mode of pcd0 pin i/o port sdras output pmccd3 0 1 i/o port sdcas output pmccd2 0 1 i/o port sdclk output pmccd1 0 1 i/o port sdcke output pmccd0 0 1 after reset: 00h r/w address: fffff04eh
chapter 4 port functions user?s manual u16397ej3v0ud 172 (2) block diagram figure 4-37. block diagram of pcd0 and pcd1 pins wr pmc wr pm wr port rd pmccdn pmccd pmcdn pmcd pcdn pcd pcd0/sdcke, pcd1/sdclk address mode0, mode1 sdcke, sdclk outputs internal bus selector selector selector remark n = 0, 1
chapter 4 port functions user?s manual u16397ej3v0ud 173 figure 4-38. block diagram of pcd2 and pcd3 pins wr pmc wr pm wr port rd pmccdn pmccd pmcdn pmcd pcdn pcd output buffer off signal note pcd2/sdcas, pcd3/sdras sdcas, sdras outputs address mode0, mode1 internal bus selector selector selector remark n = 2, 3
chapter 4 port functions user?s manual u16397ej3v0ud 174 4.3.16 port bd port bd can be set to the input or output mode in 1-bit units. port bd has an alternate function as the following pins. table 4-18. alternate-function pins of port bd pin no. pin name gj f1 alternate-function pin i/o pbd0 42 n4 dmaak0 pbd1 41 p3 dmaak1 pbd2 40 m4 dmaak2 pbd3 39 n3 dmaak3 i/o remark gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13) (1) registers (a) port bd register (pbd) pbd after reset: undefined r/w address: fffff012h 0 0 0 0 pbd3 pbd2 pbd1 pbd0 output 0. output 1. pbdn 0 1 control of output data (in output mode) ( n = 0 to 3) (b) port bd mode register (pmbd) output mode input mode pmbdn 0 1 control of input/output mode (in port mode) ( n = 0 to 3) pmbd after reset: ffh r/w address: fffff032h 1 1 1 1 pmbd3 pmbd2 pmbd1 pmbd0
chapter 4 port functions user?s manual u16397ej3v0ud 175 (c) port bd mode control register (pmcbd) 0 pmcbd 0 0 0 pmcbd3 pmcbd2 pmcbd1 pmcbd0 specification of operation mode of pbd3 pin specification of operation mode of pbd2 pin specification of operation mode of pbd1 pin specification of operation mode of pbd0 pin i/o port dmaak3 output pmcbd3 0 1 i/o port dmaak2 output pmcbd2 0 1 i/o port dmaak1 output pmcbd1 0 1 i/o port dmaak0 output pmcbd0 0 1 after reset: 00h r/w address: fffff052h
chapter 4 port functions user?s manual u16397ej3v0ud 176 (2) block diagram figure 4-39. block diagram of pbd0 to pbd3 pins wr pmc wr pm wr port rd pmcbdn pmcbd pmbdn pmbd pbdn pbd dmaak0 to dmaak3 outputs pbd0/dmaak0 to pbd3/dmaak3 address internal bus selector selector selector remark n = 0 to 3
chapter 4 port functions user?s manual u16397ej3v0ud 177 4.4 setting to use alternate function of port pin set the port pins as shown in table 4-19 to use their alternate function.
chapter 4 port functions user?s manual u16397ej3v0ud 178 table 4-19. using alternate function of port pins (1/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) input output input input input input output input input input input input input input input input p00 p01 p04 p05 intp000 top00 evtp00 tip00 intpp00 intp001 top01 intpp01 intp004 dmarq0 intp11 tclr10 intp005 dmarq1 intp10 tcud10 p00 = setting not required p00 = setting not required p00 = setting not required p00 = setting not required p00 = setting not required p01 = setting not required p01 = setting not required p01 = setting not required p04 = setting not required p04 = setting not required p04 = setting not required p04 = setting not required p05 = setting not required p05 = setting not required p05 = setting not required p05 = setting not required pm00 = setting not required pm00 = setting not required pm00 = setting not required pm00 = setting not required pm00 = setting not required pm01 = setting not required pm01 = setting not required pm01 = setting not required pm04 = setting not required pm04 = setting not required pm04 = setting not required pm04 = setting not required pm05 = setting not required pm05 = setting not required pm05 = setting not required pm05 = setting not required pmc00 = 1 pmc00 = 1 pmc00 = 1 pmc00 = 1 pmc00 = 1 pmc01 = 1 pmc01 = 1 pmc01 = 1 pmc04 = 1 pmc04 = 1 pmc04 = 1 pmc04 = 1 pmc05 = 1 pmc05 = 1 pmc05 = 1 pmc05 = 1 pfce00 = 0 pfce00 = 0 pfce00 = 1 pfce00 = 1 pfce00 = 1 pfce01 = 0 pfce01 = 0 pfce01 = 1 pfce04 = 0 pfce04 = 0 pfce04 = 1 pfce04 = 1 pfce05 = 0 pfce05 = 0 pfce05 = 1 pfce05 = 1 pfc00 = 0 pfc00 = 1 pfc00 = 0 pfc00 = 0 pfc00 = 0 pfc01 = 0 pfc01 = 1 pfc01 = 0 pfc04 = 0 pfc04 = 1 pfc04 = 0 pfc04 = 0 pfc05 = 0 pfc05 = 1 pfc05 = 0 pfc05 = 0 intr00 (intr0), intf00 (intf0) intr01 (intr0), intf01 (intf0) intr04 (intr0), intf04 (intf0) intr05 (intr0), intf05 (intf0)
chapter 4 port functions user?s manual u16397ej3v0ud 179 table 4-19. using alternate function of port pins (2/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? p06 p07 p10 p11 p12 p13 intp106 dmarq2 tms note intp107 dmarq3 tck note intp010 toqb1 intpq0 toq0 intp011 toqt1 intpq1 toq1 intp012 toqt2 intpq2 toq2 intp013 toqt3 intpq3 toq3 p06 = setting not required p06 = setting not required p06 = setting not required p07 = setting not required p07 = setting not required p07 = setting not required p10 = setting not required p10 = setting not required p10 = setting not required p10 = setting not required p11 = setting not required p11 = setting not required p11 = setting not required p11 = setting not required p12 = setting not required p12 = setting not required p12 = setting not required p12 = setting not required p13 = setting not required p13 = setting not required p13 = setting not required p13 = setting not required pm06 = setting not required pm06 = setting not required pm06 = setting not required pm07 = setting not required pm07 = setting not required pm07 = setting not required pm10 = setting not required pm10 = setting not required pm10 = setting not required pm10 = setting not required pm11 = setting not required pm11 = setting not required pm11 = setting not required pm11 = setting not required pm12 = setting not required pm12 = setting not required pm12 = setting not required pm12 = setting not required pm13 = setting not required pm13 = setting not required pm13 = setting not required pm13 = setting not required pmc06 = 1 pmc06 = 1 pmc06 = setting not required pmc07 = 1 pmc07 = 1 pmc07 = setting not required pmc10 = 1 pmc10 = 1 pmc10 = 1 pmc10 = 1 pmc11 = 1 pmc11 = 1 pmc11 = 1 pmc11 = 1 pmc12 = 1 pmc12 = 1 pmc12 = 1 pmc12 = 1 pmc13 = 1 pmc13 = 1 pmc13 = 1 pmc13 = 1 pfc06 = 0 pfc06 = 1 pfc06 = setting not required pfc07 = 0 pfc07 = 1 pfc07 = setting not required pfc10 = 0 pfc10 = 1 pfc10 = 0 pfc10 = 1 pfc11 = 0 pfc11 = 1 pfc11 = 0 pfc11 = 1 pfc12 = 0 pfc12 = 1 pfc12 = 0 pfc12 = 1 pfc13 = 0 pfc13 = 1 pfc13 = 0 pfc13 = 1 pfce10 = 0 pfce10 = 0 pfce10 = 1 pfce10 = 1 pfce11 = 0 pfce11 = 0 pfce11 = 1 pfce11 = 1 pfce12 = 0 pfce12 = 0 pfce12 = 1 pfce12 = 1 pfce13 = 0 pfce13 = 0 pfce13 = 1 pfce13 = 1 intr06 (intr0), intf06 (intf0) intr07 (intr0), intf07 (intf0) intr10 (intr1), intf10 (intf1) intr11 (intr1), intf11 (intf1) intr12 (intr1), intf12 (intf1) intr13 (intr1), intf13 (intf1) input input input input input input input output input output input output input output input output input output input output input output note the tms and tck pins are for on-chip debugging. to use the p06 and p07 pins as p06/intp106/dmarq2 and p07/intp107/dmarq3, be sure to input a low level to the trst pin. if a high level is input to the tr st pin, the values set to the p0 , pm0, pmc0, and pfc0 registers b ecome invalid, and the p06 and p07 pins function as the tms and tck pins.
chapter 4 port functions user?s manual u16397ej3v0ud 180 table 4-19. using alternate function of port pins (3/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ?? ? p14 p15 p20 p21 p22 p24 p25 intp114 toqb2 tiq intp115 toqb3 evtq nmi intp021 top10 evtp1 tip1 intpp10 intp022 top11 intpp11 intp124 tc0 intp125 tc1 tiud10 to10 p14 = setting not required p14 = setting not required p14 = setting not required p15 = setting not required p15 = setting not required p15 = setting not required p20 = setting not required p21 = setting not required p21 = setting not required p21 = setting not required p21 = setting not required p21 = setting not required p22 = setting not required p22 = setting not required p22 = setting not required p24 = setting not required p24 = setting not required p25 = setting not required p25 = setting not required p25 = setting not required p25 = setting not required pm14 = setting not required pm14 = setting not required pm14 = setting not required pm15 = setting not required pm15 = setting not required pm15 = setting not required pm21 = setting not required pm21 = setting not required pm21 = setting not required pm21 = setting not required pm21 = setting not required pm22 = setting not required pm22 = setting not required pm22 = setting not required pm24 = setting not required pm24 = setting not required pm25 = setting not required pm25 = setting not required pm25 = setting not required pm25 = setting not required pmc14 = 1 pmc14 = 1 pmc14 = 1 pmc15 = 1 pmc15 = 1 pmc15 = 1 pmc21 = 1 pmc21 = 1 pmc21 = 1 pmc21 = 1 pmc21 = 1 pmc22 = 1 pmc22 = 1 pmc22 = 1 pmc24 = 1 pmc24 = 1 pmc25 = 1 pmc25 = 1 pmc25 = 1 pmc25 = 1 pfc14 = 0 pfc14 = 1 pfc14 = 0 pfc15 = 0 pfc15 = 1 pfc15 = 0 pfc21 = 0 pfc21 = 1 pfc21 = 0 pfc21 = 0 pfc21 = 0 pfc22 = 0 pfc22 = 1 pfc22 = 0 pfc24 = 0 pfc24 = 1 pfc25 = 0 pfc25 = 1 pfc25 = 0 pfc25 = 1 pfce14 = 0 pfce14 = 0 pfce14 = 1 pfce15 = 0 pfce15 = 0 pfce15 = 1 pfce21 = 0 pfce21 = 0 pfce21 = 1 pfce21 = 1 pfce21 = 1 pfce22 = 0 pfce22 = 0 pfce22 = 1 pfce25 = 0 pfce25 = 0 pfce25 = 1 pfce25 = 1 intr14 (intr1), intf14 (intf1) intr15 (intr1), intf15 (intf1) nmif0 (nmif), nmir0 (nmir) intr21 (intr2), intf21 (intf2) intr22 (intr2), intf22 (intf2) intr24 (intr2), intf24 (intf2) intr25 (intr2), intf25 (intf2) input output input input output input input input output input input input input output input input output input output input output
chapter 4 port functions user?s manual u16397ej3v0ud 181 table 4-19. using alternate function of port pins (4/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? p26 p27 p30 p31 p32 p33 p34 p37 intp126 tc2 tdi note 1 tc3 tdo note 1 intp130 txd2 so2 intp131 rxd2 si2 intp132 asck2 sck2 intp133 txd3 sda note 2 intp134 rxd3 scl note 2 intp137 adtrg p26 = setting not required p26 = setting not required p26 = setting not required p27 = setting not required p27 = setting not required p30 = setting not required p30 = setting not required p30 = setting not required p31 = setting not required p31 = setting not required p31 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required p33 = setting not required p33 = setting not required p33 = setting not required p34 = setting not required p34 = setting not required p34 = setting not required p37 = setting not required p37 = setting not required pm26 = setting not required pm26 = setting not required pm26 = setting not required pm27 = setting not required pm27 = setting not required pm30 = setting not required pm30 = setting not required pm30 = setting not required pm31 = setting not required pm31 = setting not required pm31 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pm33 = setting not required pm33 = setting not required pm33 = setting not required pm34 = setting not required pm34 = setting not required pm34 = setting not required pm37 = setting not required pm37 = setting not required pmc26 = 1 pmc26 = 1 pmc26 = setting not required pmc27 = 1 pmc27 = setting not required pmc30 = 1 pmc30 = 1 pmc30 = 1 pmc31 = 1 pmc31 = 1 pmc31 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmc33 = 1 pmc33 = 1 pmc33 = 1 pmc34 = 1 pmc34 = 1 pmc34 = 1 pmc37 = 1 pmc37 = 1 pfc26 = 0 pfc26 = 1 pfc26 = setting not required pfc30 = 0 pfc30 = 1 pfc30 = 0 pfc31 = 0 pfc31 = 1 pfc31 = 0 pfc32 = 0 pfc32 = 1 pfc32 = 0 pfc33 = 0 pfc33 = 1 pfc33 = 0 pfc34 = 0 pfc34 = 1 pfc34 = 0 pfce30 = 0 pfce30 = 0 pfce30 = 1 pfce31 = 0 pfce31 = 0 pfce31 = 1 pfce32 = 0 pfce32 = 0 pfce32 = 1 pfce33 = 0 pfce33 = 0 pfce33 = 1 pfce34 = 0 pfce34 = 0 pfce34 = 1 intr26 (intr2), intf26 (intf2) intr30 (intr3), intf30 (intf3) intr31 (intr3), intf31 (intf3) intr32 (intr3), intf32 (intf3) intr33 (intr3), intf33 (intf3) intr34 (intr3), intf34 (intf3) intr37 (intr3), intf37 (intf3) input output input output output input output output input input input input input i/o input output i/o input input i/o input output notes 1. tdi and tdo pins are for on-chip debugging. to use the p26 and p27 pins as p26/intp126/tc2 and p27/tc3, be sure to input a lo w level to the trst pin. if a high level is input to the trst pin, the values set to the p2, pm2, pmc2, and pfc2 registers become invalid, an d the p06 and p07 pins function as the tdi and tdo pins. 2. i 2 c bus versions (y products) (see table 1-1 ) when the p33 and p34 pins are used as the sda and scl pins, resp ectively, they function as dummy open-drain output pins (p-ch is always off).
chapter 4 port functions user?s manual u16397ej3v0ud 182 table 4-19. using alternate function of port pins (5/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? p40 p41 p42 p43 p44 p45 p50 p51 so0 txd0 si0 rxd0 sck0 asck0 so1 txd1 si1 rxd1 sck1 asck1 intp050 top20 evtp2 tip2 intpp20 intp051 top21 intpp21 p40 = setting not required p40 = setting not required p41 = setting not required p41 = setting not required p42 = setting not required p42 = setting not required p43 = setting not required p43 = setting not required p44 = setting not required p44 = setting not required p45 = setting not required p45 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required pm40 = setting not required pm40 = setting not required pm41 = setting not required pm41 = setting not required pm42 = setting not required pm42 = setting not required pm43 = setting not required pm43 = setting not required pm44 = setting not required pm44 = setting not required pm45 = setting not required pm45 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pm51 = setting not required pm51 = setting not required pm51 = setting not required pmc40 = 1 pmc40 = 1 pmc41 = 1 pmc41 = 1 pmc42 = 1 pmc42 = 1 pmc43 = 1 pmc43 = 1 pmc44 = 1 pmc44 = 1 pmc45 = 1 pmc45 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc51 = 1 pmc51 = 1 pmc51 = 1 pfc40 = 0 pfc40 = 1 pfc41 = 0 pfc41 = 1 pfc42 = 0 pfc42 = 1 pfc43 = 0 pfc43 = 1 pfc44 = 0 pfc44 = 1 pfc45 = 0 pfc45 = 1 pfc50 = 0 pfc50 = 1 pfc50 = 0 pfc50 = 0 pfc50 = 0 pfc51 = 0 pfc51 = 1 pfc51 = 0 pfce50 = 0 pfce50 = 0 pfce50 = 1 pfce50 = 1 pfce50 = 1 pfce51 = 0 pfce51 = 0 pfce51 = 1 intr50 (intr5), intf50 (intf5) intr51 (intr5), intf51 (intf5) output output input input i/o input output output input input i/o input input output input input input input output input
chapter 4 port functions user?s manual u16397ej3v0ud 183 table 4-19. using alternate function of port pins (6/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p70 p71 p72 p73 p74 p75 p76 p77 p80 p81 pal0 pal1 pal2 pal3 pal4 pal5 pal6 pal7 pal8 pal9 pal10 pal11 pal12 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ano0 ano1 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required p80 = setting not required p81 = setting not required pal0 = setting not required pal1 = setting not required pal2 = setting not required pal3 = setting not required pal4 = setting not required pal5 = setting not required pal6 = setting not required pal7 = setting not required pal8 = setting not required pal9 = setting not required pal10 = setting not required pal11 = setting not required pal12 = setting not required pmal0 = setting not required pmal1 = setting not required pmal2 = setting not required pmal3 = setting not required pmal4 = setting not required pmal5 = setting not required pmal6 = setting not required pmal7 = setting not required pmal8 = setting not required pmal9 = setting not required pmal10 = setting not required pmal11 = setting not required pmal12 = setting not required pmc70 = 1 pmc71 = 1 pmc72 = 1 pmc73 = 1 pmc74 = 1 pmc75 = 1 pmc76 = 1 pmc77 = 1 pmcal0 = 1 pmcal1 = 1 pmcal2 = 1 pmcal3 = 1 pmcal4 = 1 pmcal5 = 1 pmcal6 = 1 pmcal7 = 1 pmcal8 = 1 pmcal9 = 1 pmcal10 = 1 pmcal11 = 1 pmcal12 = 1 input input input input input input input input output output output output output output output output output output output output output output output
chapter 4 port functions user?s manual u16397ej3v0ud 184 table 4-19. using alternate function of port pins (7/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pal13 pal14 pal15 pah0 pah1 pah2 pah3 pah4 pah5 pah6 pah7 pah8 pah9 pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 pal13 = setting not required pal14 = setting not required pal15 = setting not required pah0 = setting not required pah1 = setting not required pah2 = setting not required pah3 = setting not required pah4 = setting not required pah5 = setting not required pah6 = setting not required pah7 = setting not required pah8 = setting not required pah9 = setting not required pdl0 = setting not required pdl1 = setting not required pdl2 = setting not required pdl3 = setting not required pdl4 = setting not required pdl5 = setting not required pdl6 = setting not required pdl7 = setting not required pdl8 = setting not required pdl9 = setting not required pmal13 = setting not required pmal14 = setting not required pmal15 = setting not required pmah0 = setting not required pmah1 = setting not required pmah2 = setting not required pmah3 = setting not required pmah4 = setting not required pmah5 = setting not required pmah6 = setting not required pmah7 = setting not required pmah8 = setting not required pmah9 = setting not required pmdl0 = setting not required pmdl1 = setting not required pmdl2 = setting not required pmdl3 = setting not required pmdl4 = setting not required pmdl5 = setting not required pmdl6 = setting not required pmdl7 = setting not required pmdl8 = setting not required pmdl9 = setting not required pmcal13 = 1 pmcal14 = 1 pmcal15 = 1 pmcah0 = 1 pmcah1 = 1 pmcah2 = 1 pmcah3 = 1 pmcah4 = 1 pmcah5 = 1 pmcah6 = 1 pmcah7 = 1 pmcah8 = 1 pmcah9 = 1 pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 output output output output output output output output output output output output output i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o
chapter 4 port functions user?s manual u16397ej3v0ud 185 table 4-19. using alternate function of port pins (8/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i/o i/o i/o i/o i/o i/o output output output output output output output output output output output output output output output output pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 pcs0 pcs1 pcs2 pcs3 pcs4 pcs5 pcs6 pcs7 pct0 pct1 ad10 ad11 ad12 ad13 ad14 ad15 cs0 cs1 cs2 iowr cs3 cs4 cs5 iord cs6 cs7 lwr ldqm lbe uwr udqm ube pdl10 = setting not required pdl11 = setting not required pdl12 = setting not required pdl13 = setting not required pdl14 = setting not required pdl15 = setting not required pcs0 = setting not required pcs1 = setting not required pcs2= setting not required pcs2 = setting not required pcs3 = setting not required pcs4 = setting not required pcs5 = setting not required pcs5 = setting not required pcs6 = setting not required pcs7 = setting not required pct0 = setting not required pct0 = setting not required pct0 = setting not required pct1 = setting not required pct1 = setting not required pct1 = setting not required pmdl10 = setting not required pmdl11 = setting not required pmdl12 = setting not required pmdl13 = setting not required pmdl14 = setting not required pmdl15 = setting not required pmcs0 = setting not required pmcs1 = setting not required pmcs2= setting not required pmcs2 = setting not required pmcs3 = setting not required pmcs4 = setting not required pmcs5 = setting not required pmcs5 = setting not required pmcs6 = setting not required pmcs7 = setting not required pmct0 = setting not required pmct0 = setting not required pmct0 = setting not required pmct1 = setting not required pmct1 = setting not required pmct1 = setting not required pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 pmccs0 = 1 pmccs1 = 1 pmccs2 = 1 pmccs2 = 1 pmccs3 = 1 pmccs4 = 1 pmccs5 = 1 pmccs5 = 1 pmccs6 = 1 pmccs7 = 1 pmcct0 = 1 pmcct0 = 1 pmcct0 = 1 pmcct1 = 1 pmcct1 = 1 pmcct1 = 1 pfccs2 = 0 pfccs2 = 1 pfccs5 = 0 pfccs5 = 1 pfcct0 = 0, note pfcct0 = 0/1, note pfcct0 = 1, note pfcct1 = 0, note pfcct1 = 0/1, note pfcct1 = 1, note note xwr output or xdqm output, or xbe output and xdqm output are automatically selected when the target memory is accessed (x = u or l).
chapter 4 port functions user?s manual u16397ej3v0ud 186 table 4-19. using alternate function of port pins (9/9) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pct4 pct5 pct6 pct7 pcm0 pcm1 pcm2 pcm3 pcm4 pcd0 pcd1 pcd2 pcd3 pbd0 pbd1 pbd2 pbd3 rd wr we astb bcyst wait busclk hldak hldrq refrq sdcke sdclk sdcas sdras dmaak0 dmaak1 dmaak2 dmaak3 pct4 = setting not required pct5 = setting not required pct5 = setting not required pct6 = setting not required pct7 = setting not required pcm0 = setting not required pcm1 = setting not required pcm2 = setting not required pcm3 = setting not required pcm4 = setting not required pcd0 = setting not required pcd1 = setting not required pcd2 = setting not required pcd3 = setting not required pbd0 = setting not required pbd1 = setting not required pbd2 = setting not required pbd3 = setting not required pmct4 = setting not required pmct5 = setting not required pmct5 = setting not required pmct6 = setting not required pmct7 = setting not required pmcm0 = setting not required pmcm1 = setting not required pmcm2 = setting not required pmcm3 = setting not required pmcm4 = setting not required pmcd0 = setting not required pmcd1 = setting not required pmcd2 = setting not required pmcd3 = setting not required pmbd0 = setting not required pmbd1 = setting not required pmbd2 = setting not required pmbd3 = setting not required pmcct4 = 1 pmcct5 = 1 pmcct5 = 1 pmcct6 = 1 pmcct7 = 1 pmccm0 = 1 pmccm1 = 1 pmccm2 = 1 pmccm3 = 1 pmccm4 = 1 pmccd0 = 1 pmccd1 = 1 pmccd2 = 1 pmccd3 = 1 pmcbd0 = 1 pmcbd1 = 1 pmcbd2 = 1 pmcbd3 = 1 output output output output output input output output input output output output output output output output output output
chapter 4 port functions user?s manual u16397ej3v0ud 187 4.5 noise eliminator 4.5.1 interrupt input pin the following timing controller used to secure the noise elimination time is provided for the nmi and port pins that operate in the alternate-function mode when the valid edge is input. input signals that change within the noise elimination time are not internally acknowledged. table 4-20. noise elimination time of interrupt input pins pin noise elimination time nmi intp000 intp001 intp004 intp005 intp010 intp011 intp012 intp013 intp021 intp022 intp050 intp051 intp106 intp107 intp114 intp115 intp124 intp125 intp126 intp130 intp131 intp132 intp133 intp134 intp137 analog delay (80 ns typ.) cautions 1. the above non-maskab le and maskable interrupt pins are used to release the standby mode. a timing circuit that controls the clock is not employed becau se the internal system clock is stopped in the standby mode. 2. the noise eliminator is valid only in the alternate-function mode.
chapter 4 port functions user?s manual u16397ej3v0ud 188 4.5.2 timer enc1 input pins the following noise filter that operates via clock sampling is provided for the pins of timer enc1, which operates when the valid edge is input. input signals that change within the noise elimination time are not internally acknowledged. table 4-21. noise elimination ti me of timer enc1 input pins pin noise elimination time intp10/tcud10 intp11/tclr10 tiud10 f xx 3 cautions 1. the noise filter of the above pins ca nnot acknowledge an input signa l when the cpu clock is stopped because it uses clock sampling. 2. the noise eliminator is valid only when used as in tp10/tcud10, intp11/tclr10, and tiud10. 4.5.3 timer p and timer q input pins the following timing controller used to secure the noise elimi nation time is provided for the pins of timers p and q that operate when the valid edge is input. an input sign al that changes within the noise elimination time is not internally acknowledged. table 4-22. noise elimination time of timer p and timer q input pins pin noise elimination time evtp0/tip0/intpp00 intpp01 evtp1/tip1/intpp10 intpp11 evtp2/tip2/intpp20 intpp21 intpq0 intpq1 intpq2 intpq3 evtq tiq analog delay (80 ns typ.) caution the noise eliminat or is valid only in th e alternate-function mode.
chapter 4 port functions user?s manual u16397ej3v0ud 189 4.6 cautions 4.6.1 cautions on setting port pins (1) procedure to change mode from port mode to alternate-function mode change the mode of a port pin that f unctions as an output or i/o pin in the alternate-function mode to the alternate-function mode using the following procedure (except port 8). <1> set the inactive level of the signal to be output in the alternate-function mode to the corresponding bit of port n (n = 0 to 5, 7, al, ah, dl, cs, ct, cm, cd, bd). <2> select the alternate-function mode by us ing the port n mode control register (pmcn). if <1> is not performed, the contents of port n may be momentarily output when the mode is changed from the port mode to the alternate-function mode. (2) changing mode to exter nal interrupt input mode when the mode is changed from the port mode to the external interrupt input mode (intpa), an external interrupt may be generated if an incorrect valid edge is detected. disable (hold pending) (xxicn.xxmkn bit = 1) interrupt servicing by using the interrupt mask flag of the target interrupt control register, and perform the following procedure. (1) set the pfce register. (2) set the pfc register. (3) set the pmc register note . (4) set the intf and intr registers note . (5) clear the interrupt request flag (xxicn.xxifn bit = 0) note . (6) clear the interrupt mask flag (xxicn.xxmkn bit = 0). note make sure that 500 ns or more elapse between (3) and (5). it takes the level signal of the pin 80 ns (typ.) to reach the internal circuit after the pmc register has been set in (3) above, because the analog noise elimi nator of the external interrupt input pin (intpa) operates. remarks 1. to change the mode from the external interrupt input (intpa) mode to the port mode or the mode of other alternate-function mode, mask the external interrupt input with the xxicn.xxmkn bit. 2. xx: identification name of each peripheral unit (see table 20-2 .) n: peripheral unit number (see table 20-2 .) a = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137
chapter 4 port functions user?s manual u16397ej3v0ud 190 4.6.2 cautions on bit manipulation instruction for port n register (pn) when a bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewrit e (using st/ss instruction) the output latch when switching a port from input mode to output mode (including switching fr om alternate-function mode to port mode). when pcs0 pin is an output port, pcs1 to pcs7 pins are input ports (a ll pin statuses are high level), and the value of the port latch is 00h, if t he output of pcs0 pin is changed from low level to high level via a bit manipulation instruct ion, the value of the port latch is ffh. explanation: the targets of writing to and reading from the pn register of a port whose pmnm bit is 1 are the output latch and pin status, respectively. a bit manipulation instruction is executed in the following order in the v850e/ma3. <1> the pn register is read in 8-bit units. <2> the targeted one bit is manipulated. <3> the pn register is written in 8-bit units. in step <1>, the value of the output latch (0) of pc s0 pin, which is an output port, is read, while the pin statuses of pcs1 to pcs7 pins, which are inpu t ports, are read. if the pin statuses of pcs1 to pcs7 pins are high level at this time, the read value is feh. the value is changed to ffh by the manipulation in <2>. ffh is written to the output la tch by the manipulation in <3>. figure 4-40. bit manipulation instruction (pcs0 pin) low-level output bit manipulation instruction (set1 0, pcs[r0]) is executed for pcs0 bit. pin status: high level pcs0 pcs1 to pcs7 port cs latch 00000000 high-level output pin status: high level pcs0 pcs1 to pcs7 port cs latch 11111111 bit manipulation instruction for pcs0 bit <1> pcs register is read in 8-bit units.  in the case of pcs0, an output port, the value of the port latch (0) is read.  in the case of pcs1 to pcs7, input ports, the pin status (1) is read. <2> set (1) pcs0 bit. <3> write the results of <2> to the output latch of pcs register in 8-bit units.
chapter 4 port functions user?s manual u16397ej3v0ud 191 4.6.3 hysteresis characteristics in port mode, the following port pins do not have hysteresis characteristics. p00, p01, p04 to p07 p10 to p15 p20 to p22, p24 to p26 p30 to p34, p37 p41, p42, p44, p45 p50, p51
user?s manual u16397ej3v0ud 192 chapter 5 bus control function the v850e/ma3 is provided with an external bus interface function via which external memories such as rom and ram, and i/o can be connected. 5.1 features 16-bit/8-bit data bus sizing function 8-space chip select function wait function ? programmable wait function of up to 7 states for each memory block ? external wait function using wait pin idle state insertion function bus arbitration function bus hold function connectable to external device with alternate-function port pin separate bus mode/multiplexed bus mode selectable 5.2 bus control pins the pins used to connect an external device are listed in the table below. bus control pin (function in alternate-function mode) function in port mode port mode/alternate-function mode switching registers address/data bus (ad0 to ad15) pdl0 to pdl15 (port dl) pmcdl address bus (a0 to a15) pal0 to pal15 (port al) pmcal address bus (a16 to a25) pah0 to pah9 (port ah) pmcah chip select (cs0 to cs7, iowr, iord) pcs0 to pcs7 (port cs) pmccs sdram synchronous control (sdcke, sdclk) pcd0, pcd1 (port cd) sdram control (sdcas, sdras) pcd2, pcd3 (port cd) pmccd read/write control (lbe/lwr/ldqm, ube/uwr/udqm, rd, wr/we) pct0, pct1, pct4, pct5 (port ct) address strobe control (astb) pct6 (port ct) bus cycle start (bcyst) pct7 (port ct) pmcct external wait control (wait) pcm0 (port cm) bus clock (busclk) pcm1 (port cm) bus hold control (hldrq, hldak) pcm2, pcm3 (port cm) sdram refresh control (refrq) pcm4 (port cm) pmccm
chapter 5 bus control function user?s manual u16397ej3v0ud 193 (1) a0 to a15 these are the address output pins of the lower 16 bits of the address bu s?s 26-bit address when the external memory is accessed. the output changes in synchronization with the rising edge of the busclk signal in the t1 state. in the idle state (ti), the address of the bus cycl e immediately before is retained. (2) a16 to a25 these are the address output pins of the higher 10 bits of the address bus?s 26-bit address when the external memory is accessed. the output changes in synchronization with the rising edge of the busclk signal in the t1 state. in the idle state (ti), the address of the bus cycl e immediately before is retained. (3) ad0 to ad15 these pins form a multiplexed address/ data bus when the external memory is accessed. in the multiplexed bus mode, this bus outputs an address and inputs/out puts data. it inputs/outputs data in the separate bus mode. (4) cs0 to cs7 these are the chip select signal output pins for the sram, extern al rom, external peripheral i/o, page rom, and sdram area. the csn signal is assigned to memory block n (n = 0 to 7). it becomes active while the bus cycle that accesses the correspondi ng memory block is activated. in the idle state (ti), it becomes inactive. (5) iowr this is a write strobe signal output pin for external i/o during dma flyb y transfer. it indicates whether the bus cycle currently being executed is a write cycl e for external i/o during dma flyby transfer. note that if the ioen bit of the bu s cycle period control register (bcp) is set (1), this signal can be output even in the normal sram, external rom, or external i/o cycle. (6) iord this is a read strobe signal output pin for external i/o during dma flyby transfer. it indicates whether the bus cycle currently being executed is a read cycle for external i/o during dma flyby transfer. note that if the ioen bit of the bcp register is se t (1), this signal can be output even in the normal sram, external rom, or external i/o cycle. (7) lwr this is a strobe signal output pin that indicates that the bus cycle currently being executed is a write cycle for the sram, external rom, or external peripheral i/o area. for the data bus, the lower byte (d0 to d7) becomes valid. if the bus cycle is a lower memory write, it becomes active at the falling edge of the busclk signal in the t1 stat e and becomes inactive at the falling edge of the busclk signal in t he t2 state (in separate bus mode). (8) uwr this is a strobe signal output pin that indicates that the bus cycle currently being executed is a write cycle for the sram, external rom, or external peripheral i/o area. for the data bus, the higher byte (d8 to d15) becomes valid. if the bus cycle is a higher byte memory write, it becomes active at the falling edge of the busclk signal in the t1 stat e and becomes inactive at the falling edge of the busclk signal in t he t2 state (in separate bus mode).
chapter 5 bus control function user?s manual u16397ej3v0ud 194 (9) ldqm this is a pin for outputting the data bus control signal to sdram. for the data bus, the lower byte (d0 to d7) is valid. this signal controls sdram output disable during a read operation, and sdram byte masking during a write operation. (10) udqm this is a pin for outputting the data bus control signal to sdram. for the data bus, the higher byte (d8 to d15) is valid. this signal controls sdram out put disable during a read operation, and sdram byte masking during a write operation. (11) lbe this is a signal output pin that enables the lo wer byte (d0 to d7) of the external data bus. (12) ube this is a signal output pin that enables the higher byte (d8 to d15) of the external data bus. (13) rd this is a strobe signal output pin that indicates that the bus cycle current ly being executed is a read cycle for the sram, external rom, external peripheral i/o, or page rom area. (14) we this is a enable signal out put pin that indicates that the bus cycle currently being executed is a write cycle for the sdram area. (15) wr this is a strobe signal output pin t hat indicates that the bus cycle current ly being executed is a write cycle for the sram, external rom, or external peripheral i/o area. it becomes active at the falling edge of the busclk signa l in the t1 state and becomes inactive at the falling edge of the busclk signal in t he t2 state (in separate bus mode). (16) astb this pin outputs a latch strobe signal for the external address bus. the output signal goes low at the fa lling edge of the busclk signal in the t1 state of a bus cycle, and goes high at the falling edge of the bu sclk signal in the t3 state. (17) bcyst this is a status signal output pin t hat shows the start of the bus cycle. it becomes active for 1 clock cycle from the start of each cycle. in the idle state (ti), it becomes inactive. (18) wait this is the control signal input pin from which a data wait is inserted in the bus cycle. the wait signal can be input asynchronously to the busclk signal. when the busclk signal rises, sampling is executed (in separate bus mode). if the set/hold time is not satisfie d within the sampling timing, wait insertion may not be executed.
chapter 5 bus control function user?s manual u16397ej3v0ud 195 (19) hldak this is the acknowledge signal output pin that indica tes the high impedance status for the address bus, data bus, and control bus when the v850e/ma3 receives a bus hold request. while this signal is active, the impedance of the addr ess bus, data bus, and control bus becomes high and the bus mastership is transferred to the external bus master. (20) hldrq this is the input pin through which an external device requests the v850e/ma3 to release the address bus, data bus, and control bus. the hldrq signal can be input asynchronously to the busclk signal. when this pin is active, the address bus, data bus, and cont rol bus are set to the high impedance status. this occurs either when the v850e/ma3 completes execution of the current bus cycle or immediately if no bus cycle is being executed, then the hldak signal is activated and the bus is released. in order to make the bus hold state secure, keep t he hldrq signal active until the hldak signal is output. (21) refrq this is the refresh request signal output pin for sdram. this signal becomes active during the refresh cycle. also, during bus hold, it becomes active when a refresh request is generated and informs the external bus master that a refresh request was generated. (22) busclk this is a clock output pin for external bus interface. (23) sdcke this is the sdram clock enable output signal. it becomes inactive in self-refresh and standby mode. (24) sdclk this is a clock output pin dedicated to sdram. it al ways outputs a clock of the same frequency as that of busclk. (25) sdcas this is a command output signal for sdram. (26) sdras this is a command output signal for sdram. 5.2.1 pin status when internal rom, intern al ram, or on-chip peripheral i/o is accessed the address bus outputs a low level when the internal rom, internal ram, or on-chip peripheral i/o is accessed. the data bus goes into a high-impedanc e state without outputting anything. t he external bus control signal is deasserted.
chapter 5 bus control function user?s manual u16397ej3v0ud 196 5.3 memory block function the 256 mb memory space is divided into memory blocks of 2 mb and 64 mb. the programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. note that the 64 mb spac e of 0000000h to 3fffffh c an be used as a program area. on-chip peripheral i/o area (4 kb) internal ram area (60 kb note 1 ) external memory area external memory area block 1 (2 mb) block 0 (2 mb) block 2 (2 mb) block 3 (2 mb) 64 mb 64 mb block 5 (2 mb) block 6 (2 mb) block 4 (2 mb) block 7 (2 mb) on-chip peripheral i/o area (4 kb) note 2 internal ram area (60 kb note 1 ) internal rom area (1 mb) cs7, cs6, cs5 area 3 area 2 area 1 area 0 cs6 cs4 cs1 cs3 cs2, cs1, cs0 fffffffh fe00000h fdfffffh fc00000h fbfffffh fffffffh ffff000h fffefffh fff0000h 3ffffffh 3fff000h 3ffefffh 3ff0000h 00fffffh 0000000h fa00000h f9fffffh f800000h f7fffffh c000000h bffffffh 8000000h 7ffffffh 4000000h 3ffffffh 0800000h 07fffffh 0600000h 05fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h notes 1. 8/16/32 kb (see table 1-1 ) 2. accessing addresses 3fff000h to 3ffffffh is prohibited. to a ccess the on-chip peripheral i/o, specify addresses ffff000h to fffffffh.
chapter 5 bus control function user?s manual u16397ej3v0ud 197 5.3.1 chip select control function each memory block can be divided by using the csc0 and csc1 registers to control the chip select signal. by using these chip select functions, the memory bloc k can be divided to enable effective use of the memory space. the allocation of the memory blocks is shown below. (1) chip area select control registers 0, 1 (csc0, csc1) each bit of this register becomes valid when set to 1. if different chip select signals are set to the same block, the priority is controlled as follows. csc0: cs0 > cs2 > cs1 csc1: cs7 > cs5 > cs6 if both the csc0.cs0n and csc0.cs2n bits are cleared to 00, cs1 is output to the corresponding block (n = 0 to 3). similarly, if both the csc1.cs5n and csc1.cs7n bits are cleared to 0, cs6 is output to the corresponding block (n = 0 to 3). reset input sets these registers to 2c11h. caution write to the csc0 and csc1 registers afte r reset, and then do not change the set values. cs33 cs13 csc0 cs32 cs12 cs31 cs11 cs30 cs10 cs23 cs03 cs22 cs02 cs21 cs01 cs20 cs00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 cs43 cs63 csc1 cs42 cs62 cs41 cs61 cs40 cs60 cs53 cs73 cs52 cs72 cs51 cs71 cs50 cs70 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 2c11h r/w address: csc0 fffff060h, csc1 fffff062h caution for details of the csnm bit, see table 5-1 specification of chip select signal (csn) (n = 0 to 7, m = 0 to 3).
chapter 5 bus control function user?s manual u16397ej3v0ud 198 table 5-1. specification of chip select signal (csn) csnm bit cs operation cs00 cs0 is output when block 0 is accessed. cs01 cs0 is output when block 1 is accessed. cs02 cs0 is output when block 2 is accessed. cs03 cs0 is output when block 3 is accessed. cs10 to cs13 setting is meaningless. cs20 cs2 is output when block 0 is accessed. cs21 cs2 is output when block 1 is accessed. cs22 cs2 is output when block 2 is accessed. cs23 cs2 is output when block 3 is accessed. cs30 to cs33 setting is meaningless. cs40 to cs43 setting is meaningless. cs50 cs5 is output when block 7 is accessed. cs51 cs5 is output when block 6 is accessed. cs52 cs5 is output when block 5 is accessed. cs53 cs5 is output when block 4 is accessed. cs60 to cs63 setting is meaningless. cs70 cs7 is output when block 7 is accessed. cs71 cs7 is output when block 6 is accessed. cs72 cs7 is output when block 5 is accessed. cs73 cs7 is output when block 4 is accessed. caution the chip select signal (csn) can be enab led by setting the csnm bit to 1 (n = 0 to 7, m = 0 to 3). the cs signal that is enabled for area 0 when the csc0 register is set to 0703h is shown below. if the csc0 register is set to 0703h, cs0 and cs2 ar e output to both block 0 and 1. because cs0 takes precedence over cs2, however, cs0 is output w hen an address of block 0 or 1 is accessed. when an address of block 3 is accessed, cs1 is output because both the csc0.cs03 and csc0.cs23 bits are 0.
chapter 5 bus control function user?s manual u16397ej3v0ud 199 figure 5-1. example where csc0 register is set to 0703h block 2 (2 mb) block 3 (2 mb) block 1 (2 mb) block 0 (2 mb) cs1 output cs2 output cs0 output 58 mb 2 mb 4 mb 3ffffffh 0800000h 07fffffh 0600000h 05fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h
chapter 5 bus control function user?s manual u16397ej3v0ud 200 5.4 bus cycle type control function the v850e/ma3 can directly connect the following external devices to each memory block. ? sram, external rom, external i/o ? page rom ? sdram the external device to be connected is specified by using the bct0 and bct1 registers. 5.4.1 bus cycle type configuratio n registers 0, 1 (bct0, bct1) (1) bus cycle type configuration registers 0, 1 (bct0, bct1) these registers can be read or written in 16-bit units. reset input sets these registers to 8888h. cautions 1. write to the bct0 and bct1 registers af ter reset, and then do not change the set values (however, the men bit value can be changed) . also, do not access an external memory area other than the one for this initializati on routine until the initial settings of the bct0 and bct1 registers are complete. however, ex ternal memory areas whose initial settings are complete may be accessed. 2. to connect external i/o, page rom, or s dram, set the bus mode of the csn space to the separate bus mode (n = 0 to 7). 3. when accessing a csn space set in the mult iplexed bus mode, do not use the iord and iowr signals (n = 0 to 7). 4. in a system that uses both the multiple xed bus mode and separate bus mode, set the number of address setup wait states corresponding to the csn space set in the multiplexed bus mode to 1 or more (n = 0 to 7).
chapter 5 bus control function user?s manual u16397ej3v0ud 201 me3 me1 bct0 mm3 mm1 bt31 bt11 bt30 bt10 me2 me0 mm2 mm0 bt21 bt01 bt20 bt00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 me7 me5 bct1 mm7 mm5 bt71 bt51 bt70 bt50 me6 me4 mm6 mm4 bt61 bt41 bt60 bt40 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 8888h r/w address: bct0 fffff480h, bct1 fffff482h btn1 0 0 1 1 btn0 0 1 0 1 sram, external i/o page rom setting prohibited sdram: n = 1, 3, 4, 6 setting prohibited: n = 0, 2, 5, 7 specify the device to be connected to the csn signal (n = 0 to 7) cs3 csn signal csn signal csn signal csn signal cs1 cs7 cs5 cs2 cs0 cs6 cs4 men 0 1 operation disabled operation enabled enable the operation of the memory controller in each csn space (n = 0 to 7) mmn 0 1 separate bus mode multiplexed bus mode set the bus mode of each csn space (n = 0 to 7)
chapter 5 bus control function user?s manual u16397ej3v0ud 202 5.4.2 chip select signal delay control register (csdc) (1) chip select signal delay control register (csdc) if the external device of the sram (including external i/o) interface is accessed immediately a fter sdram is accessed, the external device of the sram may be written by mistake. if there is a possibility that the external device of the sram interface is written by mistake in a system that uses both the sdram and external device of the sram (including external i/o) interface, delay the falling of the csn signal of sram (i ncluding external i/o) one clock by using this csdc register (n = 0, 4, 6, or 7). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions 1. be sure to allocate an external device that may be written by mistake to the csn space of cs0, cs4, cs6, or cs7. also set the type of the memory of the csn space to which the external device is allocated to sram (btn1, btn0 bits of bct0, bct1 registers = 00) (n = 0, 4, 6, or 7). 2. in the csn space where the cs dcn bit is set to 1, be sure to insert one or more address setup wait states (the necessary number of wait states + 1), by using the asc register (n = 0, 4, 6, or 7). 3. do not change the csdcn bit for th e csn space where the program currently under execution is allocated (n = 0, 4, 6, or 7). csdc7 csdc csdc6 0 csdc4 0 0 0 csdc0 654321 after reset: 00h r/w address: fffff804h 7 0 remark when the csdcn bit is set to 1, the falling of the corresponding csn signal is delayed by one clock (n = 0, 4, 6, or 7). the output timing of the signals other than the csn signal remains unchanged. an example of timing chart where the csdc.csdcn bit is set to 1 is shown below.
chapter 5 bus control function user?s manual u16397ej3v0ud 203 figure 5-2. example of sram access timing immediately after sdram access (if sram is accessed two times in a row after sdram is accessed) (a) sram setting (address setup wait inserted, csdc.csdcn bit = 1, xdqm/xbe/xwr pin as xdqm/xwr output) busclk (output) sdclk (output) t0 note sdram access sram access sram access twr tasw t1 t2 tasw t1 t2 a0 to a25 (output) bcyst (output) xdqm (output) xwr (output) wr (output) we (output) signal output timing is delayed by 1 clock. timing varies in range of ac characteristics. csm (output) (sdram space) csn (output) (sram space) caution the timing is the same e ven when the xdqm/xbe/xwr pin is used as xdqm/xbe output pin. note this state is inserted between bus cycles (t0). remark m = 1, 3, 4, or 6 n = 0, 4, 6, or 7 m n x = u or l
chapter 5 bus control function user?s manual u16397ej3v0ud 204 5.5 bus access 5.5.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. bus cycle type resource (bus width) instruction fetch operand data access internal rom (32 bits) 1 7 internal ram (32 bits) 1 note 1 note 2 if a conflict with a data access occurs. remark unit: clocks/access 5.5.2 bus sizing function the bus sizing function controls the data bus width of each cs space. the data bus width is set by using the lbs register. (1) local bus sizing control register (lbs) this register can be read or written in 16-bit units. reset input sets this register to 5555h. cautions 1. write to the lbs register after reset, a nd then do not change the set values. also, do not access an external memory area ot her than the one for this in itialization routine until the initial settings of the lbs register are comp lete. however, external memory areas whose initial settings are complete may be accessed. 2. only the following signal is asse rted if the bus width is 8 bits. lwr: to access sram, external rom, or external i/o (write cycle) 0 0 lbs lb70 lb30 0 0 lb60 lb20 0 0 lb50 lb10 0 0 lb40 lb00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 5555h r/w address: fffff48eh cs6 cs7 cs3 csn signal csn signal cs2 cs5 cs1 cs4 cs0 lbn0 0 1 8 bits 16 bits setting of data bus width of a csn space (n = 0 to 7) caution be sure to clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?. the operation cannot be guaranteed if these bits are set to 1.
chapter 5 bus control function user?s manual u16397ej3v0ud 205 5.5.3 endian control function the endian control function is used to specify whether the word data in the memory of the cs space selected by the chip select signal (cs0 to cs7) is processed in bi g-endian or little-endian mode. the endianness is selected by using the bec register. caution the following areas are fixe d to little-endian mode and thus the setting of the bec register is invalid. ? on-chip peripheral i/o area ? internal rom area ? internal ram area ? program fetch area of external memory (1) endian configuration register (bec) this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution write to the bec register after reset , and then do not change the set values. 0 0 bec be70 be30 0 0 be60 be20 0 0 be50 be10 0 0 be40 be00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 0000h r/w address: fffff068h cs6 cs7 cs3 cs2 cs5 cs1 cs4 cs0 ben0 0 1 little-endian mode big-endian mode specification of endian mode of each csn space (n = 0 to 7) csn signal csn signal caution be sure to clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?. the operation cannot be guaranteed if these bits are set to 1. figure 5-3. big-endian address in word 0008h 0009h 000ah 000bh 0004h 0005h 0006h 0007h 0000h 0001h 0002h 0003h 31 24 23 16 15 8 7 0
chapter 5 bus control function user?s manual u16397ej3v0ud 206 figure 5-4. little-endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 5.5.4 restrictions on big endianness with nec electronics development tools (1) when debugger (id850) is used only the indication of the memory window supports big endian. (2) when compiler (ca850) is used (a) restriction of c language (i) the variables to be located in the big- endian space have the following restrictions. ? union cannot be used. ? bitfield cannot be used. ? access by cast (changing access size) cannot be used. ? variables with an initial value cannot be used. (ii) because the access size may be changed as a result of optimization, the following optimization suppressing options must be specified. ? for wide-area optimization block (opt850): ? wo, ? xtb ? for machine type dependent optimization block (impr850): ? wi, +arg_reg_opt = off, +stld_trans_opt = off
chapter 5 bus control function user?s manual u16397ej3v0ud 207 if an access by casting or masking/shifting is not used note , the above optimization suppressing options do not have to be specified. note this applies if a pattern that causes the follo wing optimization is not used. however, it is extremely difficult for the user to completely check this when each pattern (especially, machine type dependent optimization blocks) is combined. it is therefore recommended to specify the above optimization suppressing options. [wide area optimization block-related] ? setting 1 bit by using bit or int i; i ^ = 1; ? clearing 1 bit by using bit and i & = ~1; ? negating 1 bit by using bit xor i ^ = 1; ? testing 1 bit by using bit and if(i & 1); [machine type dependent opti mization block-related] use to enable accessing the same variable in a different size ? cast ? mask ? shift example : int i, *ip; char c; c =*((char*)ip); c = 0xff & i; i = (i<<24) >>24; (b) restriction of assembly language area securing quasi directives (.hword, .word, .float, and .shword) of a size other than byte size cannot be used for variables to be located in the big-endian space.
chapter 5 bus control function user?s manual u16397ej3v0ud 208 5.5.5 bus width the v850e/ma3 accesses the on-chip peripheral i/o and ex ternal memory in 8-bit, 16-bit, or 32-bit units. the operations when v850e/ma3 accesses the on-chip peripheral i/o and external me mory are described below. all data are sequentially accessed, starting from the lowest bit. (1) byte access (8 bits) (a) 16-bit data bus width (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus (c) 16-bit data bus width (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address byte data external data bus 7 0 7 0 15 8 2n + 1 address byte data external data bus
chapter 5 bus control function user?s manual u16397ej3v0ud 209 (d) 8-bit data bus width (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus (2) halfword access (16 bits) (a) with 16-bit data bus width (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width (little endian) <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus
chapter 5 bus control function user?s manual u16397ej3v0ud 210 (c) with 16-bit data bus width (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n + 1 15 8 2n address halfword data external data bus first access second access 7 0 7 0 15 8 15 8 2n + 1 7 0 7 0 15 8 15 8 2n + 2 address address halfword data external data bus halfword data external data bus (d) 8-bit data bus width (big endian) <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access first access second access 7 0 7 0 15 8 2n 7 0 7 0 15 8 2n + 1 halfword data external data bus address halfword data external data bus address 7 0 7 0 15 8 2n + 1 7 0 7 0 15 8 2n + 2 halfword data external data bus address halfword data external data bus address
chapter 5 bus control function user?s manual u16397ej3v0ud 211 (3) word access (32 bits) (a) 16-bit data bus width (little endian) (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16397ej3v0ud 212 (a) 16-bit data bus width (little endian) (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16397ej3v0ud 213 (b) 8-bit data bus width (little endian) (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16397ej3v0ud 214 (b) 8-bit data bus width (little endian) (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16397ej3v0ud 215 (c) 16-bit data bus width (big endian) (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n + 3 15 8 4n + 2 23 16 31 24 7 0 7 0 15 8 4n + 1 15 8 4n 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 3 15 8 4n + 2 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16397ej3v0ud 216 (c) 16-bit data bus width (big endian) (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 5 15 8 4n + 4 23 16 31 24 7 0 7 0 15 8 4n + 3 15 8 4n + 2 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 5 15 8 4n + 4 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16397ej3v0ud 217 (d) 8-bit data bus width (big endian) (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 4 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function user?s manual u16397ej3v0ud 218 (d) 8-bit data bus width (big endian) (2/2) <3> access to address (4n + 2) first access second access third access fourth access 7 0 7 0 15 8 4n + 5 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 6 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus word data external data bus word data external data bus word data external data bus address address address address
chapter 5 bus control function user?s manual u16397ej3v0ud 219 5.6 write buffer function the v850e/ma3 has an on-chip write buffer of 4 words (128 bits). the write buffer st ores data if a write cycle cannot be executed while the external bus is occupied note . the next instructions are speculatively executed until the write buffer becomes full. the write buffer is valid for all the external memory areas. if a write request is generated while the write buffer is full, the next instruction execution is postponed until there is a vacancy in the write buffer. while data is being stored in the write buffer (when a write operation to the external memory has not been completed), dma flyby and bus hold requests are not acknowledged (dma flyby and bus hold requests are acknowledged and an enable signal is generated after all the data of the write buffers has been written to the external memory). note the external bus is occupied when there is a bus cycle currently under execution. cautions 1. because the write buffer consists of f our stages, the write buffer becomes full after 4 bytes (32 bits) when a byte write operation is execute d. similarly, the conditions under which the write buffer becomes full vary due to an address miss-align access, etc. 2. when data is written to an external device , the write operation to the external device may not be executed even when a cpu write operation h as been completed by the write buffer. the cpu can access the on-chip peripheral i/o re gisters after the write operation has been completed even if the write buffer exists. there fore, if it is necessary to change the value of an on-chip peripheral i/o register after completi on of execution of an external memory cycle, write 00h to the was register be fore writing the on-chip peripheral i/o register whose value is to be changed. when writing an on-chip peri pheral i/o register other than the was register without writing 00h to the was register, the regi ster value may be changed before completion of the external memory cycle. 3. if an read access to the exte rnal device occurs when data ex ist in the write buffer, reading from the external device is executed after the writin g all data in the write buffer to the external device. 4. during 2-cycle transfer that writes data to the external device, the write operation to the external device may not be completed even if dchcn.tcn bit = 1 (dma transfer completion) is read by the write buffer (n = 0 to 3). if it is necessary to change the value of an on-chip peripheral i/o register after co mpletion of dma transfer (compl etion of a write operation to the external device), perform eith er of the following operations. ? monitor the tcn signal (the tcn signal beco mes active in synchronization with a write operation to the external device). ? after detecting setting (to 1) of the dchcn.tcn bit, write 00h to the was register and then change the value of the on-chip peripheral i/o regi ster. if the value of an on-chip peripheral i/o register other than the was register is ch anged without writing 00h to the was register, the value of the on-chip peripheral i/o register may be changed before completion of dma transfer.
chapter 5 bus control function user?s manual u16397ej3v0ud 220 (1) write access synchronization control register (was) when an external device is written, even if the write operation by the cp u via the write buffer is complete, writing to the external device may not be complete. the was register is used to complete writing all data in the write buffer to the external device. see 5.6 write buffer function for details. this register is write-only, in 8-bit units. 000000 00 76543210 was after reset: undefined w address: fffff49ch caution be sure to write 00h to the was register. operation cannot be guaranteed if value other than 00h is written.
chapter 5 bus control function user?s manual u16397ej3v0ud 221 5.7 bus clock control function (1) bus mode control register (bmc) the bmc register is used to set the division ratio of t he bus clock (busclk) with respect to the internal system clock. when this register is written, busclk stops once at the low level. busclk resumes operation using the divided clock that is set after busclk was stopped. while busclk is stopped, the operation of the rfsn register of sdram also stops (n = 1, 3, 4, 6). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. cautions 1. write to the bmc register afte r reset, and then do not change the set value. 2. be sure to write to the bmc register after setting the vswc register to x7h (x: vswc register value before the set value of the bm c register is changed). after changing the set value of the bmc register, re-set the value of the vswc register to the value before the set value of the bmc register was changed. [setting procedure] <1> save the set value of the vswc register. <2> set x7h to the vswc register (x: value of the vswc register before the set value of the bmc register is changed). <3> set the bmc register. (in the meantime, busclk once stops.) <4> restore the saved set value of the vswc register. 3. the maximum operating frequency of the ex ternal bus interface of the v850e/ma3 is 50 mhz. do not set a bus clock (busclk) or perform a setting sequence that may exceed this frequency. 0 bmc 0 0 0 0 0 ckm1 ckm0 after reset: 01h r/w address: fffff498h f clk f clk /2 f clk /3 f clk /4 ckm1 0 0 1 1 ckm0 0 1 0 1 specification of division ratio of busclk with respect to f clk caution be sure to clear bits 7 to 2 to ?0?. the operation cannot be guaranteed if these bits are set to 1. remark f clk : internal system clock
chapter 5 bus control function user?s manual u16397ej3v0ud 222 5.8 wait function 5.8.1 programmable wait function (1) data wait control registers 0, 1 (dwc0, dwc1) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle note that is executed for each cs space. the number of wait states can be programmed by using the dwc0 and dwc1 registers. immediately after system reset, 7 data wait states are inserted for all the blocks. these registers can be read or written in 16-bit units. reset input sets these registers to 7777h. note separate bus mode: sram read/write cycle page rom read cycle (off page) multiplexed bus mode: sram read/write cycle cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-ch ip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. the setting of the dwc0 and dwc1 registers is invalid in the following cases (wait control is performed by each memory controller). ? on-page access to page rom ? access to sdram 3. write to the dwc0 and dwc1 registers after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the dwc0 and dwc1 registers are complete. however, extern al memory areas whose initial settings are complete may be accessed.
chapter 5 bus control function user?s manual u16397ej3v0ud 223 0 0 dwc0 dw32 dw12 dw31 dw11 dw30 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 0 0 dwc1 dw72 dw52 dw71 dw51 dw70 dw50 0 0 dw62 dw42 dw61 dw41 dw60 dw40 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 7777h r/w address: dwc0 fffff484h, dwc1 fffff486h dwn2 dwn1 cs2 cs0 cs6 cs4 cs3 cs1 cs7 cs5 not inserted 1 2 3 4 5 6 7 specification of number of wait states to be inserted in csn space (n = 0 to 7) dwn0 csn signal csn signal csn signal csn signal 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
chapter 5 bus control function user?s manual u16397ej3v0ud 224 (2) address setup wait control register (asc) the v850e/ma3 can insert address setup wait states at the beginning of a read/write cycle of sram cycle and a read cycle of page rom cycle in the separate mode, and at the beginning of a read/ write cycle of sram in the multiplexed bus mode (the setting of the asc register is invalid in the sdram cycle). the number of address setup wait states can be set for each cs space by using the asc register. this register can be read or written in 16-bit units. reset input sets this register to ffffh. cautions 1. an address setup wa it state is not inserted in the in ternal rom area, in ternal ram area, and on-chip peripheral i/o area. 2. the external wait function that is effect ed by the wait pin is invalid when an address setup wait state is inserted. 3. write to the asc register after reset , and then do not change the set value. 4. the address setup wait setting value is valid during the dma flyby transfer. ac71 ac31 asc ac70 ac30 ac61 ac21 ac60 ac20 ac51 ac11 ac50 ac10 ac41 ac01 ac40 ac00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: ffffh r/w address: fffff48ah acn1 acn0 cs7 cs3 cs6 cs2 cs5 cs1 cs4 cs0 not inserted 1 2 3 specification of number of address setup wait states in csn space (n = 0 to 7) csn signal csn signal 0 0 1 1 0 1 0 1
chapter 5 bus control function user?s manual u16397ej3v0ud 225 (3) address hold wait control register (ahc) the ahc register inserts an address hold wait state bet ween the t1 cycle and t2 cycle of a read/write cycle of the sram cycle in the multiplexed bus mode. the number of address hold wait states to be insert ed can be specified for each cs space by using this register. this register can be read or written in 16-bit units. reset input sets this register to ffffh. cautions 1. an address hold wait state is not inser ted in the internal rom area, internal ram area, and on-chip peripheral i/o area. 2. the ahc register can be set only in the multiplexed bus mode. 3. the external wait function that is effected by the wait pin is invalid when an address hold wait state is inserted. 4. write to the ahc register after reset , and then do not change the set values. ah71 ah31 ahc ah70 ah30 ah61 ah21 ah60 ah20 ah51 ah11 ah50 ah10 ah41 ah01 ah40 ah00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: ffffh r/w address: fffff49eh ahn1 ahn0 cs7 cs3 cs6 cs2 cs5 cs1 cs4 cs0 not inserted 1 2 3 specification of number of address hold wait states in csn space (n = 0 to 7) csn signal csn signal 0 0 1 1 0 1 0 1
chapter 5 bus control function user?s manual u16397ej3v0ud 226 (4) bus cycle period control register (bcp) the v850e/ma3 can enable or disable the operations of iord and iowr in the sram, external rom, and external i/o cycles. this register can be read or written in 8-bit units. reset input clears this register to 00h. cautions 1. the iord and iowr signals are output , regardless of the setting of the ioen bit, during flyby dma transfer to transfer data to/from the sram, external rom, and external i/o. the setting of the ioen bit is meaningless in the page rom cycle. 2. write to the bcp register after reset , and then do not change the set values. 0 bcp 0 0 0 ioen 0 0 0 after reset: 00h r/w address: fffff48ch ioen 0 1 iord, iowr operation enable in the sram, external rom, and external i/o cycles disables the operations of iord, iowr. enables the operations of iord, iowr. caution be sure to clear bits 7 to 4 and 2 to 0 to ?0?. the operation cannot be guaranteed if these bits are set to 1.
chapter 5 bus control function user?s manual u16397ej3v0ud 227 (5) dma flyby transfer wait control register (fwc) the fwc register sets the number of data wait states for channel n during dma flyby transfer (n = 0 to 3). the set value of this register becomes valid during dma flyby transfer, and the set values of the dwc0, dwc1, and prc registers become invalid. this register can be read or written in 16-bit units. reset input sets this register to 7777h. cautions 1. wait states cannot be programmed for accessing the internal rom and internal ram areas, and these areas are alwa ys accessed without a wait state. wait states cannot be programmed for accessing the on-chip periphera l i/o area, and only the wait states that are inserted when each peripheral functi on accesses this area are controlled. 2. write to the fwc register after reset , and then do not change the set values. 0 0 fwc fw32 fw12 fw31 fw11 fw30 fw10 0 0 fw22 fw02 fw21 fw01 fw20 fw00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 7777h r/w address: fffff494h fwn2 fwn1 dma2 dma0 dma3 dma channel dma channel dma1 not inserted 1 2 3 4 5 6 7 specification of number of data waits in csn space during dma flyby transfer (n = 0 to 3) fwn0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
chapter 5 bus control function user?s manual u16397ej3v0ud 228 5.8.2 external wait function to synchronize an extremely slow external memory, i/o, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). access to each area of the internal rom, internal ram, a nd on-chip peripheral i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to busclk, and is sampled at the rising edge of the busclk signal immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sa mpling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. 5.8.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specifi ed by the set value of the programmable wait and the wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-5. example of inserting wait states t1 tw tw tw t2 busclk wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing.
chapter 5 bus control function user?s manual u16397ej3v0ud 229 5.8.4 bus cycle for which wait function is valid the v850e/ma3 can specify the number of wait states in accordance with t he type of the memory specified for each memory block. the bus cycle for which the wait function is valid and the register t hat specifies the number of wait states are shown below. table 5-2. bus cycle in which wait function is valid (a) in separate bus mode setting of programmable wait bus cycle wait type register bit number of waits wait by wait pin address setup wait asc acn1, acn0 0 to 3 (invalid) sram, external rom, external i/o cycle data wait dwc0, dwc1 dwn2 to dwn0 0 to 7 (valid) page rom cycle address setup wait asc acn1, acn0 0 to 3 (invalid) off-page data access wait dwc0, dwc1 dwn2 to dwn0 0 to 7 (valid) on-page data access wait prc prw2 to prw0 0 to 7 (valid) sdram cycle row address precharge scrm bcwm1, bcwm0 1 to 3 (invalid) flyby transfer wait fwc fwa2 to fwa0 0 to 7 (valid) dma flyby transfer cycle external i/o ? sram address setup wait asc acn1, acn0 0 to 3 (invalid) (b) in multiplexed bus mode setting of programmable wait bus cycle wait type register bit number of waits wait by wait pin address setup wait asc acn1, acn0 0 to 3 (invalid) address hold wait ahc ahn1, ahn0 0 to 3 (invalid) sram, external rom cycle data access wait dwc0, dwc1 dwn2 to dwn0 0 to 7 (valid) remark n = 0 to 7 m = 1, 3, 4, 6 a = 0 to 3
chapter 5 bus control function user?s manual u16397ej3v0ud 230 5.9 idle state insertion function (1) bus cycle control register (bcc) to establish interfacing with a low-speed memory easily and to secure the data output float delay time during a read access to each cs space, the specif ied number of idle states (ti) can be inserted after the t2 state in the bus cycle to be started. the bus cycle following t he t2 state starts after the inserted idle state. the timing of inserting an idle state is as follows. (a) in separate bus mode ? after read cycle or write cycle of sram, external i/o, and external rom ? after read cycle of page rom ? after read cycle of sdram (b) in multiplexed bus mode ? after read cycle or write cycle of sram and external rom whether the idle state is to be in serted can be programmed by using the bcc register. an idle state is inserted for all the blocks immediately after system reset. for the timing of inserti ng the idle state, see the access timing of each memory in chapter 6. this register can be read or written in 16-bit units. reset input sets this register to ffffh. cautions 1. the internal rom, internal ram, a nd on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. however, external memory areas w hose initial settings are complete may be accessed. 3. the chip select signal (csn) is not asserte d in the idle state (n = 0 to 7). bc71 bc31 bcc bc70 bc30 bc61 bc21 bc60 bc20 bc51 bc11 bc50 bc10 bc41 bc01 bc40 bc00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: ffffh r/w address: fffff488h bcn1 0 0 1 1 bcn0 0 1 0 1 cs7 cs3 cs6 cs2 cs5 cs1 cs4 cs0 not inserted 1 2 3 specification of number of idle states in csn space (n = 0 to 7) csn signal csn signal
chapter 5 bus control function user?s manual u16397ej3v0ud 231 (2) dma flyby transfer idle control register (fic) the fic register specifies the number of idle states during dma flyby transfer for dma channel n (n = 0 to 3). the idle state is inserted at the end of the dma flyby transfer. during the dma flyby transfer, the set value of this register becomes valid, and the set value of t he bus cycle control register (bcc) becomes invalid. this register can be read or written in 16-bit units. reset input sets this register to 3333h. cautions 1. the internal rom, internal ram, a nd on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the fic register after rese t, and then do not change the set values. 0 0 fic 0 0 fi31 fi11 fi30 fi10 0 0 0 0 fi21 fi01 fi20 fi00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 3333h r/w address: fffff496h fin1 fin0 dma3 dma1 dma2 dma0 not inserted 1 2 3 specification of number of idle states in csn space during dma flyby transfer (n = 0 to 3) dma channel dma channel 0 0 1 1 0 1 0 1
chapter 5 bus control function user?s manual u16397ej3v0ud 232 5.10 bus hold function 5.10.1 functional outline the hldak and hldrq functions are valid if the pcm2 and pcm3 pins are set to their alternate functions. when the hldrq pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus and each strobe pin go into a high-impedance state and the bus is released (bus hold status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the internal opera tion of the v850e/ma3 is continued until the external memory or an on-chip peripheral i/o register is accessed. the bus hold status is indicated by assertion of the hldak pin (low level). it takes the hldak pin at least two clocks to be asserted (low level) after the hldrq pin is asserted (low level). the bus hold function enables the conf iguration of a multiproce ssor type system in which two or more bus masters exist. status data bus width access type timing at which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access cautions 1. if the external bus master accesses sd ram during bus hold, make sure that the external bus master executes the all bank precharge command. to clear the bus hold status, the cpu always executes the all bank precharge command. the external bus master must not change the va lue of the command register of sdram during bus hold. 2. the hldrq function is invalid during the reset period. the hldak pin is asserted immediately after the reset pin has been deass erted after the reset and hldrq pins were asserted at the same time or after one clock addr ess cycle is inserted. if an external bus master other than the v850e/ma3 is connected, perform arbitration upon power application by using the reset signal.
chapter 5 bus control function user?s manual u16397ej3v0ud 233 5.10.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.10.3 operation in power save mode because the internal system clock is stopped in the so ftware stop and idle modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin is asserted, and the bus hold status is entered. when the hldrq pin is later deasserted, the hldak pin is also deasserted, and the bus hold status is cleared and return to the halt mode.
chapter 5 bus control function user?s manual u16397ej3v0ud 234 5.10.4 bus hold timing (1) when bus hold request is issued without bus cycle generated (bmc register = 01h) th th t0 note 2 undefined ti note 1 busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 3 (output) ad0 to ad15 (input) wait (input) rd (output) hldrq (input) hldak (output) undefined notes 1. idle state (ti) independent of bcc register setting 2. state (t0) inserted between bys cycles 3. lwr/lbe/ldqm, uwr/ube/udqm, we /wr, iord, iowr, sdras, sdcas remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 5 bus control function user?s manual u16397ej3v0ud 235 5.10.5 bus hold timing (sram) (1) sram (during read, no idle st ates inserted, bmc register = 01h) t0 note 1 data t1 t2 th th t0 note 1 ti note 2 address undefined busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 4 (output) ad0 to ad15 (input) wait (input) iord note 3 , rd (output) hldrq (input) hldak (output) wr, iowr (output) undefined notes 1. state (t0) inserted between bys cycles 2. idle state (ti) independe nt of bcc register setting 3. when bcp.ioen bit is set (1). 4. ube, lbe remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 5 bus control function user?s manual u16397ej3v0ud 236 (2) sram (during write, two idle st ates inserted, bmc register = 01h) th th t0 note 1 ti note 3 ti note 2 ti note 2 t1 t2 t0 note 1 address data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) note 5 (output) ad0 to ad15 (input) wait (input) iowr note 4 , wr (output) hldrq (input) hldak (output) rd, iord (output) undefined undefined notes 1. state (t0) inserted between bys cycles 2. idle state (ti) inserted according to the bcc register setting 3. idle state (ti) independent of the bcc register setting 4. when bcp.ioen bit is set (1). 5. ube, lbe remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 5 bus control function user?s manual u16397ej3v0ud 237 5.10.6 bus hold timing (sdram) (1) sdram (during read, latency = 2, no idle st ates inserted, 16-bit bus width halfword access, bmc register = 01h) row col. row address h undefined h tread tlate tlate tact t0 note 1 bnk. th th ti note 2 t0 note 1 tpre note 3 data busclk (output) a1 to a10 (output) csn (output) bcyst (output) note 5 (output) ad0 to ad15 (input) sdcke (output) sdras (output) hldrq (input) hldak (output) sdcas (output) note 6 (output) we (output) a11 (output) note 4 (output) bank address (output) undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined address notes 1. state (t0) inserted between bys cycles 2. idle state (ti) inserted according to the bcc register setting 3. always executes the all bank precharge command. 4. addresses other than bank address, a11, and a1 to a10 5. when xwr output mode/xdqm output mode is set (pfcct.pfcctm bit = 0) 6. when xbe output mode/xdqm output mode is set (pfcct.pfcctm bit = 1) remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, or 6 m = 0 or 1 xx = u or l 4. bnk.: bank address col.: column address row: row address
chapter 5 bus control function user?s manual u16397ej3v0ud 238 (2) sdram (during read, latency = 2, two idle st ates inserted, 16-bit bus width halfword access, bmc register = 01h) h data h tread row tlate tlate tact t0 note 1 row bnk. address th ti note 2 th t0 note 1 tpre note 4 ti note 3 ti note 2 col. busclk (output) a1 to a10 (output) csn (output) bcyst (output) note 6 (output) ad0 to ad15 (input) sdcke (output) sdras (output) hldrq (input) hldak (output) sdcas (output) note 7 (output) we (output) a11 (output) note 5 (output) bank address (output) undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined address notes 1. state (t0) inserted between bys cycles 2. idle state (ti) inserted according to the bcc register setting 3. idle state (ti) independent of the bcc register setting 4. always executes the all bank precharge command. 5. addresses other than bank address, a11, and a1 to a10 6. when xwr output mode/xdqm output mode is set (pfcct.pfcctm bit = 0) 7. when xbe output mode/xdqm output mode is set (pfcct.pfcctm bit = 1) remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, or 6 m = 0 or 1 xx = u or l 4. bnk.: bank address col.: column address row: row address
chapter 5 bus control function user?s manual u16397ej3v0ud 239 (3) sdram (during write, bmc register = 01h) h twr tact t0 note 1 address row col. bnk.a undefined th th ti note 2 t0 note 1 tpre note 3 data busclk (output) a1 to a10 (output) csn (output) bcyst (output) note 6 (output) ad0 to ad15 (i/o) sdcke (output) sdras (output) hldrq (input) hldak (output) sdcas (output) note 5 (output) we (output) a11 (output) note 4 (output) bank address (output) data undefined undefined undefined undefined undefined undefined undefined address row notes 1. state (t0) inserted between bys cycles 2. idle state (ti) inserted according to the bcc register setting 3. always executes the all bank precharge command. 4. addresses other than bank address, a11, and a1 to a10 5. when xwr output mode/xdqm output mode is set (pfcct.pfcctm bit = 0) 6. when xbe output mode/xdqm output mode is set (pfcct.pfcctm bit = 1) remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, or 6 m = 0 or 1 xx = u or l 4. bnk.: bank address col.: column address row: row address
chapter 5 bus control function user?s manual u16397ej3v0ud 240 (4) sdram (during write, bmc register = 01h, when bus hold request is acknowledged during on-page access) h tw t0 note 1 col. address data ti note 2 undefined th t0 note 1 tpre note 3 th bnk. busclk (output) a1 to a10 (output) csn (output) bcyst (output) ad0 to ad15 (i/o) sdcke (output) sdras (output) hldrq (input) hldak (output) sdcas (output) note 5 (output) we (output) a11 (output) note 4 (output) bank address (output) undefined undefined undefined undefined undefined undefined undefined notes 1. state (t0) inserted between bys cycles 2. idle state (ti) independent of the bcc register setting 3. always executes the all bank precharge command. 4. addresses other than bank address, a11, and a1 to a10 5. udqm, ldqm remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state. 3. n = 1, 3, 4, or 6 4. bnk.: bank address col.: column address
chapter 5 bus control function user?s manual u16397ej3v0ud 241 5.11 bus priority bus hold, instruction fetch, operand data accesses, dma cycles, and refresh cycles are executed in the external bus cycle. bus hold has the highest priority, followed by refresh cycle, dma cycle, operand data access, and instruction fetch. an instruction fetch may be inserted between the read access and write access in a read-modify-write access. table 5-3. bus priority priority external bus cycle bus master bus hold external device refresh cycle sdram controller dma cycle dma controller operand data access cpu high low instruction fetch cpu
chapter 5 bus control function user?s manual u16397ej3v0ud 242 5.12 boundary operation conditions 5.12.1 program space do not branch to the on-chip peripheral i/o area. if branc h is executed, undefined data is fetched, and data is not fetched from the external memory. 5.12.2 data space the v850e/ma3 has an address misalign function. with this function, data can be placed at all addresses, rega rdless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (1) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (2) word-length data access (a) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (b) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10.
user?s manual u16397ej3v0ud 243 chapter 6 memory ac cess control function 6.1 sram, external rom, external i/o interface 6.1.1 features ? sram is accessed in a minimum of 2 states. ? up to 7 states of programmable data waits can be inserted by setting the dwc0 and dwc1 registers (dma flyby transfer: fwc register). ? data wait can be controlled via wait pin input. ? up to 3 idle states can be inserted after a read/writ e cycle by setting the bcc register (dma flyby transfer: fic register). ? up to 3 address setup wait states can be inserted by setting the asc register. ? dma flyby transfer can be activated (sram external i/o, external i/o sram) ? supports separate bus mode/multiplexed bus mode.
chapter 6 memory access control function user?s manual u16397ej3v0ud 244 6.1.2 sram connection examples of connection to sram are shown below. figure 6-1. examples of connection to sram (in separate bus mode) (a) when data bus width is 8 bits v850e/ma3 a1 to a17 ad8 to ad15 csn rd uwr ad0 to ad7 lwr a0 to a16 i/o1 to i/o8 cs oe we a0 to a16 i/o1 to i/o8 cs oe we sram (128 kwords 8 bits) sram (128 kwords 8 bits) (b) when data bus width is 16 bits v850e/ma3 a1 to a18 ad0 to ad15 csn rd ube lbe wr a0 to a17 i/o1 to i/o16 cs oe hb lb we sram (256 kwords 16 bits) remark n = 0 to 7
chapter 6 memory access control function user?s manual u16397ej3v0ud 245 figure 6-2. examples of connection to sram (in multiplexed bus mode) (a) when data bus width is 8 bits v850e/ma3 a16 to a19 ad0 to ad15 astb a1 to a15 a0 to a18 d0 to d7 rd wr cs a0 to a18 d0 to d7 rd wr cs rd uwr lwr sram (512 kwords 8 bits) sram (512 kwords 8 bits) csn d ce q (b) when data bus width is 16 bits v850e/ma3 a16 to a20 ad0 to ad15 astb a1 to a15 wr a0 to a19 i/o1 to i/o16 oe we cs ub lb rd csn ube sram (1 mword 16 bits) lbe d ce q remark n = 0 to 7
chapter 6 memory access control function user?s manual u16397ej3v0ud 246 6.1.3 sram, external rom, external i/o access (1) timing in separate bus mode figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (1/12) (a) read (successive 32-bit access) data t1 t2 tw busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t2 address a t0 note t1 t2 t1 t2 tw t0 note t2/ti/t0 note without data wait insertion with data wait insertion data data data address b address b + 2 address a + 2 note state (t0) insert ed between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 247 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (2/12) (b) read (successive 16-bit access) data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t2 t1 t2 tw t2/ti/t0 note address a address b t0 note t0 note without data wait insertion with data wait insertion note state (t0) insert ed between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 248 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (3/12) (c) read (32-bit access, address setup wait, idle state inserted) data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t2 tasw ti t2/ti note1 /t0 note 2 address a t0 note 2 data t1 t2 tasw ti address a+2 notes 1. if the chip select signal is not the same, the id le state may not be inserted, depending on the setting. 2. state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 249 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (4/12) (d) read (16-bit access, address setup wait, idle state inserted) data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t2 tasw ti t2/ti note 1 /t0 note 2 address t0 note 2 notes 1. if the chip select signal is not the same, the id le state may not be inserted, depending on the setting. 2. state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 250 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (5/12) (e) write (32-bit access (1/2)) wr (output) busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (output) wait (input) data address a cpu access data address b data address a+2 data address b+2 t1 t2 t1 t2/ti/t0 note t2 tw t1/t0 note t0 note t1 t2 t1 tw t2 32-bit write to address (b) 32-bit write to address (a) without data wait insertion with data wait insertion note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 251 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (6/12) (e) write (32-bit access (2/2)) t1 t2 t1 t2 tw t2/ti/t0 note cpu access 32-bit write to address (a) 32-bit write to address (b) data wr (output) busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (output) wait (input) data address a address b+2 t1/t0 note data address a+2 t1 t2 tw data address b t1 t2 without data wait insertion with data wait insertion note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 252 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (7/12) (f) write (16-bit access (1/2)) wr (output) busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (output) wait (input) data t1 t2 t1 t2/ti/t0 note address a cpu access 16-bit write to address (a) 16-bit write to address (b) data t2 tw address b t1/t0 note t0 note without data wait insertion with data wait insertion note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 253 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (8/12) (f) write (16-bit access (2/2)) data wr (output) busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (output) wait (input) data t1 t2 t1 t2 tw t2/ti/t0 note address a address b cpu access 16-bit write to address (a) 16-bit write to address (b) t1/t0 note without data wait insertion with data wait insertion note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 254 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (9/12) (g) write (16-bit access, address setup wait, idle state inserted) data wr (output) busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (output) wait (input) t1 t2 tasw ti t2/ti note 1 /t0 note 2 address t1/t0 note 2 notes 1. if the chip select signal is not the same, the id le state may not be inserted, depending on the setting. 2. state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 255 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (10/12) (h) read write (16-bit read access 16-bit write access) data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t2 t1 t2 t2/ti/t0 note address address t0 note wr (output) t1/t0 note note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 256 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (11/12) (i) write read (16-bit write access 16-bit read access (1/2)) data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t2 t1 t2 t2/ti/t0 note address a address b t0 note wr (output) cpu access write to address (a) read from address (b) t0 note note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 257 figure 6-3. sram, external rom, external i/o access timing (in separate bus mode) (12/12) (i) write read (16-bit write access 16-bit read access (2/2)) data data busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t2 t0 note t2 t2/ti/t0 note address a address b wr (output) cpu access write to address (a) read from address (b) t0 note note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 258 (2) timing in multiplexed bus mode figure 6-4. sram, external rom access timing (in multiplexed bus mode) (1/5) (a) read (32-bit access) data address a+2 busclk (output) a16 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t3 t1 t2 tah ti/t3/t0 note address a address a+2 ti/t0 note t2 astb (output) address a t3 tw data note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 259 figure 6-4. sram, external rom access timing (in multiplexed bus mode) (2/5) (b) read (successive 16-bit access) data address b busclk (output) a16 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t3 t1 t2 tah ti/t3/t0 note address a address b ti/t0 note t2 astb (output) address a t3 tw data t0 note with address hold wait, data wait insertion without address hold wait, data wait insertion note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 260 figure 6-4. sram, external rom access timing (in multiplexed bus mode) (3/5) (c) read (address setup wait, idle state inserted) data busclk (output) a16 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) rd (output) t1 t3 ti/t0 note address ti t2 astb (output) address tasw ti/t0 note note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 261 figure 6-4. sram, external rom access timing (in multiplexed bus mode) (4/5) (d) write (successive 16-bit access) data address b busclk (output) a16 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) wr (output) t1 t3 t1 t2 tah ti/t3/t0 note address a address b t1/ti/t0 note t2 astb (output) address a t3 tw data without address hold wait, data wait insertion with address hold wait, data wait insertion note state (t0) inse rted between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 262 figure 6-4. sram, external rom access timing (in multiplexed bus mode) (5/5) (e) write (16-bit access, address setup wait, idle state inserted) data busclk (output) a16 to a25 (output) cs0 to cs7 (output) bcyst (output) ube, lbe (output) ad0 to ad15 (input) wait (input) wr (output) t1 t3 ti/t0 note ti t2 astb (output) address tasw t0 note address note state (t0) insert ed between bus cycles remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 263 6.2 page rom controller (romc) the page rom controller (romc) is provided for a ccessing rom (page rom) with a page access function. 6.2.1 features ? direct connection to 8-bit/16-bit page rom supported ? page rom is accessed in a minimum of 2 states. ? on-page judgment function ? up to 7 states of programmable data waits c an be inserted by setting the following registers. during on-page cycle: prc register during off-page cycle: dwc0 and dwc1 registers during dma flyby cycle: fwc register ? waits can be controlled via wait pin input. ? dma flyby cycle can be activated (page rom external i/o) ? sram write cycle is started when a write cycle request is issued to a csn space (n = 0 to 7) where page rom is located
chapter 6 memory access control function user?s manual u16397ej3v0ud 264 6.2.2 page rom connection examples of connection to page rom are shown below. figure 6-5. examples of connection to page rom (a) when data bus width is 8 bits v850e/ma3 a1 to a21 ad8 to ad15 csn rd ad0 to ad7 a0 to a20 o0 to o7 ce oe a0 to a20 o0 to o7 ce oe page rom (2 mwords 8 bits) page rom (2 mwords 8 bits) (b) when data bus width is 16 bits v850e/ma3 a1 to a20 ad0 to ad15 csn rd a0 to a19 o0 to o15 ce oe page rom (1 mword 16 bits) remark n = 0 to 7
chapter 6 memory access control function user?s manual u16397ej3v0ud 265 6.2.3 on-page on-page access in the page rom cycle is generated in the following conditions. ? 8-bit bus width halfword access 16-bit access from even address boundary [off-page on-page] ? 8-bit bus width word access 32-bit access from word boundary [off-page on-page on-page on-page] 32-bit access from halfword boundary [off-page on-page off-page on-page] 32-bit access from odd address [off-page off-page on-page off-page] ? 16-bit bus width word access 32-bit access from word boundary [off-page on-page] 6.2.4 page rom configuration register (prc) this register sets the wait state in the on-page cycle and sets t he number of waits corres ponding to the connected page rom on-page access time, as we ll as to the system clock. this register can be read or written in 16-bit units. reset input sets this register to 7000h. caution write to the prc register after reset, and th en do not change the set values. also, do not access an external memory area until the initial setting of the prc register is complete. however, it is possible to access external memory areas w hose initialization se ttings are complete. 0 0 prc prw2 0 prw1 0 prw0 0 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 7000h r/w address: fffff49ah prw2 prw1 0 1 2 3 4 5 6 7 specification of number of waits corresponding to system clock during on-page access prw0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 cautions 1. for off-page access, the wait s set by dwc0 and dwc1 registers are inserted. 2. be sure to clear bits 15 and 11 to 0 to ?0?. the operation cannot be guaranteed if these bits are set to 1.
chapter 6 memory access control function user?s manual u16397ej3v0ud 266 6.2.5 page rom access figure 6-6. page rom access timing (1/3) (a) read (address setup wait, idle state inserted, 16-bit bus width halfword access) t0 note 1 tasw t1 t0 note 1 ti t2 tasw t1 t0 note 1 ti t2 tasw t1 t0 note 1 ti t2 tasw t1 t0 note 1 ti t2 off-page address data h busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) wr (output) ad0 to ad15 (input) wait (input) rd (output) note 2 (output) off-page address off-page address off-page address data data data notes 1. state (t0) insert ed between bus cycles. 2. ube, lbe remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 267 figure 6-6. page rom access timing (2/3) (b) read (address setup wait, idle stat e inserted, 16-bit bus width word access) t0 note 1 t1 tasw t2 to1 to2 ti t0 note 1 t0 note 1 t1 tasw t2 to1 to2 ti data on-page h busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) wr (output) ad0 to ad15 (input) wait (input) rd (output) note 2 (output) data data data address a address a + 2 address b address b + 2 on-page off-page off-page notes 1. state (t0) insert ed between bus cycles. 2. ube, lbe remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 268 figure 6-6. page rom access timing (3/3) (c) read (address setup wait, idle st ate inserted, data wait inserted, on-page data wait inserted, 16-bit bus width word access) t0 note 1 t0 note 1 tasw t1 tw tw tw t2 to1 ti to2 tow address a + 2 data h busclk (output) a0 to a25 (output) cs0 to cs7 (output) bcyst (output) wr (output) ad0 to ad15 (input) wait (input) rd (output) note 2 (output) on-page off-page data address a + 2 notes 1. state (t0) insert ed between bus cycles. 2. ube, lbe remarks 1. the circles indicate the sampling timing. 2. the broken lines indicate the high-impedance state.
chapter 6 memory access control function user?s manual u16397ej3v0ud 269 6.3 dram controller (sdram) 6.3.1 features ? burst length: 1 ? wrap type: sequential ? cas latency: 1, 2, and 3 supported ? 4 types of sdram can be assigned to 4 memory blocks. ? row and column address multiplex widths can be changed. ? waits (0 to 3 waits) can be inserted between t he bank active command and the read/write command. ? supports cbr (automatic) refresh and self-refresh. 6.3.2 sdram connection an example of connection to sdram is shown below. figure 6-7. example of connection to sdram v850e/ma3 a1 to a12 a22, a23 note ad0 to ad15 sdclk sdcke csn sdras sdcas udqm ldqm we a0 to a11 a12, a13 dq0 to dq15 clk cke cs ras cas hdqm ldqm we sdram (2 mwords 16 bits 4 banks) note the address signals to be used differ depending on the sdram product. remark n = 1, 3, 4, 6
chapter 6 memory access control function user?s manual u16397ej3v0ud 270 6.3.3 address multiplex function the row address output in the sdram cycle is multiplexed as shown in figure 6-8 (a) (n = 1, 3, 4, 6) according to the value of the scrn.saw n0 and scrn.sawn1 bits. t he column address output in the sdram cycle is multiplexed as shown in figure 6-8 (b) (n = 1, 3, 4, 6) according to the value of the scrn.sson0 and scrn.sson1 bits. in figures 6-8 (a) and (b), a0 to a25 indicate the addresses output from the cpu, and a0 to a25 indicate the address pins of the v850e/ma3. figure 6-8. row address/co lumn address output (1/2) (a) row address output a14 a25 a13 a24 a12 a23 a2 a13 a3 a14 a4 a15 a5 a16 a6 a17 a7 a18 a8 a19 a9 a20 a10 a21 a11 a22 a15 a15 a16 a16 a17 a17 a25 to a18 a25 to a18 a1 a12 a0 a11 a17 a16 a25 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 to a18 a14 a13 a12 a11 a10 row address (sawn1, sawn0 bits = 11) address pin row address (sawn1, sawn0 bits = 10) a25 a24 a23 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a17 a25 to a18 a12 a11 a10 a9 a25 a24 a23 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a25 to a18 a12 a11 a10 a9 a8 row address (sawn1, sawn0 bits = 01) row address (sawn1, sawn0 bits = 00) remark n = 1, 3, 4, 6 (b) column address output (using all-bank precharge command) a14 a14 a13 a13 a12 a12 a2 a2 a3 a3 a4 a4 a5 a5 a6 a6 a7 a7 a8 a8 a9 a9 a10 1 a11 a11 a15 a15 a16 a16 a17 a17 a25 to a18 a25 to a18 a1 a1 a0 a0 a16 a15 a14 a4 a5 a6 a7 a8 a9 a10 1 a12 a13 a17 a25 to a18 a3 a2 a1 a0 column address (sson1, sson0 bits = 00) address pin column address (sson1, sson0 bits = 01) remark n = 1, 3, 4, 6 (c) column address output (usi ng register write command) a14 0 a13 0 a12 0 a2 0 a3 0 a4 lt m 0 a5 lt m 1 a6 ltm2 a7 0 a8 0 a9 0 a10 0 a11 0 a15 0 a16 0 a17 0 a25 to a18 0 a1 0 a0 0 000 0 0 lt m 0 lt m 1 ltm2 0 0 0 0 0 0 0 0 00 0 column address (sson1, sson0 bits = 00) address pin column address (sson1, sson0 bits = 01) remark n = 1, 3, 4, 6
chapter 6 memory access control function user?s manual u16397ej3v0ud 271 figure 6-8. row address/colu mn address output (2/2) (d) column address output (using read/write command) a14 a14 a13 a12 a12 a11 a2 a2 a3 a3 a4 a4 a5 a5 a6 a6 a7 a7 a8 a8 a9 a9 a10 0 a11 a10 a15 a15 a16 a16 a17 a17 a25 to a18 a25 to a18 a1 a1 a0 a0 a16 a15 a14 a4 a5 a6 a7 a8 a9 a10 0 a11 a12 a17 a25 to a18 a3 a2 a1 a0 column address (sson1, sson0 bits = 00) address pin column address (sson1, sson0 bits = 01) remark n = 1, 3, 4, 6
chapter 6 memory access control function user?s manual u16397ej3v0ud 272 (1) output of each address and connection of sdram the set contents of the scrn register, physical addr ess, address output from the v850e/ma3, and connection between the v850e/ma3 and sdram at each data bus width (8 bits or 16 bits) are described below. (a) at 8-bit data bus width an example of connecting 64 mb sdram (2 mwords 8 bits 4 banks) at 8-bit data bus width is shown below. ? set contents of scrn register sson1, sson0 bits = 00: data bus width = 8 bits rawn1, rawn0 bits = 01: row address width = 12 bits sawn1, sawn0 bits = 01: column address width = 9 bits ? physical address a22, a21: bank address a20 to a9: row address a8 to a0: column address ? address output from v850e/ma3 a22, a21: bank address a11 to a0: row address (12 bits), column address (9 bits) (a) row address, bank addres s output (with active command) address pin a0 a9 a1 a10 a2 a11 a3 a12 a4 a13 a5 a14 a6 a15 a7 a16 a8 a17 a9 a18 a10 a19 a11 a20 a12 a21 a13 a22 a14 a23 a15 a24 a16 a25 a17 a17 a18 a18 a19 a19 a20 a20 a21 a21 a22 a22 a23 a23 a24 a24 a25 a25 row address bank address (b) column address output (with read/write command) address pin a0 a0 a1 a1 a2 a2 a3 a3 a4 a4 a5 a5 a6 a6 a7 a7 a8 a8 a9 a9 a10 0 a11 a10 a12 a11 a13 a12 a14 a14 a15 a15 a16 a16 a17 a17 a18 a18 a19 a19 a20 a20 a21 a21 a22 a22 a23 a23 a24 a24 a25 a25 column address ? connection of v850e/ma3 and sdram a22, a21 (v850e/ma3) ba0 (a13), ba1 (a12) (sdram) a11 to a0 (v850e/ma3) a11 to a0 (sdram)
chapter 6 memory access control function user?s manual u16397ej3v0ud 273 (b) at 16-bit data bus width an example of connecting 512 mb sdram (8 mwords 16 bits 4 banks) at 16-bit data bus width is shown below. ? set contents of scrn register sson1, sson0 bits = 01: data bus width = 16 bits rawn1, rawn0 bits = 10: row address width = 13 bits sawn1, sawn0 bits = 10: column address width = 10 bits ? physical address a25, a24: bank address a23 to a11: row address a10 to a1: column address ? address output from v850e/ma3 a25, a24: bank address a13 to a1: row address (13 bits), column address (10 bits) (a) row address, bank addres s output (with active command) address pin a0 a10 a1 a11 a2 a12 a3 a13 a4 a14 a5 a15 a6 a16 a7 a17 a8 a18 a9 a19 a10 a20 a11 a21 a12 a22 a13 a23 a14 a24 a15 a25 a16 a16 a17 a17 a18 a18 a19 a19 a20 a20 a21 a21 a22 a22 a23 a23 a24 a24 a25 a25 row address bank address (b) column address output (with read/write command) address pin a0 a0 a1 a1 a2 a2 a3 a3 a4 a4 a5 a5 a6 a6 a7 a7 a8 a8 a9 a9 a10 a10 a11 0 a12 a11 a13 a12 a14 a14 a15 a15 a16 a16 a17 a17 a18 a18 a19 a19 a20 a20 a21 a21 a22 a22 a23 a23 a24 a24 a25 a25 column address ? connection of v850e/ma3 and sdram a25, a24 (v850e/ma3) ba0 (a14), ba1 (a13) (sdram) a13 to a1 (v850e/ma3) a12 to a0 (sdram)
chapter 6 memory access control function user?s manual u16397ej3v0ud 274 (2) bank address output the v850e/ma3 precharges a bank to access by usi ng a bank precharge command when a row address is output immediately after page change. after bank chang e, it precharges the bank previously accessed when a column address is output. therefore, a bank is pr echarged both when a row address is output and when a column address is output. to connect sdram with the contents described in 6.3.3 (1) (a) at 8-bit data bus width , always connect the pins (a22 and a21) of the v8 50e/ma3 that outputs bank addresses to the bank address pins (a13 and a12) of sdram. an example of address output by the bank precharge command when the page or bank is changed if sdram is connected with the contents described in 6.3.3 (1) (a) at 8-bit data bus width is shown below. (a) when page is changed (at 8-bit data bus width) when the page is changed, the precharge command outputs the physical addresses to be accessed (a20 and a18 to a9) to the a11 and a9 to a0 pins, and the bank addresses to be accessed (a22 and a21) to the a22 and a21 pins. address pin a0 a9 a1 a10 a2 a11 a3 a12 a4 a13 a5 a14 a6 a15 a7 a16 a8 a17 a9 a18 a10 0 a11 a20 a12 a21 a13 a22 a14 a23 a15 a24 a16 a25 a17 a17 a18 a18 a19 a19 a20 a20 a21 a21 a22 a22 a23 a23 a24 a24 a25 a25 row address bank address to be accessed (b) when bank is changed (at 8-bit data bus width) when the bank is changed, the bank precharge command outputs the physical addresses to be accessed (a8 to a0) to the a8 to a0 pins, and the bank addre sses previously accessed (a22 and a21) to the a22 and a21 pins. address pin a0 a0 a1 a1 a2 a2 a3 a3 a4 a4 a5 a5 a6 a6 a7 a7 a8 a8 a9 a9 a10 0 a11 a10 a12 a11 a13 a12 a14 a14 a15 a15 a16 a16 a17 a17 a18 a18 a19 a19 a20 a20 a21 a21 a22 a22 a23 a23 a24 a24 a25 a25 column address bank address previously accessed the bits that determine the prechar ge mode (a10: 8-bit data bus width, a11: 16-bit data bus width, a12: 32-bit data bus width) output a high level when the al l bank precharge command is executed, and a low level when any other command is executed for precharging.
chapter 6 memory access control function user?s manual u16397ej3v0ud 275 6.3.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) these registers specify the number of waits and the address multiplex width. the scrn register corresponds to csn (n = 1, 3, 4, 6). for example, to connect sdram to cs1, set the scr1 register. these registers can be read or written in 16-bit units. the wcfn bit is read-only. reset input sets these registers to 30c0h. cautions 1. an sdram read/write cycle is not genera ted prior to executing a register write operation. access sdram after reading the value of the s crn register and confirming that the wcfn bit is set to 1. 2. to write to the scrn register again fo llowing access to sdram, clear the bct0.men and bct1.men bits to 0, and then set it to 1 agai n before performing access (n = 1, 3, 4, 6). 3. do not execute instructions to write to the scrn register c ontinuously. be sure to insert another instruction between commands to write to the scrn register. 4. start accessing sdram after all the scrn re gisters have been set. set the rfsn register before setting the scrn register (n = 1, 3, 4, 6). (1/2) 0 bcwn1 scrn (n = 1, 3, 4, 6) ltmn2 bcwn0 ltmn1 sson1 ltmn0 sson0 0 rawn1 0 rawn0 0 sawn1 wcfn sawn0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 30c0h r/w address: scr1 fffff4a4h, scr3 fffff4ach, scr4 fffff4b0h, scr6 fffff4b8h ltmn2 0 0 0 ltmn1 0 1 1 1 2 3 setting prohibited specification of cas latency value when reading ltmn0 1 0 1 bcwn1 0 0 1 1 bcwn0 0 1 0 1 setting prohibited 1 2 3 specification of number of wait states to be inserted setting not complete setting complete wcfn 0 1 register write command completion flag to sdram after scrn register setting set (1) when a register write command occurs. specify the number of wait states inserted from the bank active command to a read/write command, or from the precharge command to the bank active command. other than above caution be sure to clear bits 15, 11, 10, and 9 to ?0?. the operation cannot be guaranteed if these bits are set to 1. remark n = 1, 3, 4, 6
chapter 6 memory access control function user?s manual u16397ej3v0ud 276 (2/2) sson1 0 0 1 1 sson0 0 1 0 1 specification of address shift width during on-page judgment if the external data bus width is set to 16 bits, the system does not use the lower address (a0). set these bits in accordance with the contents of the lbs register corresponding to csn. rawn1 0 0 1 1 rawn0 0 1 0 1 specification of row address width sawn1 sawn0 specification of address multiplex width (column address width) during sdram access 0 bits (external data bus width: 8 bits) 1 bit (external data bus width: 16 bits) note setting prohibited setting prohibited 11 bits 12 bits 13 bits note setting prohibited 8 bits 9 bits 10 bits 11 bits note 0 0 1 1 0 1 0 1 note the following setting is prohibited because th e upper limit of the address is exceeded. sson1 sson0 rawn1 rawn0 sawn1 sawn0 setting 0 1 1 0 1 1 data bus width: 16 bits row address width: 13 bits column address width: 11 bits remark n = 1, 3, 4, 6
chapter 6 memory access control function user?s manual u16397ej3v0ud 277 6.3.5 sdram access during power-on or a refresh operation, the all-bank precharge command is always issued for sdram. when accessing sdram after that, therefore, the active command and read/write command are issued in that order (see <1> in figure 6-9 ). if a page change occurs following this, the prechar ge command, active command, and read/write command are issued in that order (see <2> in figure 6-9 ). if a bank change occurs, the active command and read/write command for the bank to be accessed next are issued in that order. following this read/write comma nd, the precharge command for the bank that was accessed before the bank currently being accessed will be issued (see <3> in figure 6-9 ). figure 6-9. state transition of sdram access <1> <3> <2> all-bank precharge command (power on/refresh) bank a active command bank a precharge command bank a active command bank a active command bank b active command bank b read/write command bank a read/write command bank a read/write command read/write command read/write command (on-page access) (page change) (bank change) (bank change) bank a precharge command
chapter 6 memory access control function user?s manual u16397ej3v0ud 278 (1) sdram single read cycle the sdram single read cycle is a cycle for reading from s dram by executing a load instruction (ld) for the sdram area, by fetching an instruction, or by 2-cycle dma transfer. in the sdram single read cycle, the active command (act) and read command (rd) are issued to sdram in that order. during on-page access, however, only the read command is issued and the precharge command and active command are not issued. when a page change occurs in the same bank, the precharge command (pre) is issued before the active command. a one-state t0 cycle is always inserted immediately before all read commands activated by the cpu. the number of idle states (ti) set by the bcc register are inserted after the read cycle (no idle states are inserted, however, if the bcc.bcn1 and bcc.bcn0 bits ar e 00) (n = 1, 3, 4, 6). the following shows the sdram single read cycle timing. caution when executing a write ac cess to sram or external i/o a fter read accessing sdram, data conflict may occur depending on the sdram data output float delay time. in such a case, avoid data conflict by inserting an idle stat e in the sdram space via a setting in the bcc register.
chapter 6 memory access control function user?s manual u16397ej3v0ud 279 figure 6-10. sdram single read cycle (1/5) (a) off-page access (latency = 2, bcw = 1, 16-bit bus width halfword access) t0 note 1 t0 note 1 tact rd row col. undefined data bcw = 1 latency = 2 row address h bnk.a act(bnk.a) tread tlate tlate sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) address undefined undefined undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 280 figure 6-10. sdram single read cycle (2/5) (b) off-page access (latency = 2, bcw = 2, two idle state inserted, 16-bit bus width halfword access) t0 note 1 ti ti t0 note 1 tact tread tbcw tlate tlate rd row row col. h bnk.a bnk.a act(bnk.a) bcw = 2 data latency = 2 sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) address undefined undefined undefined undefined undefined undefined undefined undefined address notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 281 figure 6-10. sdram single read cycle (3/5) (c) off-page access (latency = 2, page cha nge, bcw = 1, 16-bit bus width halfword access) bcw = 1 bcw = 1 bcw = 1 page change t0 note 1 t0 note 1 tact tread tlate tlate t0 note 1 tact tread tlate tlate tprec rd rd row row col. row row col. bnk.a bnk.a act(bnk.a) pre(bnk.a) act(bnk.a) data latency = 2 sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) undefined address latency = 2 data address address address undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 282 figure 6-10. sdram single read cycle (4/5) (d) off-page access (latency = 2, bank cha nge, bcw = 1, 16-bit bus width halfword access) bcw = 1 bcw = 1 t0 note 1 t0 note 1 tact tact tread tlate tlate t0 note 1 tread tlate tlate rd row row row col. row col. bnk.b bnk.a bnk.a act(bnk.a) rd act(bnk.b) pre(bnk.a) bank change data latency = 2 sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) address latency = 2 data address undefined undefined undefined undefined undefined undefined undefined undefined undefined address address undefined undefined undefined undefined undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 283 figure 6-10. sdram single read cycle (5/5) (e) on-page access (latency = 2, 16-bit bus width halfword access) t0 note 1 t0 note 1 tread tlate tlate rd col. bnk.a h h sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) latency = 2 data address undefined undefined undefined undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 284 (2) sdram single write cycle the sdram single write cycle is a cycle for writing to sdram by executing a write instruction (st) for the sdram area or by 2-cycle dma transfer. in the sdram single write cycle, the active command (act) and write command (wr) are issued to sdram in that order. during on-page access, however, only the write command is issued and the precharge command and active command are not issued. when a page change occurs in the same bank, the precharge command (pre) is issued before the active command. the following shows the sdra m single write cycle timing.
chapter 6 memory access control function user?s manual u16397ej3v0ud 285 figure 6-11. sdram single write cycle (1/6) (a) off-page access (bcw = 1, 16-bit bus width halfword access) bcw = 1 t0 note 1 tact twr wr row row col. bnk.a act(bnk.a) sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) data address address notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 286 figure 6-11. sdram single write cycle (2/6) (b) off-page access (bcw = 1, page chan ge, 16-bit bus width halfword access) (1/2) bcw = 1 page change bcw = 1 bcw = 1 t0 note 1 tact twr tact twr tw tprec wr wr row row row col. row col. undefined bnk.a bnk.a act(bnk.a) act(bnk.a) pre(bnk.a) write to address (1) write to address (2) sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) data address cpu access data address address address undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 287 figure 6-11. sdram single write cycle (3/6) (b) off-page access (bcw = 1, page chan ge, 16-bit bus width halfword access) (2/2) bcw = 1 bcw = 1 bcw = 1 t0 note 1 t0 note 1 tact twr tact twr tprec wr wr row row col. row row col. bnk.a bnk.a act(bnk.a) act(bnk.a) pre(bnk.a) page change undefined write to address (1) write to address (2) sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) data cpu access data address address undefined undefined undefined undefined undefined address address notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 288 figure 6-11. sdram single write cycle (4/6) (c) off-page access (bcw = 1, bank chan ge, 16-bit bus width halfword access) (1/2) bcw = 1 bcw = 1 t0 note 1 tact twr wpre wend tact twr tw wr row row col. row row col. bnk.a bnk.a bnk.b act(bnk.a) wr act(bnk.b) pre(bnk.a) bank change write to address (1) write to address (2) sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) cpu access data undefined address data undefined undefined undefined undefined undefined address undefined undefined undefined undefined address address notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 289 figure 6-11. sdram single write cycle (5/6) (c) off-page access (bcw = 1, bank chan ge, 16-bit bus width halfword access) (2/2) bcw = 1 bcw = 1 t0 note 1 t0 note 1 tact twr wpre wend tact twr wr row row col. row row col. bnk.a bnk.a bnk.b act(bnk.a) wr act(bnk.b) pre(bnk.a) bank change write to address (1) write to address (2) sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) cpu access data address data undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined address address address notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 290 figure 6-11. sdram single write cycle (6/6) (d) on-page access (16-bit bus width halfword access) (1/2) t0 note 1 twr wr col. bnk.a h sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) data address notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 291 (3) sdram access timing control the sdram access timing can be controlled by the scrn register (n = 1, 3, 4, 6). for details, see 6.3.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) . caution wait control by the wait pi n is not available during sdram access. (a) number of waits from bank active command to read/write command the number of wait states from bank active command issuance to read/write command issuance can be set by setting the scrn.bcwn1 and scrn.bcwn0 bits. bcwn1, bcwn0 bits = 01: 1 wait bcwn1, bcwn0 bits = 10: 2 waits bcwn1, bcwn0 bits = 11: 3 waits (b) number of waits from precharge command to bank active command the number of wait states from precharge command issuance to bank active command issuance can be set by setting the scrn.bcwn1 and scrn.bcwn0 bits. bcwn1, bcwn0 bits = 01: 1 wait bcwn1, bcwn0 bits = 10: 2 waits bcwn1, bcwn0 bits = 11: 3 waits (c) cas latency setting when read the cas latency during a read operation can be set by setting the scrn.ltmn2 to scrn.ltmn0 bits. ltmn2 to ltmn0 bits = 001: latency = 1 ltmn2 to ltmn0 bits = 010: latency = 2 ltmn2 to ltmn0 bits = 011: latency = 3 (d) number of waits from refresh command to next command the number of wait states from refresh command is suance to next command issuance can be set by setting the scrn.bcwn1 and scrn.bcwn0 bits. the num ber of wait states becomes four times the value set by bcwn1 and bcwn0 bits. bcwn1, bcwn0 bits = 01: 4 waits bcwn1, bcwn0 bits = 10: 8 waits bcwn1, bcwn0 bits = 11: 12 waits
chapter 6 memory access control function user?s manual u16397ej3v0ud 292 figure 6-12. sdram access timing (1/6) (a) read (on-page page change, 16-bit bus width wo rd access, bcw = 2, latency = 2) page change bcw = 2 bcw = 2 latency = 2 t0 note 1 t0 note 1 t0 note 1 tact tprec tbcw tbcw tread tread tread tread tlate tlate tlate tlate rd rd rd rd row row col. col. col. col. undefined bnk.a bnk.a bnk.a bnk.a act(bnk.a) pre(bnk.a) sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) data address data data data latency = 2 latency = 2 latency = 2 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined address address address address notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 293 figure 6-12. sdram access timing (2/6) (b) read (on-page bank change, 16-bit bus width wo rd access, bcw = 2, latency = 2) bcw = 2 t0 note 1 t0 note 1 t0 note 1 tact tbcw tread tread tread tread tlate tlate tlate tlate rd rd rd rd row row col. col. col. col. bnk.a bnk.a bnk.b bnk.b act(bnk.b) pre(bnk.a) bank change latency = 2 sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) data data data data latency = 2 latency = 2 latency = 2 undefined undefined address undefined undefined undefined undefined undefined undefined address address address undefined undefined undefined undefined undefined undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 294 figure 6-12. sdram access timing (3/6) (c) read write (on-page page change, 16-bit bus width wo rd access, bcw = 2, latency = 2) bcw = 2 bcw = 2 t0 note 1 t0 note 1 t0 note 1 tact tprec tbcw tbcw tread twr tread tlate tlate twr rd rd wr wr row row col. col. col. col. bnk.a bnk.a bnk.a bnk.a act(bnk.a) pre(bnk.a) page change sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) data data data data latency = 2 latency = 2 undefined undefined address address undefined undefined undefined undefined undefined undefined undefined undefined address address notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 295 figure 6-12. sdram access timing (4/6) (d) write read (bank change, 16-bit bus width word access, bcw = 2, latency = 2) bcw = 2 bcw = 2 t0 note 1 t0 note 1 tact tact tbcw tbcw twr twr tw tread tread tlate tlate wr rd rd wr row row row row col. col. col. col. bnk.a bnk.a bnk.a bnk.b bnk.b act(bnk.a) act(bnk.b) pre(bnk.a) bank change sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 4 (output) note 5 (output) bcyst note 3 (output) command a11 (output) data data data data latency = 2 latency = 2 undefined address undefined undefined undefined undefined undefined address address address address undefined undefined undefined undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. glitch may occur if bcyst out puts low levels successively. 4. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 5. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address row: row address
chapter 6 memory access control function user?s manual u16397ej3v0ud 296 figure 6-12. sdram access timing (5/6) (e) read (on-page successive access, 16 -bit bus width word access, latency = 2) t0 note 1 t0 note 1 t0 note 1 tread tread tread tread tlate tlate tlate tlate t0 note 1 tread tread tlate tlate rd rd rd rd rd rd col. col. col. col. col. col. bnk.a bnk.a bnk.a h h sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) command a11 (output) data data latency = 2 latency = 2 address undefined data data latency = 2 latency = 2 data data latency = 2 latency = 2 undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined address address address address address undefined undefined undefined undefined undefined undefined undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address
chapter 6 memory access control function user?s manual u16397ej3v0ud 297 figure 6-12. sdram access timing (6/6) (f) write (on-page successive access, 16-bit bus width word access) t0 note 1 tw tw tw twr twr tw tw twr twr tw tw twr twr twr twr wr wr wr wr wr wr wr wr col. col. col. col. col. col. col. col. bnk.a bnk.a bnk.a bnk.a h sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 2 (output) note 4 (output) note 5 (output) bcyst note 3 (output) command a11 (output) data data data data data data undefined data data address address address address address address address address undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined notes 1. state (t0) insert ed between bus cycles 2. addresses other than bank address, a1 to a10, and a11 3. glitch may occur if bcyst out puts low levels successively. 4. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 5. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l 3. bnk.: bank address col.: column address
chapter 6 memory access control function user?s manual u16397ej3v0ud 298 6.3.6 refresh control function the v850e/ma3 can generate a refresh cycle. the refr esh cycle is set by the rfs1, rfs3, rfs4, and rfs6 registers. the rfsn register corresponds to csn (n = 1, 3, 4, 6). for example, to connect sdram to cs1, set the rfs1 register. when another bus master occupies the external bus, the dram controller cannot occupy the external bus. in this case, the dram controller issues a refresh request to the bus master by changing the refrq signal to active (low level). during a refresh operation, the address bus retains t he state it was in just before the refresh cycle. (1) sdram refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) these registers are used to enable or disable a refresh and set the refresh interval. the refresh interval is determined by the following calculation formula. refresh interval ( s) = refresh count clock (t rcy ) interval factor the refresh count clock and interval factor are determined by the rfsn.rcc n1 and rfsn.rccn0 bits and rfsn.rin5n to rfsn.rin0n bits, respectively. note that n corresponds to the register number (1, 3, 4, 6) of the scr1, scr3, scr4, and scr6 registers. these registers can be read or written in 16-bit units. reset input clears these registers to 0000h. cautions 1. write the rfsn register after reset a nd do not change its value after that. however, the set value of the rfsn register can be cha nged only if it is necessary to change the refresh interval of sdram as a result of ch anging the set value of the ckc register or pcc register (internal system clock (f clk )). do not access the external memory area until the initial setting of the rfsn register is completed. 2. change the setting of the rfsn register in the following procedure (n = 1, 3, 4, or 6). <1> clear the bctm.men bit to 0 (m = 0 or 1, n = 1, 3, 4, or 6). <2> clear the rfsn.renn bit to 0. <3> change the clock cycle. <4> set the men bit to 1. <5> set a new refresh interval to the rf sn register. clear the renn bit to 0. <6> write a value same as that currently set to the scrn register to the scrn register. <7> confirm that the scrn.wcfn bit is set to 1 and then set the renn bit to 1. write a value set in <5> above to the bi ts other than the renn bit. <8> sdram can now be accessed. for how to change the clock cycle, see 7. 3 (1) processor clock control register (pcc) and 7.3 (2) clock control register (ckc). 3. to change the refresh inte rval, consider and set a value at which refreshing can be performed in time even while the refresh interval is changed. for details, see 6.3.6 (1) (a) notes on changing refresh interval.
chapter 6 memory access control function user?s manual u16397ej3v0ud 299 renn 0 rfsn (n = 1, 3, 4, 6) 0 0 0 rinn5 0 rinn4 0 rinn3 0 rinn2 rccn1 rinn1 rccn0 rinn0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 after reset: 0000h r/w address: rfs1 fffff4a6h, rfs3 fffff4aeh, rfs4 fffff4b2h, rfs6 fffff4bah rinn5 0 0 1 1 rinn4 0 0 1 1 1 2 63 64 interval factor ... ... ... ... ... ... ... rinn3 0 0 1 1 rinn2 0 0 1 1 refresh disabled refresh enabled renn 0 1 cbr (automatic) refresh enable rccn1 0 0 1 1 rccn0 0 1 0 1 32/busclk 128/busclk 256/busclk setting prohibited specification of refresh count clock (t rcy ) rinn1 0 0 1 1 rinn0 0 1 0 1 sets the interval factor of the interval timer for the generation of the refresh timing using the rinn5 to rinn0 bits. table 6-1. example of interval factor settings interval factor value notes 1, 2 specified refresh interval value ( s) refresh count clock (t rcy ) busclk = 30 mhz busclk = 40 mhz busclk = 50 mhz 32/busclk 14 (14.9) 19 (15.2) 24 (15.4) 128/busclk 3 (12.8) 4 (12.8) 6 (15.4) 15.6 256/busclk 1 (8.5) 2 (12.8) 3 (15.4) 32/busclk 7 (7.5) 9 (7.2) 12 (7.7) 128/busclk 1 (4.3) 2 (6.4) 3 (7.7) 7.8 256/busclk ? 1 (6.4) 1 (5.1) notes 1. the interval factor is set by the rfsn.r inn0 to rfsn.rinn5 bits (n = 1, 3, 4, 6). 2. the values in parentheses are the calc ulated values for the refresh interval ( s). refresh interval ( s) = refresh count clock (t rcy ) interval factor the v850e/ma3 can automatically generate a cbr (automatic) refres h cycle and a self-refresh cycle.
chapter 6 memory access control function user?s manual u16397ej3v0ud 300 (a) notes on changing refresh interval figure 6-13 shows the internal status and external bus status while the refresh interval is changed when sdram is connected to cs1 and cs3. in this case, sdram connected to cs1 is not refreshed during periods <1>, <3>, and <4>, and sdram connected to cs3 is not refreshed during periods <1>, <2>, and <4>. periods <1> and <4> may extend or shorten depending on the status of the internal system bus or on a factor such as a bus hold request from the exter nal bus. periods <2> and <3> changes depending on the set value of the rfsn register. to change the refresh interval, therefore, periods <1> to <4> in figure 6-13 during which sdram is not refreshed must be taken into consideration and a value to set to the rfsn register must be determined. even when sdram is connected only to one cs area, the refresh interval value must be changed, taking periods <1> to <4> in figure 6-13 into consideration. cautions 1. the refresh command is issued eight times in the register write cycle, regardless of the set value of the renn bit (n = 1, 3, 4, 6). 2. while the renn bit is 0, the refrq signal does not operate. this should be noted when the external bus master references the refrq signal. 3. while the bctm.men bit is 0 (n = 1, 3 when m = 0, n = 4, 6 when m = 1), the self refresh status is not set even when th e idle or software stop mode is set. figure 6-13. internal status and external bu s status when refresh interval is changed (if sdram is connected to cs1 and cs3) refresh enable (internal signal) external bus cycle (1) (3) (2) (4) (5) (8) (6)-1 (6)-2 (7)-1 (7)-2 cs1 register write cycle cs3 register write cycle <1> <2> <3> <4> (1) clear the bct0.me1 and bct3.me3 bits to 0. (2) clear the rfs1.ren1 and rfs3.ren3 bits to 0. (3) change the clock cycle. (4) set the me1 and me3 bits to 1. (5) set a new refresh interval to the rfs1 and rfs3 regist ers. however, clear the ren1 and ren3 bits to 0. (6)-1 write a value same as that currently set to the scr1 register to the scr1 register. (6)-2 write a value same as that currently set to the scr3 register to the scr3 register. (7)-1 confirm that the scr1.wcf1 and scr3.wcf3 bits are set to 1. (7)-2 set the ren1 and ren3 bits to 1. write a value se t in (5) to the bits other than the ren1 and ren3 bits. (8) sdram can be accessed. (2) cbr (automatic) refresh cycle in the cbr (automatic) refresh cycle, the auto-refr esh command (ref) is issued four clocks after the precharge command for all banks (pall) is issued.
chapter 6 memory access control function user?s manual u16397ej3v0ud 301 figure 6-14. cbr (automatic) refr esh cycle (16-bit bus width) cbr (automatic) refresh cycle tabpw trefw trefw trefw tref pall ref h h h h sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) ad0 to ad15 (i/o) we (output) sdras (output) note 1 (output) note 3 (output) note 4 (output) bcyst note 2 (output) command a11 (output) undefined sdcke (output) undefined undefined undefined notes 1. addresses other than bank address, a1 to a10, and a11 2. glitch may be generated if bcyst outputs high levels in the cb r (automatic) refresh cycle. 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l
chapter 6 memory access control function user?s manual u16397ej3v0ud 302 6.3.7 self-refresh control function in the case of transition to the idle or software stop mode, the dram controller gener ates the self-refresh cycle. caution the internal rom and internal ram can be accessed even in the self-refr esh cycle. however, access to an on-chip peripheral i/o register or external device is held pending until the self- refresh cycle is released. to release the self-refresh cycle, us e one of the three methods below. (1) release by nmi input (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the sdr as and sdcas signals inactive immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the s dras and sdcas signals inactive after stabilizing oscillation. (2) release by intp0n input (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137) (a) in the case of self-refresh cycle in idle mode to release the self-refresh cycle, make the sdr as and sdcas signals inactive immediately. (b) in the case of self-refresh cycle in software stop mode to release the self-refresh cycle, make the s dras and sdcas signals inactive after stabilizing oscillation. (3) release by reset input
chapter 6 memory access control function user?s manual u16397ej3v0ud 303 figure 6-15. self timing (16-bit bus width) all bank precharge command refresh command self-refresh mode bcw 4clk nop command trpw tref trpw trpw trpw trpw trpw trpw trpw trpw trpw tabpw trefw trefw trefw trefw trefw trefw trefw trefw trefw t0 note 1 h h h sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) we (output) sdras (output) note 2 (output) note 3 (output) note 4 (output) bcyst (output) a11 (output) sdcke (output) nop command undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined notes 1. state (t0) inserted between bys cycles 2. addresses other than bank address, a1 to a10, and a11 3. in xwr output mode/xdqm output mode (pfcct.pfcctm bit = 0) 4. in xbe output mode/xdqm output mode (pfcct.pfcctm bit = 1) remarks 1. wait states of ?bcw 4 clk = number of wait states set by scrn.bcwn1 and scrn.bcwn0 bits 4 clk? is inserted. 2. n = 1, 3, 4, or 6, m = 0 or 1, x = u or l
chapter 6 memory access control function user?s manual u16397ej3v0ud 304 6.3.8 sdram initialization sequence be sure to initialize sdram when applying power. initialize sdram in the following procedure. (1) set the registers of sdram (other than sdram co nfiguration register n (scrn), sdram refresh control register n (rfsn)). ? bus cycle type configuration r egisters 0, 1 (bct0, bct1) ? bus cycle control register (bcc) (2) set other than renn bit of sdram refresh control regist ers 1, 3, 4, 6 (rfs1, rfs3 , rfs4, rfs6). clear the renn bit to 0. (3) set sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6). when writing data to the scrn register, the following commands are iss ued for sdram in the order shown below. ? all-bank precharge command ? refresh command (8 times) ? command that is used to set a mode register (4) after confirming that all the sdram initialization is complete using the scrn.wcfn bit, set the rfsn.ren bit to 1. set the value set in step (2) to other bits than the renn bit. caution if it is necessary to ma ke the input levels of the udqm and ld qm pins high until initialization of sdram is complete, do not change the set values of the pfcct1 a nd pfcct0 bits of the pfcct register and do not write to the exter nal device until initialization of sdram is complete. an example of timing of a sdram regist er write operation is shown below.
chapter 6 memory access control function user?s manual u16397ej3v0ud 305 figure 6-16. sdram register write op eration timing (16-bit bus width) scrn register write all bank precharge command refresh command (1st) refresh (1st) end refresh (8th) end refresh command (2nd) register write command sdram access enable refresh 7 tw0 tw0 tw0 tw0 tref tregw trpw trpw trpw tabpw trefw trefw trefw trefw trefw trefw trefw tref trefw trefw trefw pall ref regwr h h h valid sdclk (output) a1 to a10 (output) csn (output) bank address (output) sdcas (output) we (output) sdras (output) note 1 (output) note 3 (output) bcyst note 2 (output) a11 (output) sdcke (output) command refresh interval 1/2 notes 1. addresses other than bank address, a1 to a10, and a11 2. glitch may be generated if bcyst outputs high levels in the s dram initialization sequence. 3. udqm, ldqm remark n = 1, 3, 4, or 6
user?s manual u16397ej3v0ud 306 chapter 7 clock generator 7.1 overview the features of clock generator are as follows. { oscillator ? f x = 4 to 8 mhz (in pll mode) ? f x = 5 to 25 mhz (in clock-through mode) { multiply ( 1.25/2.5/5/10) function by pll (phase locked loop) ? clock-through mode/pll mode selectable { internal system clock generation ? 4 steps (f xx , f xx /2, f xx /4, f xx /8) { peripheral clock generation { oscillation stabilization time selection remark f x : oscillation frequency f xx : system clock 7.2 configuration figure 7-1. clock generator mfrc bit ck1, ck0 bits ckdiv1, ckdiv0 bits software stop mode prescaler 1 oscillation stabilization time contro l prescaler 2 idle control halt control halt mode cpu clock peripheral clock watchdog timer clock oscillation stabilization time internal system clock oscillator stop control x1 x2 idle mode selector selector pll f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /32,768 f x /2 14 , f x /2 16 f xx f x f xw 1/2 psel cksel remark f x : oscillation frequency f xx : system clock frequency f cpu : cpu clock frequency f clk : internal system clock frequency f xw : watchdog timer clock frequency
chapter 7 clock generator user?s manual u16397ej3v0ud 307 (1) oscillator the main resonator oscillates the following frequencies (f x ): ? f x = 4 to 8 mhz (in pll mode) ? f x = 5 to 25 mhz (in clock-through mode) (2) stop control this circuit generates a control signal that stops oscillation of the oscillator. oscillation of the oscillator is stopped in the software stop mode. (3) idle control a control signal that stops clock supply to the intern al circuits other than the oscillator is generated. in the idle mode, clock supply to the internal circuits other than the oscillator is stopped. (4) halt control only the cpu clock (f cpu ) is stopped. (5) pll this circuit multiplies the clock (f x ) generated by the oscillator by 1.25, 2.5, 5, or 10. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be selected by the cksel pin input. change the setting of the psel pi n according to the frequency band. (6) prescaler 1 this prescaler generates the clock (f xx to f xx /32,768) to be supplied to the following on-chip peripheral functions: tmp0 to tmp2, tmq0, tm d0 to tmd3, tmenc10, uarta0 to uarta3, csib0 to csib2, i 2 c, adc, and dac. (7) prescaler 2 this circuit divides the system clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /8) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom correction, rom, and ram blocks. (8) oscillation stabilization time control the time until oscillation is stabilized after the softwar e stop mode has been released by an interrupt request signal is counted. the count clock can be selected from 2 14 /f x and 2 16 /f x .
chapter 7 clock generator user?s manual u16397ej3v0ud 308 7.3 control registers the clock generator is controlled by following five registers. ? processor clock control register (pcc) ? clock control register (ckc) ? power save control register (psc) ? power save mode register (psmr) ? oscillation stabilization time select register (osts) (1) processor clock control register (pcc) the pcc register is a special register. data can be wr itten to this register only in combination of specific sequences (see 3.4.9 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 pcc 0 mfrc 0 0 0 ck1 ck0 7 6 <5> 4 3 2 1 0 used (resonator is connected to x1, x2 pins) not used (external clock is connected to x1 pin) mfrc 0 1 use of main clock on-chip feedback resistor after reset: 00h r/w address: fffff828h f xx f xx /2 f xx /4 f xx /8 clock selection (f clk /f cpu ) ck1 0 0 1 1 ck0 0 1 0 1 cautions 1. be sure to clear bi ts 2 to 4, 6, and 7 to ?0?. 2. after the ck1 and ck0 bits have been set, the clock is switched within 10 cpu clocks (f cpu ).
chapter 7 clock generator user?s manual u16397ej3v0ud 309 (2) clock control register (ckc) the ckc register is an 8-bit register that controls the system clock (f xx ) in pll mode. it can be written to only in a specific sequence combination so that it cannot easily be overwritte n by mistake due to an inadvertent program loop. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution do not change the ckdiv1 a nd ckdiv0 bits in clock-through mode. 0 1.25 f x 2.5 f x 5 f x 10 f x ckdiv1 0 0 1 1 system clock (f xx ) ckc 0 0 0 0 0 ckdiv1 ckdiv0 ckdiv0 0 1 0 1 after reset: 00h r/w address: fffff822h cautions 1. the system clock fre quency switches in 10 system clocks (f xx ) after the ckdiv1 and ckdiv0 bits are set. 2. be sure to clear bits 2 to 7 to ?0?. remark f x : oscillation frequency example clock generator settings ckc register operation mode cksel pin ckdiv0 bit ckdiv0 bit input clock (f x ) system clock (f xx ) clock-through mode high-level input 25 mhz 25 mhz 0 0 8 mhz 10 mhz 0 1 8 mhz 20 mhz 1 0 8 mhz 40 mhz pll mode low-level input 1 1 8 mhz 80 mhz remark : don?t care
chapter 7 clock generator user?s manual u16397ej3v0ud 310 (3) power save control register (psc) the psc register is a special register. data can be wri tten to this register only in a combination of specific sequences (see 3.4.9 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 psc 0 nmim intm 0 0 stb 0 standby mode release enabled by nmi request standby mode release disabled by nmi request nmim 0 1 control of non-maskable interrupt request (nmi) from nmi pin note 1 standby mode release enabled by intxx request standby mode release disabled by intxx request intm 0 1 control of all maskable interrupt requests note 1 (intxx note 2 ) normal mode standby mode stb 0 1 setting operation mode note 3 after reset: 00h r/w after reset: fffff1feh < > < > < > notes 1. setting these bits is valid only in the idle/software stop mode. 2. for details, see tables 20-1 interrupt source list . 3. for the setting procedure, see 21.7 procedure for setting a nd restoring from idle and software stop modes . cautions 1. be sure to clear bi ts 0, 2, 3, 6, and 7 to ?0?. 2. to set the idle mode or software stop m ode, set the psmr.psm bit first and then set the stb bit to 1.
chapter 7 clock generator user?s manual u16397ej3v0ud 311 (4) power save mode register (psmr) the psmr register is an 8-bit register that controls th e operation status in the power save mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 idle mode software stop mode psm 0 1 specification of operation in software standby mode psmr 0 0 0 0 0 0 psm after reset: 00h r/w after reset: fffff820h < > cautions 1. be sure to cl ear bits 1 to 7 to ?0?. 2. the psm bit is valid only when the psc.stb bit is 1.
chapter 7 clock generator user?s manual u16397ej3v0ud 312 (5) oscillation stabilization time select register (osts) the osts register selects the oscillation stabilization time until the oscillation stabilizes after the software stop mode is released by an interrupt request signal. this register can be read/written in 8-bit units. reset input sets this register to 01h. 0 osts 0 0 0 0 0 0 osts0 2 14 /f x 2 16 /f x selection of oscillation stabilization time osts0 0 1 2.731 ms 10.923 ms 2.048 ms 8.192 ms f x after reset: 01h r/w address: fffff6c0h 8 mhz 6 mhz cautions 1. the wait time does not include the time until the clock oscillation st arts (?a? in the figure below) following release of the software stop mode. a software stop mode release voltage waveform of x1 pin v ss 2. set the osts register to 01h when using an oscillator. 3. be sure to clear bits 1 to 7 to ?0?. 4. when the software stop mode is rele ased by reset pin input, the oscillation stabilization time does not elapse. secure th e oscillation stabilization time by the low- level width of the reset pin input. remark f x : oscillation frequency
chapter 7 clock generator user?s manual u16397ej3v0ud 313 7.4 operation 7.4.1 operation of each clock the following table shows the oper ation status of each clock. table 7-1. each clock operation status clock source power save mode oscillator (f x ) pll internal system clock (f clk ) peripheral clock (f xx to f xx /32,768) cpu clock (f cpu ) watchdog timer clock (f xw ) normal operation halt mode idle mode software stop mode oscillation stabilization period oscillation with resonator reset period normal operation halt mode idle mode software stop mode oscillation stabilization period pll mode external clock reset period normal operation halt mode idle mode software stop mode oscillation stabilization period clock- through mode external clock reset period note note note note note the clock is supplied during the reset period but the operations of the cpu and all the peripheral functions are stopped. remark : operating : stopped 7.4.2 external cloc k input function an external clock can be directly input to the oscillator. in this case, input the clock signal only to the x1 pin (leave the x2 pin open). set the mfrc bit of the pcc register to 1 (to cut the feedback resistor). note, however, that oscillation stabilization time is inserted even in the external clock mode.
chapter 7 clock generator user?s manual u16397ej3v0ud 314 7.5 pll function 7.5.1 overview the cpu and the operating clock of the on-chip periphe ral function can be switched between output of the oscillation frequency multiplied by 1.25, 2.5, 5, or 10, and clock-through mode. when pll function is used: input clock = 4 to 8 mhz (f xx : 5 to 80 mhz) clock-through mode: input clock = 5 to 25 mhz (f xx : 5 to 25 mhz) 7.5.2 selecting system clock in the v850e/ma3, the system clock is selected according to the input levels of the cksel and psel pins, and the setting of the ckc register. the following system cl ocks can be selected. table 7-2. selecting system clock ckc register cksel psel internal clock selection input clock frequency (f x ) ckdiv1 ckdiv0 system clock frequency (f xx ) 0 0 5 to 6.875 mhz 0 1 10 to 13.75 mhz 1 0 20 to 27.5 mhz l l low-frequency mode 4.0 to 5.5 mhz 1 1 40 to 55 mhz 0 0 6.875 to 10 mhz 0 1 13.75 to 20 mhz 1 0 27.5 to 40 mhz l h pll mode high-frequency mode 5.5 to 8.0 mhz 1 1 55 to 80 mhz h clock-through mode 5.0 to 25.0 mhz 5 to 25 mhz caution fix the input levels of the cksel and psel pins during the reset peri od and do not change the levels during operation. otherwise, th e operation will not be guaranteed. remark : don?t care
chapter 7 clock generator user?s manual u16397ej3v0ud 315 7.5.3 pll mode in the pll mode, the oscillation frequency (f x ) is multiplied by the pll to generate a system clock (f xx ). f xx can be selected from f x multiplied by 1.25, 2.5, 5, or 10, according to the setting of the clock control register (ckc). fix the input level of the psel pin to the high or low le vel according to the value of the oscillation frequency (f x ). in the pll mode, the clock is input from the oscillator to the pll. a clock at a stable frequency must be supplied to the internal circuit after the lapse of the lockup time (f requency stabilization time) during which the phase is locked at a specific frequency and oscillation is stabi lized. the v850e/ma3 automatically secures the following lockup time after release of reset. lockup time = 2 14 /f x + = approx. 2.048 ms (f x = 8 mhz) to approx. 4.096 ms (f x = 4 mhz) 7.5.4 clock-through mode in the clock-through mode, a system clock (f xx ) of the same frequency as the oscillation frequency (f x ) is generated. the v850e/ma3 requires the following time until the cpu starts operation after release of reset. cpu operation start time = 2 16 /f x + = approx. 2.62144 ms (f x = 25 mhz) to approx. 13.1072 ms (f x = 5 mhz)
user?s manual u16397ej3v0ud 316 chapter 8 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850e/ma3 has three timer/event counter channels, tmp0 to tmp2. 8.1 overview an outline of tmpn is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? timer output pins: 2 remark n = 0 to 2 8.2 functions tmpn has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement ? timer tuning operation function (tmp2 only) remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 317 8.3 configuration tmpn includes the following hardware. table 8-1. configuration of tmpn item configuration timer register 16-bit counter registers tmpn capture/compare registers 0, 1 (tpnccr0, tpnccr1) tmpn counter read buffer register (tpncnt) ccr0 and ccr1 buffer registers timer input total 12 (intpp00, intpp01, intpp10, intpp11, intpp20, intpp21, evtp0 to evtp2, tip0 to tip2 pins) note timer output total 6 (top00, top01, top10, top11, top20, top21 pins) note control registers tmpn control registers 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option register 0 (tpnopt0) note intppn0/evtpn/tipn pin functions alternately as a capture trigger input pin (intppn0), external event count input pin (evtpn), external trigger input pin (tipn), and timer output pin (topn0). intppn1 pin functions alternately as a capture trigger input pin (intppn1) and timer output pin (topn1). remark n = 0 to 2 figure 8-1. tmpn block diagram selector edge detector selector f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 internal bus internal bus tpncnt tpnccr0 ccr1 buffer register tpnccr1 intppn1 intppn0/evtpn/tipn 16-bit counter ccr0 buffer register clear intovpn output controller intccpn0 topn0 topn1 intccpn1 remarks 1. n = 0 to 2 2. f xx : peripheral clock
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 318 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tpncnt register. when the tpnctl0.tpnce bit = 0, the va lue of the 16-bit counter is ffffh. if the tpncnt register is read at this time, 0000h is read. reset input clears the tpnce bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr0 register is used as a compare regist er, the value written to the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (intccpn0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, and the tpnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr1 register is used as a compare regist er, the value written to the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (intccpn1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, and the tpnccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the intppn0/evtpn/tipn and intppn1 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tpnioc1 and tpnioc2 registers. (5) output controller this circuit controls the output of the topn0 and topn 1 pins. the output contro ller is controlled by the tpnioc0 registers. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 319 8.4 registers (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tpnctl0 register by software. tpnce tmpn operation disabled (tmpn reset asynchronously note ) tmpn operation enabled. tmpn operation start tpnce 0 1 tmpn operation control tpnctl0 (n = 0 to 2) 0 0 0 0 tpncks2 tpncks1 tpncks0 654321 after reset: 00h r/w address: tp0ctl0 fffff640h, tp1ctl0 fffff660h, tp2ctl0 fffff680h <7> 0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 tpncks2 0 0 0 0 1 1 1 1 internal count clock selection tpncks1 0 0 1 1 0 0 1 1 tpncks0 0 1 0 1 0 1 0 1 note tpnopt0.tpnovf bit and 16-bit count er are reset simultaneously. moreover, timer outputs (topn0 and topn1 pins) are reset to the tpnioc0 register set status at the same time as the 16-bit counter. cautions 1. set the tpncks2 to tpncks0 bits when the tpnce bit = 0. when the value of the tpnce bit is changed from 0 to 1, the tpncks 2 to tpncks0 bits can be set simultaneously. 2. be sure to set bits 3 to 6 to ?0?. remark f xx : peripheral clock
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 320 (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit regist er that controls the tmpn operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. (1/2) tp2sye note tpnctl1 tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 654321 after reset: 00h r/w address: tp0ctl1 fffff641h, tp1ctl1 fffff661h, tp2ctl1 fffff681h tmp2 single mode tuning operation mode (see 12.4.5 ) tp2sye note 0 1 operation mode selection tmp2 can be used only as an a/d conversion start trigger factor of an a/d converter during the tuning operation. in the tuning operation mode, this bit always operates in synchronization with tmq0. 7 0 (n = 0 to 2) tpnest 0 1 software trigger control generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tpnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tpnest bit as the trigger. disable operation with external event count input (evtpn pin). (perform counting with the count clock selected by the tpnctl0.tpncks0 to tpnctl0.tpncks2 bits.) tpneee 0 1 count clock selection the tpneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. enable operation with external event count input (evtpn pin). (perform counting at the valid edge of the external event count input signal (evtpn pin).) ? the read value of the tpnest bit is always 0. note this bit can only be set in tmp2. be sure to clear bit 7 of tmp0 and tmp1 to 0. for details of tuning operation mode, see chapter 12 motor control function .
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 321 (2/2) interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tpnmd2 0 0 0 0 1 1 1 1 timer mode selection tpnmd1 0 0 1 1 0 0 1 1 tpnmd0 0 1 0 1 0 1 0 1 cautions 1. the tpnest bit is valid only in the external trigger pulse output mode or one-shot pulse output mode. in any other mode, wr iting 1 to this bit is ignored. 2. external event count input is selected in th e external event count mode regardless of the value of the tpneee bit. 3. set the tp2sye, tpneee, and tpnmd2 to tp nmd0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnc e bit = 1.) the operation is not guaranteed when rewriting is performed with the tpnce bit = 1. if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 4. be sure to set bits 3 and 4 to ?0?.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 322 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register that controls the timer output (topn0, topn1 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnol1 0 1 topn1 pin output level setting note topn1 pin starts output at high level. topn1 pin starts output at low level. tpnioc0 0 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 6543<2>1 after reset: 00h r/w address: tp0ioc0 fffff642h, tp1ioc0 fffff662h tp2ioc0 fffff682h tpnoe1 0 1 topn1 pin output setting timer output prohibited ? low level is output from the topn1 pin when the tpnol1 bit = 0. ? high level is output from the topn1 pin when the tpnol1 bit = 1. timer output enabled (a pulse is output from the topn1 pin.) tpnol0 0 1 topn0 pin output level setting note topn0 pin starts output at high level. topn0 pin starts output at low level. tpnoe0 0 1 topn0 pin output setting timer output prohibited ? low level is output from the topn0 pin when the tpnol0 bit = 0. ? high level is output from the topn0 pin when the tpnol0 bit = 1. timer output enabled (a pulse is output from the topn0 pin.) 7 <0> (n = 0 to 2) note the output level of the timer output pins (topn0 and topn1) specified by the tpnola bit is shown below (a = 0, 1). tpnce bit topn0 and topn1 output pins 16-bit counter ? when tpnola bit = 0 tpnce bit topn0 and topn1 output pins 16-bit counter ? when tpnola bit = 1 cautions 1. if the setting of the tpnioc0 register is changed when topn0 and topn1 are set in the output mode, the output of the pins change. set the port in the input mode and make the port go into a high-impedance state, noting changes in the pin status. 2. rewrite the tpnol1, tpnoe1, tpnol0, and tp noe0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnc e bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 3. even if the tpnol0 or tpnol1 bit is ma nipulated when the tpnce, tpnoe0, and tpnoe1 bits are 0, the output level of th e topn0 and topn1 pins changes.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 323 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit re gister that controls the valid edge for the capture trigger input signals (intppn0, intppn1 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnis3 0 0 1 1 tpnis2 0 1 0 1 capture trigger input signal (intppn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tpnioc1 (n = 0 to 2) 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 654321 after reset: 00h r/w address: tp0ioc1 fffff643h, tp1ioc1 fffff663h, tp2ioc1 fffff683h tpnis1 0 0 1 1 tpnis0 0 1 0 1 capture trigger input signal (intppn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnis3 to tpnis0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tp nce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid onl y in the free-running timer mode (only when the tpnopt0.tpnccs1 and tpnopt0. tpnccs0 bits = 11) and the pulse width measurement mode. in all other modes, a cap ture operation is not possible.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 324 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit regist er that controls the valid edge for the external event count input signal (evtpn pin) and external trigger input signal (tipn pin). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnees1 0 0 1 1 tpnees0 0 1 0 1 external event count input signal (evtpn pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tpnioc2 (n = 0 to 2) 0 0 0 tpnees1 tpnees0 tpnets1 tpnets0 654321 after reset: 00h r/w address: tp0ioc2 fffff644h, tp1ioc2 fffff664h, tp2ioc2 fffff684h tpnets1 0 0 1 1 tpnets0 0 1 0 1 external trigger input signal (tipn pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnees1, tpnees0, tpnets1, and tpnets0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when th e tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are valid only when the tpnctl1.tpneee bit = 1 or when the external event count mode (the tpnctl1 .tpnmd2 to tpnctl1.tpnmd0 bits = 001) has been set. 3. the tpnets1 and tpnets0 bits are valid on ly in the external trigger pulse mode or one- shot pulse output mode.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 325 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit register that sets the capture/compare operat ion and detects overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnccs1 0 1 tpnccr1 register capture/compare selection the tpnccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by tpnctl0.tpnce bit = 0) tpnopt0 (n = 0 to 2) 0 tpnccs1 tpnccs0 0 0 0 tpnovf 654321 after reset: 00h r/w address: tp0opt0 fffff645h, tp1opt0 fffff665h, tp2opt0 fffff685h tpnccs0 0 1 tpnccr0 register capture/compare selection the tpnccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by tpnctl0.tpnce bit = 0) tpnovf set (1) reset (0) tmpn overflow flag ? the tpnovf bit is set to 1 when the 16-bit counter value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an overflow interrupt request signal (intovpn) is generated at the same time that the tpnovf bit is set to 1. the intovpn signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tpnovf bit is not cleared to 0 even when the tpnovf bit or the tpnopt0 register are read when the tpnovf bit = 1. ? before clearing the tpnovf bit to 0 after generation of the intovpn signal, be sure to confirm (by reading) that the tpnovf bit is set to 1. ? the tpnovf bit can be both read and written, but the tpnovf bit cannot be set to 1 by software. writing 1 has no effect on the operation of tmpn. overflow occurred 0 written to tpnovf bit or tpnctl0.tpnce bit = 0 7 <0> cautions 1. rewrite the tpnccs1 and tpnccs0 bits when the tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriti ng was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. be sure to set bits 1 to 3, 6, and 7 to ?0?.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 326 (7) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register is a 16-bit r egister that can be used as a captur e register or compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs0 bit. in the pulse width measurement mode, the tpnccr0 register can be used only as a capture register. in any other mode, this register can be used only as a compare register. the tpnccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tpnccr0 (n = 0 to 2) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr0 fffff646h, tp1ccr0 fffff666h, tp2ccr0 fffff686h 14 0 13 11 9 7 5 3 15 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 327 (a) function as compare register the tpnccr0 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (intccpn0) is generated. if topn0 pi n output is enabled at this time , the output of the topn0 pin is inverted. when the tpnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. the compare register is not cleared by setting the tpnctl0.tpnce bit to 0. (b) function as capture register when the tpnccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr0 regist er if the valid edge of the capture trigger input pin (intppn0 pin) is detected. in the pulse-width measurement mode, t he count value of the 16-bit counter is stored in the tpnccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (intppn0) is detected. even if the capture operation and reading the tp nccr0 register conflict, the correct value of the tpnccr0 register can be read. the capture register is cleared by setting the tpnctl0.tpnce bit to 0. remark n = 0 to 2 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tpnccr1 register is the trigger. remark for anytime write and batch write, see 8.6 (2) anytime write and batch write .
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 328 (8) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is a 16-bit r egister that can be used as a captur e register or compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs1 bit. in the pulse width measurement mode, the tpnccr1 register can be used only as a capture register. in any other mode, this register can be used only as a compare register. the tpnccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tpnccr1 (n = 0 to 2) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr1 fffff648h, tp1ccr1 fffff668h, tp2ccr1 fffff688h 14 0 13 11 9 7 5 3 15 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 329 (a) function as compare register the tpnccr1 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (intccpn1) is generated. if topn1 pi n output is enabled at this time , the output of the topn1 pin is inverted. the compare register is not cleared by setting the tpnctl0.tpnce bit to 0. (b) function as capture register when the tpnccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr1 regist er if the valid edge of the capture trigger input pin (intppn1 pin) is detected. in the pulse-width measurement mode, t he count value of the 16-bit counter is stored in the tpnccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (intpp n1 pin) is detected. even if the capture operation and reading the tp nccr1 register conflict, the correct value of the tpnccr1 register can be read. the capture register is cleared by setting the tpnctl0.tpnce bit to 0. remark n = 0 to 2 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 8-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tpnccr1 register is the trigger. remark for anytime write and batch write, see 8.6 (2) anytime write and batch write .
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 330 (9) tmpn counter read bu ffer register (tpncnt) the tpncnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tpnctl0.tpnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tpncnt register is cleared to 0000h when the tpnce bit = 0. if t he tpncnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tpncnt register is cleared to 000 0h after reset, and the tpnce bit is cleared to 0. tpncnt (n = 0 to 2) 12 10 8 6 4 2 after reset: 0000h r address: tp0cnt fffff64ah, tp1cnt fffff66ah, tp2cnt fffff68ah 14 0 13 11 9 7 5 3 15 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 331 8.5 timer output operations the following table shows the operations and out put levels of the topn0 and topn1 pins. table 8-4. timer output control in each mode operation mode topn1 pin topn0 pin interval timer mode pwm output external event count mode none external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output pwm output free-running timer mode pwm output (only when compare function is used) pulse width measurement mode none remark n = 0 to 2 table 8-5. truth table of topn0 and topn1 pins under control of timer output control bits tpnioc0.tpnola bit tpnioc0.tpnoea bit tpnctl0.tpnce bit level of topna pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 332 8.6 operation the functions of tmpn are shown below. operation tpnctl1.tpnest bit (software trigger bit) tipn pin (external trigger input) capture/compare register setting compare register write method interval timer mode invalid invalid compare only anytime write external event count mode invalid invalid compare only anytime write external trigger pulse output mode note valid valid compare only batch write one-shot pulse output mode note valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switchable anytime write pulse width measurement mode note invalid invalid capture only not applicable note when using the external trigger pulse output m ode, one-shot pulse output mode, and pulse width measurement mode, select the internal clock as the count clock (by clearing the tpnctl1.tpneee bit to 0). remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 333 (1) counter basic operation this section explains the basic oper ation of the 16-bit counter. for details, refer to the description of the operation in each mode. remark n = 0 to 3 (a) counter start operation the 16-bit counter of tmpn starts countin g from the default value ffffh in all modes. it counts up from ffffh to 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its value matches the value of the compare register and is cleared, and when its value is c aptured and cleared. the counting op eration from ffffh to 0000h that takes place immediately after the counter has start ed counting or when the counter overflows is not a clearing operation. therefore, the intccpn0 and intccpn1 interrupt signals are not generated. (c) overflow operation the 16-bit counter overflows when the counter counts up from ffffh to 0000h in the free-running mode or pulse width measurement mode. if the counter overflows, the tpnopt0.tpnovf bit is set to 1 and an interrupt request signal (intovpn) is generated. note that the intovpn signal is not generated under the following conditions. ? immediately after a counti ng operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured and cleare d in the pulse width measuremen t mode and the counter counts up from ffffh to 0000h caution after the overflow interrupt request signa l (intovpn) has been generated, be sure to check that the overflow flag (tpnovf bit) is set to 1. (d) counter read operation during counting operation the value of the 16-bit counter of tmpn can be read by using the tpncnt register during the count operation. when the tpnctl0.tpnce bit = 1, the val ue of the 16-bit counter can be read by reading the tpncnt register. when the tpnctl0.tpnce bit = 0, the 16-bit counter is ffffh and the tpncnt register is 0000h. (e) interrupt operation tmpn generates the following three types of interrupt request signals. ? intccpn0 interrupt: this signal functions as a match interrupt request signal of the ccr0 buffer register and as a capture interrupt request signal to the tpnccr0 register. ? intccpn1 interrupt: this signal functions as a match interrupt request signal of the ccr1 buffer register and as a capture interrupt request signal to the tpnccr1 register. ? intovpn interrupt: this signal functions as an overflow interrupt request signal.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 334 (2) anytime write and batch write the tpnccr0 and tpnccr1 registers in tmpn can be rewritten during timer operation (tpnctl0.tpnce bit = 1), but the write method (anytime write, batch wr ite) of the ccr0 and ccr1 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the tpnccr0 and tpnccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. (n = 0 to 2). figure 8-2. flowchart of basic operation for anytime write start initial settings ? set values to tpnccra register ? timer operation enable (tpnce bit = 1) transfer values of tpnccra register to ccra buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start intccpn1 signal output tpnccra register rewrite transfer to ccra buffer register intccpn0 signal output note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 335 figure 8-3. timing of anytime write d 01 d 01 d 01 d 01 0000h tpnce bit = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter tpnccr0 register tpnccr1 register intccpn0 signal intccpn1 signal ccr0 buffer register ccr1 buffer register 0000h ffffh remarks 1. d 01 , d 02 : setting values of tpnccr0 register d 11 , d 12 : setting values of tpnccr1 register 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 336 (b) batch write in this mode, data is transferred all at once from the tpnccr0 and tpnccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the tpnccr1 register. whether to enable or disable the next transfer timing is controlled by writing or not writing to the tpnccr1 register. in order for the setting value when the tpnccr0 and tpnccr1 registers are rewritten to become the 16- bit counter comparison value (in other words, in order for this value to be transferred to the ccr0 and ccr1 buffer registers), it is necessary to rewrite the tpnccr0 register and then write to the tpnccr1 register before the 16-bit counter value and the ccr0 buff er register value match. therefore, the values of the tpnccr0 and tpnccr1 registers are transferred to the ccr0 and ccr1 buffer registers upon a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. thus even when wishing only to rewrite the value of the tpn ccr0 register, also write the same value (same as preset value of the tpnccr1 regi ster) to the tpnccr1 register.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 337 figure 8-4. flowchart of basic operation for batch write start initial settings ? set values to tpnccra register ? timer operation enable (tpnce bit = 1) transfer values of tpnccra register to ccra buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of tpnccra register to ccra buffer register intccpn1 signal output tpnccr0 register rewrite tpnccr1 register rewrite intccpn0 signal output batch write enable note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. caution writing to the tpnccr1 regi ster includes enabling of batch wr ite. thus, rewrite the tpnccr1 register after rewriting the tpnccr0 register. remarks 1. the above flowchart illustrates an example of the operation in the pwm output mode. 2. n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 338 figure 8-5. timing of batch write d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 0000h d 11 tpnce bit = 1 note 1 d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter tpnccr0 register tpnccr1 register intccpn0 signal intccpn1 signal topn1 pin output topn0 pin output ccr0 buffer register ccr1 buffer register note 1 note 1 note 1 same value write d 02 d 12 0000h d 03 d 12 note 2 note 3 ffffh notes 1. because the tpnccr1 register was not rewritten, d 03 is not transferred. 2. because the tpnccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of th e 16-bit counter and the value of the tpnccr0 register (d 01 ). 3. because the tpnccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of th e 16-bit counter and the value of the tpnccr0 register (d 02 ). remarks 1. d 01 , d 02 , d 03 : setting values of tpnccr0 register d 11 , d 12 : setting values of tpnccr1 register 2. the above flowchart illustrates the operation in the pwm output mode as an example. 3. n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 339 8.6.1 interval timer mode (t pnmd2 to tpnmd0 bits = 000) in the interval timer mode, an interrupt request signal (intccpn0) is gene rated at the interval set by the tpnccr0 register if the tpnctl0.tpnce bit is set to 1. a pwm waveform with a duty factor of 50% whose half cycle is equal to the interval can be output from the topn0 pin. the tpnccr1 register is not used in the interval timer mo de. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register, and when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (intccpn1) is generated. in addition, a pwm waveform with a duty factor of 50%, which is inverted when the intccpn1 signal is generated, can be ou tput from the topn1 pin. the value of the tpnccr0 and tpnccr1 registers c an be rewritten even while the timer is operating. figure 8-6. configuration of interval timer 16-bit counter output controller ccr0 buffer register tpnce bit tpnccr0 register count clock selection clear match signal topn0 pin intccpn0 signal remark n = 0 to 2 figure 8-7. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output intccpn0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 340 when the tpnce bit is set to 1, the value of the 16-bit co unter is cleared from ffffh to 0000h in synchronization with the count clock, and the c ounter starts counting. at this time, t he output of the topn0 pin is inverted. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the to pn0 pin is inverted, and a compare match interrupt request signal (intccpn0) is generated. the interval can be calculated by the following expression. interval = (set value of tpnccr0 register + 1) count clock cycle remark n = 0 to 2 figure 8-8. register setting for in terval timer mode operation (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 note 00 tpnctl1 0, 0, 0: interval timer mode 000 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest tp2sye 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count with external event count input signal note the tpneee bit can be set to 1 only when timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 341 figure 8-8. register setting for in terval timer mode operation (2/2) (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level with operation of topn0 pin disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of output level with operation of topn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 note tpnioc2 select valid edge of external event count input (evtpn pin). 0/1 note 00 tpnees0 tpnets1 tpnets0 tpnees1 note the tpnees1 and tpnees0 bits can be set only when timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value. (e) tmpn counter read bu ffer register (tpncnt) by reading the tpncnt register, the count va lue of the 16-bit counter can be read. (f) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle (g) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is not used in the interval ti mer mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, the topn1 pi n output is inverted and a compare match interrupt request signal (intccpn1) is generated. by setting this register to the same value as the value set in the tpnccr0 register, a pwm waveform with a duty factor of 50% can be output from the topn1 pin. when the tp0ccr1 to top2ccr1 registers are not used, it is recommended to set their value to ffffh. also mask the register by the interr upt mask flag (p00ic1.p00mk1, p02ic2.p02mk2, p05ic1.p05mk1). remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the interval timer mode. 2. n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 342 (1) interval timer mode operation flow figure 8-9. software processing flow in interval timer mode tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register note , tpnccr0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. the output level of the topn0 pin is as specified by the tpnioc0 register. start stop <1> count operation start flow <2> count operation stop flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output intccpn0 signal note the tpnees1 and tpnees0 bits can be set only when timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value. remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 343 (2) interval timer mode operation timing (a) operation if tpnccr0 re gister is set to 0000h if the tpnccr0 register is set to 0000h, the intccpn0 signal is generated at each count clock, and the output of the topn0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tpnce bit tpnccr0 register topn0 pin output intccpn0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 344 (b) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing . the intccpn0 signal is generated and the output of the topn0 pin is inverted. at this time, an overfl ow interrupt request signal (intovpn) is not generated, nor is the overflow flag (tpnopt0.tpnovf bit) set to 1. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output intccpn0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 345 (c) notes on rewriting tpnccr0 register if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting and then change the set value. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register tpnol0 bit topn0 pin output intccpn0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remarks 1. interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle 2. n = 0 to 2 if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tpnccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the intccpn0 signal is generated and the output of the topn0 pin is inverted. therefore, the intccpn0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock cycle?.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 346 (d) operation of tpnccr1 register figure 8-10. configuration of tpnccr1 register ccr0 buffer register tpnccr0 register tpnccr1 register ccr1 buffer register topn0 pin intccpn0 signal topn1 pin intccpn1 signal 16-bit counter output controller tpnce bit count clock selection clear match signal output controller match signal remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 347 when the tpnccr1 register is set to the same value as the tpnccr0 register, the intccpn0 signal is generated at the same timing as the intccpn1 signal and the topn1 pin output is inverted. in other words, a pwm waveform with a duty factor of 50% can be output from the topn1 pin. the following shows the operation when the tpnccr1 register is set to other than the value set in the tpnccr0 register. if the set value of the tpnccr1 regist er is less than the set value of the tpnccr0 register, the intccpn1 signal is generated once per cycle. at the same time, the output of the topn1 pin is inverted. the topn1 pin outputs a pwm waveform with a duty fa ctor of 50% after outputting a short-width pulse. figure 8-11. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output intccpn0 signal tpnccr1 register topn1 pin output intccpn1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 348 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the count value of the 16-bit counter does not match the va lue of the tpnccr1 register. consequently, the intccpn1 signal is not generated, nor is the output of the topn1 pin changed. when the tpnccr1 register is not used, it is recommended to set it s value to ffffh. figure 8-12. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output intccpn0 signal tpnccr1 register topn1 pin output intccpn1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 349 (3) operation by external event count input (evtpn) (a) operation to count the 16-bit counter at the valid edge of exte rnal event count input (evtpn) in the interval timer mode, the valid edge of the external event count input is necessary once because the 16-bit counter is cleared from ffffh to 0000h immediately afte r the tpnce bit is set from 0 to 1. when 0001h is set to both the tpnccr0 and tpnccr1 registers, the topn1 pin output is inverted each time the 16-bit counter counts twice. the tpnctl1.tpneee bit can be set to 1 in the interval timer mode only when the timer output (topn1) is used with the external event count input. tpnce bit external event count input tpnccr0 register tpnccr1 register topn1 pin output 16-bit counter ffffh 0000h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h number of external events: 3 number of external events: 2 number of external events: 2 2-count width 2-count width 2-count width (evtpn pin input) remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 350 8.6.2 external event count mode (tpnmd2 to tpnmd0 bits = 001) in the external event count mode, the valid edge of the external event count input (evtpn) is counted when the tpnctl0.tpnce bit is set to 1, and an interrupt request signal (intccpn0) is generated each time the number of edges set by the tpnccr0 register have been counted. the topn0 and topn1 pins cannot be used. when using the topn1 pin for external event count input, set the tp nctl1.tpneee bit to 1 in the interval timer mode (see 8.6.1 (3) operation by external event count input (evtpn) ). the tpnccr1 register is not used in the external event count mode. caution in the external event count mode, the tpn ccr0 and tpnccr1 registers must not be cleared to 0000h. figure 8-13. configuration in external event count mode 16-bit counter ccr0 buffer register tpnce bit tpnccr0 register edge detector clear match signal intccpn0 signal evtpn pin (external event count input) remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 351 figure 8-14. basic timing in external event count mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal d 0 d 0 d 0 d 0 16-bit counter tpnccr0 register intccpn0 signal external event count input (evtpn pin input) d 0 external event count (d 0 ) note external event count (d 0 + 1) external event count (d 0 + 1) d 0 ? 1d 0 0000 0001 note in the external event count mode, when the tpnc tl0.tpnce bit is set to 1 (operation starts), the 16-bit counter is cleared from ffffh to 0000h at the same time. the first count operation starts from 0001h each time the valid edge of the external event count input is detected. therefore, the count of the fi rst count operation is one number smaller than the count of the second or subsequent count operation. caution this figure shows the basi c timing when the rising edge is specified as the valid edge of the external event count input. remark n = 0 to 2 when the tpnce bit is set to 1, the value of the 16-bi t counter is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detected. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (intccpn0) is generated. the intccpn0 signal is generated for the first time when the valid edge of t he external event count input has been detected ?value set to tpnccr0 register? times. after that, the intccpn0 signal is generated each time the valid edge of the external event count has been detected ?value set to tpnccr0 register + 1? times.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 352 figure 8-15. register setting for oper ation in external event count mode (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 0: stop counting 1: enable counting 000 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 00000 tpnctl1 0, 0, 1: external event count mode 001 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest tp2sye (c) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input (evtpn pin) 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (d) tmpn counter read bu ffer register (tpncnt) the count value of the 16-bit counter can be read by reading the tpncnt register. (e) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the count is cleared when the number of external events has reached (d 0 ) and the first compare match interrupt request signal (intccpn0) is generated. the second compare match interrupt request signal (int ccpn0) is generated when the number of external events has reached (d 0 + 1). (f) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is not used in the external event count mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buff er register. when the count value of the 16-bit counter matches the value of the ccr1 buffer regi ster, a compare match interrupt request signal (intccpn1) is generated. when the tp0ccr1 to tp2ccr1 registers are not us ed, it is recommended to set their value to ffffh. also mask the register by the interr upt mask flag (p00ic1.p00mk1, p02ic2.p02mk2, p05ic1.p05mk1). remarks 1. tmpn i/o control register 0 (tpnioc0), tmpn i/o control register 1 (tpnioc1), and tmpn option register 0 (tpnopt0) are not us ed in the external event count mode. 2. n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 353 (1) external event count mode operation flow figure 8-16. software processing flow in external event count mode tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl1 register, tpnioc2 register, tpnccr0, tpnccr1 registers initial setting of these registers is performed before setting the tpnce bit to 1. the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow d 0 d 0 d 0 d 0 <1> <2> ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 354 (2) operation timing in external event count mode cautions 1. in the external event count mode, the tpnccr0 and tpnccr1 registers must not be cleared to 0000h. 2. in the external event count mode, use of th e timer output (topn0, topn1) is disabled. if using timer output (topn1) with external event count input (evtpn), set the interval timer mode, and select the operation enabled by the external event count input for the count clock (tpnctl1.tpneee bit = 1) (see 8.6.1 (3) operation by external event count input (evtpn)). (a) operation if tpnccr0 register is set to ffffh if the tpnccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time the vali d edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the intccpn0 signal is generated. at this time, the tpnopt0.tpnovf bit is not set. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal ffffh external event count: ffffh external event count: 10000h external event count: 10000h remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 355 (b) notes on rewriting the tpnccr0 register if the value of the tpnccr0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when the overflow may occur, stop counting once and then change the set value. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count (1): (d 1 ) external event count (ng): (10000h + d 2 + 1) external event count (2): (d 2 + 1) remark n = 0 to 2 if the value of the tpnccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buffer register as soon as the tpnccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the intccpn0 signal is generated. therefore, the intccpn0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be ge nerated at the valid edge count of ?(10000h + d 2 + 1) times?.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 356 (c) operation of tpnccr1 register figure 8-17. configuration of tpnccr1 register ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal intccpn0 signal intccpn1 signal edge detector evtpn pin (external event count input) remark n = 0 to 2 if the set value of the tpnccr1 register is smalle r than the set value of the tpnccr0 register, the intccpn1 signal is gene rated once per cycle. figure 8-18. timing chart when d 01 d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal tpnccr1 register intccpn1 signal d 01 d 11 d 01 d 11 d 11 d 11 d 11 d 01 d 01 d 01 remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 357 if the set value of the tpnccr1 register is greater than the set value of the tpnccr0 register, the intccpn1 signal is not generated because the count value of the 16-bit counter and the value of the tpnccr1 register do not match. when the tpnccr1 register is not used, it is recommended to se t its value to ffffh. figure 8-19. timing chart when d 01 < d 11 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal tpnccr1 register intccpn1 signal d 01 d 11 d 01 d 01 d 01 d 01 l remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 358 8.6.3 external trigger pulse output m ode (tpnmd2 to tpnmd0 bits = 010) in the external trigger pulse output mode, 16-bit timer/event counter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an ex ternal trigger input (tipn) is detected, 16-bit timer/event counter p starts counting, and outputs a pwm waveform from the topn1 pin. pulses can also be output by generating a software trigger instead of using the external trigger. when using a software trigger, a pwm waveform with a duty factor of 50% that has the set value of the tpnccr0 register + 1 as half its cycle can also be out put from the topn0 pin. figure 8-20. configuration in external trigger pulse output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal intccpn0 signal output controller (rs-ff) output controller topn1 pin intccpn1 signal topn0 pin note count clock selection internal count clock count start control edge detector software trigger generation evtpn/tipn pin note (external event count input/external trigger input) edge detector transfer transfer s r note because the external event count input pin (evtpn), external trigger input pin (tipn), and timer output pin (topn0) are the same al ternate-function pin, two or mo re functions cannot be used at the same time. remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 359 figure 8-21. basic timing in exte rnal trigger pulse output mode d 1 d 0 d 0 d 1 d 1 d 1 d 1 d 0 d 0 d 0 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal tpnccr1 register intccpn1 signal topn1 pin output external trigger input (tipn pin input) topn0 pin output (only when software trigger is used) wait for trigger active level width (d 1 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 1 ) active level width (d 1 ) 16-bit timer/event counter p waits for a trigger when the tpnce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts counti ng at the same time, and outputs a pwm wave\form from the topn1 pin. if the trigger is generated again while the c ounter is operating, the counter is cleared to 0000h and restarted. (the output of t he topn0 pin is inverted. the topn1 pin ou tputs a high-level regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the compare match request signal intccpn0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and th e 16-bit counter is cleared to 0000h. the compare match interrupt request signal intccpn1 is generated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccra register is transferred to t he ccra buffer register when the count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input (tipn), or se tting the software tr igger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 2, a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 360 figure 8-22. setting of registers in exte rnal trigger pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting is invalid when the tpnctl1.tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) 0 0/1 0/1 0 0 tpnctl1 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count with external event count input signal generate software trigger when 1 is written 010 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 0: external trigger pulse output mode tp2sye (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output settings of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output settings of output level while operation of topn1 pin is disabled 0: low level 1: high level 0/1 0/1 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 note clear this bit to 0 when the topn0 pin is not used in the external trigger pulse output mode.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 361 figure 8-22. setting of registers in exte rnal trigger pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external trigger input (tipn pin) note select valid edge of external event count input (evtpn) note 0/1 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 note set the valid edge selection of the unused alternate external input signals to ?no edge detection?. (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the external trigger pulse output mode. 2. n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 362 (1) operation flow in extern al trigger pulse output mode figure 8-23. software processing flow in ex ternal trigger pulse output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register intccpn0 signal tpnccr1 register ccr1 buffer register intccpn1 signal topn1 pin output external trigger input (tipn pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 363 figure 8-23. software processing flow in ex ternal trigger pulse output mode (2/2) tpnce bit = 1 setting of tpnccr0 register register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting is enabled (tpnce bit = 1). trigger wait status. writing same value (same as preset value of the tpnccr1 register) to the tpnccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tpnccra register is transferred to the ccra buffer register. start setting of tpnccr1 register <1> count operation start flow <2> tpnccr0 and tpnccr1 register setting change flow setting of tpnccr0 register when the counter is cleared after setting, the value of the tpnccra register is transferred to the ccra buffer register. setting of tpnccr1 register <4> tpnccr0, tpnccr1 register setting change flow only writing of the tpnccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of the tpnccra register is transferred to the ccra buffer register. setting of tpnccr1 register <3> tpnccr0, tpnccr1 register setting change flow tpnce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 364 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccra register after writing the tpnc cr1 register after the intccpn0 signal is detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register intccpn0 signal tpnccr1 register ccr1 buffer register intccpn1 signal topn1 pin output external trigger input (tipn pin input) topn0 pin output (only when software trigger is used) d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 365 in order to transfer data from the tpnccra register to the ccra buffer register, the tpnccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tpnccr0 register and then set the active level width to the tpnccr1 register. to change only the cycle of the pwm waveform, first se t the cycle to the tpnccr0 register, and then write the same value (same as preset value of t he tpnccr1 register) to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the val ue written to the tpnccra register is transferred to the ccra buffer register in synchronization with clea ring of the 16-bit counter, and is used as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again after writing the tpnccr1 register once, do so after the intccpn0 signal is generated. ot herwise, the value of the ccra buff er register may become undefined because the timing of transferring data from the tpn ccra register to the ccra buffer register conflicts with writing the tpnccra register. remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 366 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. the 16-bit counter is cleared to 0000h and the intccpn0 and intccpn1 signals are generated at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register intccpn0 signal intccpn1 signal topn1 pin output external trigger input (tipn pin input) d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark n = 0 to 2 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register intccpn0 signal intccpn1 signal topn1 pin output d 0 ? 1d 0 ? 1 external trigger input (tipn pin input) remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 367 (c) conflict between trigger detection and match with ccr1 buffer register if the trigger is detected immediately after the int ccpn1 signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of t he topn1 pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccr1 buffer register intccpn1 signal topn1 pin output external trigger input (tipn pin input) d 1 d 1 ? 1 0000 ffff 0000 shortened remark n = 0 to 2 if the trigger is detected immediately before the int ccpn1 signal is generated, the intccpn1 signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. the output signal of the topn1 pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccr1 buffer register intccpn1 signal topn1 pin output external trigger input (tipn pin input) d 1 d 1 ? 2d 1 ? 1d 1 0000 ffff 0000 0001 extended remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 368 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the intccpn0 signal is generated, the 16 -bit counter is cleared to 0000h and continues counting up. therefore, the ac tive period of the topn1 pin is extended by time from generation of the intccpn0 signal to trigger detection. 16-bit counter ccr0 buffer register intccpn0 signal topn1 pin output external trigger input (tipn pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended remark n = 0 to 2 if the trigger is detected immediately before the int ccpn0 signal is generated, the intccpn0 signal is not generated. the 16-bit counter is cleared to 0000h, the topn1 pin is asserted, and the counter continues counting. consequently, the inactive period of the pwm waveform is shortened. 16-bit counter ccr0 buffer register intccpn0 signal topn1 pin output external trigger input (tipn pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 369 (e) generation timing of compare match interrupt request signal (intccpn1) the timing of generation of the intccpn1 signal in the external trigger pulse output mode differs from the timing of intccpn1 signals in other mode; the intccpn1 signal is gener ated when the count value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output intccpn1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 2 usually, the intccpn1 signal is generated in synchronization with the next count-up, after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the topn1 pin.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 370 8.6.4 one-shot pulse output mode (tpnmd2 to tpnmd0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter p waits for a trigger when the tpnctl0.tpnce bit is set to 1. when the valid edge of an external trigger inpu t (tipn) is detected, 16-bit timer/event counter p starts counting, and outputs a one-shot pulse from the topn1 pin. instead of the external trigger, a software trigger can also be generated to output the pulse. when the software trigger is used, the topn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when the counter is stopped (waiting for a trigger). figure 8-24. configuration in one-shot pulse output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal intccpn0 signal output controller (rs-ff) output controller (rs-ff) topn1 pin intccpn1 signal topn0 pin note count clock selection internal count clock count start control edge detector software trigger generation evtpn/tipn pin note (external event count input/external trigger input) edge detector transfer transfer s r s r note because the external event count input pin (evtpn ), external trigger input pin (tipn), and timer output pin (topn0) are the same alternate-function pin, two or more functions cannot be used at the same time. remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 371 figure 8-25. basic timing in one-shot pulse output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal tpnccr1 register intccpn1 signal topn1 pin output external trigger input (tipn pin input) topn0 pin output (only when software trigger is used) d 1 d 0 d 0 d 1 d 1 d 1 d 0 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) when the tpnce bit is set to 1, 16-bit timer/event counter p waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts coun ting, and outputs a one-shot pulse from the topn1 pin. after the one-shot pulse is output, the 16- bit counter is cleared to 0000h, stops counting, and waits for a trigger. when the trigger is generated again, the 16-bit counter star ts counting from 0000h. if a trigger is generated again while the one-shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tpnccr1 register) count clock cycle active level width = (set value of tpnccr0 register ? set value of tpnccr1 register + 1) count clock cycle the compare match interrupt request signal intccrn0 is generated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal intccrn1 is generated when the count value of the 16-bit counter matches the val ue of the ccr1 buffer register. the valid edge of an external trigger input (tipn pin) or setting the software trigger (tpnctl1.tpnest bit) to 1 is used as the trigger. remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 372 figure 8-26. setting of registers in one-shot pulse output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting is invalid when the tpnctl1.tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) 0 0/1 0/1 0 0 tpnctl1 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 0, 1, 1: one-shot pulse output mode tp2sye (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of output level while operation of topn1 pin is disabled 0: low level 1: high level 0/1 0/1 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 note clear this bit to 0 when the topn0 pin is not used in the one-shot pulse output mode.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 373 figure 8-26. setting of registers in one-shot pulse output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external trigger input (tipn pin) note select valid edge of external event count input (evtpn pin) note 0/1 0/1 0/1 tpnees0 tpnets1 tpnets0 tpnees1 note set the valid edge selection of the unused alternate external input signals to ?no edge detection?. (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d 1 ? d 0 + 1) count clock cycle output delay period = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the one-shot pulse output mode. 2. n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 374 (1) operation flow in one-shot pulse output mode figure 8-27. software processing flow in one-shot pulse output mode <1> <2> <3> start stop d 10 d 11 d 00 d 01 d 00 d 10 d 11 d 01 setting of tpnccr0, tpnccr1 registers <2> tpnccr0, tpnccr1 register setting change flow tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). trigger wait status count operation is stopped <1> count operation start flow <3> count operation stop flow ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal tpnccr1 register intccpn1 signal topn1 pin output external trigger input (tipn pin input) as rewriting the tpnccra register immediately forwards to the ccra buffer register, rewriting immediately after the generation of the intccpn0 signal is recommended. remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 375 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tpnccra register if the value of the tpnccra register is rewritten to a smaller value during counting, the 16-bit counter may overflow. when an overflow may occur, stop counting and then change the set value. d 10 d 11 d 00 d 01 d 00 d 10 d 10 d 10 d 01 d 11 d 00 d 00 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal tpnccr1 register intccpn1 signal topn1 pin output external trigger input (tipn pin input) topn0 pin output (only when software trigger is used) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (d 10 ) active level width (d 00 ? d 10 + 1) delay (10000h + d 11 ) active level width (d 01 ? d 11 + 1) when the tpnccr0 register is rewritten from d 00 to d 01 and the tpnccr1 register from d 10 to d 11 where d 00 > d 01 and d 10 > d 11 , if the tpnccr1 register is rewritten wh en the count value of the 16-bit counter is greater than d 11 and less than d 10 and if the tpnccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter counts up to ffffh and then counts up again from 0000h. when the count value matches d 11 , the counter generates the intccpn1 signal and asserts the topn1 pin. when the count value matches d 01 , the counter generates the intccpn0 signal, deasserts the topn1 pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark n = 0 to 2, a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 376 (b) generation timing of compare match interrupt request signal (intccpn1) the generation timing of the intccpn1 signal in the one-shot pulse output mode is different from intccpn1 signals in other mode; the intccpn1 signa l is generated when the co unt value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output intccpn1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 2 usually, the intccpn1 signal is generated when the 16- bit counter counts up ne xt time after its count value matches the value of the tpnccr1 register. in the one-shot pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the topn1 pin.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 377 8.6.5 pwm output mode (tpnmd 2 to tpnmd0 bits = 100) in the pwm output mode, a pwm waveform is output from the topn1 pin when the tpnctl0.tpnce bit is set to 1. in addition, a pwm waveform with a duty factor of 50% with the set value of the tpnccr0 register + 1 as half its cycle is output from the topn0 pin. figure 8-28. configuration in pwm output mode ccr0 buffer register tpnce bit tpnccr0 register 16-bit counter tpnccr1 register ccr1 buffer register clear match signal match signal intccpn0 signal output controller (rs-ff) output controller topn1 pin intccpn1 signal topn0 pin note count start control transfer transfer s r count clock selection internal count clock evtpn pin note (external event count input) edge detector note because the external event count input pin (evtpn) and timer output pin (topn0) are the same alternate-function pin, two or more func tions cannot be used at the same time. remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 378 figure 8-29. basic timing in pwm output mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register intccpn0 signal topn0 pin output tpnccr1 register ccr1 buffer register intccpn1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 active period (d 10 ) cycle (d 00 + 1) inactive period (d 00 - d 10 + 1) when the tpnce bit is set to 1, the 16 -bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a pwm waveform from the topn1 pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tpnccr1 register) count clock cycle cycle = (set value of tpnccr0 register + 1) count clock cycle duty factor = (set value of tpnccr1 regist er)/(set value of tpnccr0 register + 1) the pwm waveform can be changed by rewriting the tpnccra register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal intccpn0 is g enerated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal intccpn1 is gener ated when the count value of the 16-bit counter matches the value of the ccr1 buffer register. the value set to the tpnccra register is transferred to the ccra buffer register when the count value of the 16-bit counter matches the value of the ccra buffer regi ster and the 16-bit counter is cleared to 0000h. remark n = 0 to 2, a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 379 figure 8-30. setting of registers in pwm output mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting is invalid when the tpnctl1.tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 100 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 0, 0: pwm output mode 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count with external event count input signal tp2sye (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level while operation of topn0 pin is disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of output level while operation of topn1 pin is disabled 0: low level 1: high level 0/1 0/1 0/1 note tpnoe1 tpnol0 tpnoe0 tpnol1 topn1 pin output 16-bit counter ? when tpnol1 bit = 0 topn1 pin output 16-bit counter ? when tpnol1 bit = 1 note clear this bit to 0 when the topn0 pin is not used in the pwm output mode.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 380 figure 8-30. register setting in pwm output mode (2/2) (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input (evtpn pin). 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 (e) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (f) tmpn capture/compare register s 0 and 1 (tpnccr0 and tpnccr1) if d 0 is set to the tpnccr0 register and d 1 to the tpnccr1 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle active level width = d 1 count clock cycle remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the pwm output mode. 2. n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 381 (1) operation flow in pwm output mode figure 8-31. software processing flow in pwm output mode (1/2) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register intccpn0 signal topn0 pin output tpnccr1 register ccr1 buffer register intccpn1 signal topn1 pin output d 10 d 00 d 00 d 01 d 00 d 00 d 10 d 10 d 11 d 10 d 10 d 10 d 11 d 10 d 01 d 00 d 10 d 10 d 00 d 10 d 00 d 11 d 11 d 01 d 01 d 01 <1> <2> <3> <4> <5> remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 382 figure 8-31. software processing flow in pwm output mode (2/2) tpnce bit = 1 setting of tpnccr0 register register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting is enabled (tpnce bit = 1). writing same value (same as preset value of the tpnccr1 register) to the tpnccr1 register is necessary only when the set cycle is changed. when the counter is cleared after setting, the value of the tpnccra register is transferred to the ccra buffer register. start setting of tpnccr1 register <1> count operation start flow <2> tpnccr0, tpnccr1 register setting change flow (cycle only) setting of tpnccr0 register when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tpnccr1 register <4> tpnccr0, tpnccr1 register setting change flow (cycle and duty) only writing of the tpnccr1 register must be performed when the set duty factor is changed. when the counter is cleared after setting, the value of compare register a is transferred to the ccra buffer register. setting of tpnccr1 register <3> tpnccr0, tpnccr1 register setting change flow (duty only) tpnce bit = 0 counting is stopped. stop <5> count operation stop flow remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 383 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tpnccr1 register last. rewrite the tpnccra register after writing the tpnc cr1 register after the intccpn1 signal is detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register ccr0 buffer register tpnccr1 register ccr1 buffer register topn1 pin output intccpn0 signal d 10 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 11 d 01 d 10 d 10 d 00 d 00 d 11 d 11 d 01 d 01 to transfer data from the tpnccra register to the ccra buffer register, the tpnccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tpnccr0 register and then set the active level to the tpnccr1 register. to change only the cycle of the pwm waveform, first se t the cycle to the tpnccr0 register, and then write the same value (same as preset value of t he tpnccr1 register) to the tpnccr1 register. to change only the active level width (duty factor) of the pwm waveform, only the tpnccr1 register has to be set. after data is written to the tpnccr1 register, the valu e written to the tpnccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tpnccr0 or tpnccr1 register again after writing the tpnccr1 register once, do so after the intccpn0 signal is genera ted. otherwise, the valu e of the ccra buffer regi ster may become undefined because the timing of transferring data from the tpn ccra register to the ccra buffer register conflicts with writing the tpnccra register. remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 384 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tpnccr1 register to 0000h. the 16-bit counter is cleared to 0000h and the intccpn0 and intccpn1 signals are generated at the next timing after a match between the count value of the 16-bit counter and t he value of the ccr0 buffer register. count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register intccpn0 signal intccpn1 signal topn1 pin output d 00 0000h d 00 0000h d 00 0000h d 00 ? 1d 00 0000 ffff 0000 d 00 ? 1d 00 0000 0001 l remark n = 0 to 2 to output a 100% waveform, set a value of (set value of tpnccr0 register + 1) to the tpnccr1 register. if the set value of the tpnccr0 register is ffffh, 100% output cannot be produced. d 00 d 00 + 1 d 00 d 00 + 1 d 00 d 00 + 1 d 00 0000 ffff 0000 d 00 0000 0001 count clock 16-bit counter tpnce bit tpnccr0 register tpnccr1 register intccpn0 signal intccpn1 signal topn1 pin output d 00 ? 1d 00 ? 1 remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 385 (c) generation timing of compare match interrupt request signal (intccpn1) the timing of generation of the in tccpn1 signal in the pwm output mode differs from the timing of intccpn1 signals in other modes; the intccpn1 signal is generated when the count value of the 16-bit counter matches the value of the tpnccr1 register. count clock 16-bit counter tpnccr1 register topn1 pin output intccpn1 signal d 1 d 1 ? 2d 1 ? 1d 1 d 1 + 1 d 1 + 2 remark n = 0 to 2 usually, the intccpn1 signal is generated in synchronization with the next counting up after the count value of the 16-bit counter matches the value of the tpnccr1 register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the topn1 pin.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 386 8.6.6 free-running timer mode (t pnmd2 to tpnmd0 bits = 101) in the free-running timer mode, 16-bit timer/event counter p starts counting when the tpnctl0.tpnce bit is set to 1. at this time, the tpnccr0 and tpnccr1 registers c an be used as compare regist ers or capture registers, depending on the setting of the tpnopt0. tpnccs0 and tpnopt0.tpnccs1 bits. figure 8-32. configuration in free-running timer mode tpnccr0 register (capture) tpnce bit tpnccr1 register (compare) 16-bit counter tpnccr1 register (compare) tpnccr0 register (capture) output controller tpnccs0, tpnccs1 bits (capture/compare selection) topn0 pin note 1 output output controller topn1 pin note 2 output edge detector count clock selection edge detector edge detector evtpn/intppn0 pin note 1 (external event count input/ capture trigger input) intppn1 pin note 2 (capture trigger input) internal count clock 0 1 0 1 intovpn signal intccpn1 signal intccpn0 signal notes 1. because the external event count input pin (evtpn), capture trigger input pin (intppn0), and timer output pin (topn0) are the same alternate-function pin, two or more functions cannot be used at the same time. 2. because the capture trigger i nput pin (intppn1) and timer out put pin (topn1) are the same alternate-function pin, two or more func tions cannot be used at the same time. remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 387 ? compare operation when the tpnce bit is set to 1, 16-bit timer/event counter p starts counting, and the ou tput signals of the topn0 and topn1 pins are inverted. when the count value of the 16-bit counter later matches the set value of the tpnccra register, a compare match interrupt request sign al (intccpna) is generated, and the output signals of the topn0 and topn1 pins are inverted. the 16-bit counter continues counting in synchroniz ation with the co unt clock. when it counts up to ffffh, it generates an overflow interrupt request signal (intovpn) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bi t) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. the tpnccra register can be rewritten while the counter is ope rating. if it is rewritten, the new value is reflected at that time by anytime write, and compared with the count value. figure 8-33. basic timing in free-r unning timer mode (compare function) ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal topn0 pin output tpnccr1 register intccpn1 signal topn1 pin output intovpn signal tpnovf bit d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 388 ? capture operation when the tpnce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the intppna pin is detected, the count valu e of the 16-bit counter is stored in t he tpnccra register, and a capture interrupt request signal (intccpna) is generated. the 16-bit counter continues counting in synchroniz ation with the co unt clock. when it counts up to ffffh, it generates an overflow interrupt request signal (intovpn) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tpnopt0.tpnovf bi t) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. figure 8-34. basic timing in free-r unning timer mode (capture function) ffffh 16-bit counter 0000h tpnce bit intppn0 pin input tpnccr0 register intccpn0 signal intppn1 pin input tpnccr1 register intccpn1 signal intovpn signal tpnovf bit d 00 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 13 d 10 d 11 d 12 d 13 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 389 figure 8-35. register setting in free-running timer mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note the setting is invalid when the tpnctl1.tpneee bit = 1 (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 101 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest tp2sye 1, 0, 1: free-running timer mode 0: operate with count clock selected by tpncks0 to tpncks2 bits 1: count on external event count input signal (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting of output level with operation of topn0 pin disabled 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting of output level with operation of topn1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 select valid edge of intppn0 pin input note select valid edge of intppn1 pin input 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 note set the valid edge selection of the unused alternat e external input signals to ?no edge detection?.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 390 figure 8-35. register setting in free-running timer mode (2/2) (e) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input (evtpn pin) note 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 note set the valid edge selection of the unused alternat e external input signals to ?no edge detection?. (f) tmpn option register 0 (tpnopt0) 0 0 0/1 0/1 0 tpnopt0 overflow flag specifies if tpnccr0 register functions as capture or compare register 0: compare register 1: capture register specifies if tpnccr1 register functions as capture or compare register 0: compare register 1: capture register 0 0 0/1 tpnccs0 tpnovf tpnccs1 (g) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (h) tmpn capture/compare regist ers 0 and 1 (tpnccr0 and tpnccr1) these registers function as capt ure registers or compare registers depending on the setting of the tpnopt0.tpnccsa bit. when the registers function as capture registers, they store the count value of the 16-bit counter when the valid edge input to the intppna pin is detected. when the registers function as compare registers and when d a is set to the tpnccra register, the intccpna signal is generated when the counter reaches (d a + 1), and the output signals of the topn0 and topn1 pins are inverted. remark n = 0 to 2, a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 391 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 8-36. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 00 d 01 d 10 d 11 d 00 d 10 d 10 d 11 d 11 d 11 d 00 d 01 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <1> <2> <2> <2> <3> ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal topn0 pin output tpnccr1 register intccpn1 signal topn1 pin output intovpn signal tpnovf bit remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 392 figure 8-36. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag). register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register, tpnopt0 register, tpnccr0 register, tpnccr1 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). start execute instruction to clear tpnovf bit (clr tpnovf). <1> count operation start flow <2> overflow flag clear flow tpnce bit = 0 counter is initialized and counting is stopped by clearing tpnce bit to 0. stop <3> count operation stop flow tpnovf bit = 1 no yes remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 393 (b) when using capture/compare register as capture register figure 8-37. software processing flow in fr ee-running timer mode (c apture function) (1/2) ffffh 16-bit counter 0000h tpnce bit intppn0 pin input tpnccr0 register intccpn0 signal intppn1 pin input tpnccr1 register intccpn1 signal intovpn signal tpnovf bit d 00 0000 0000 d 01 d 02 d 03 d 10 d 00 d 01 d 02 d 03 d 11 d 12 d 10 0000 d 11 d 12 0000 cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 394 figure 8-37. software processing flow in fr ee-running timer mode (c apture function) (2/2) tpnce bit = 1 read tpnopt0 register (check overflow flag). register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc1 register, tpnopt0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). start execute instruction to clear tpnovf bit (clr tpnovf). <1> count operation start flow <2> overflow flag clear flow tpnce bit = 0 counter is initialized and counting is stopped by clearing tpnce bit to 0. stop <3> count operation stop flow tpnovf bit = 1 no yes remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 395 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter p is used as an interval timer with the tpnccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the intccpna signal has been detected. ffffh 16-bit counter 0000h tpnce bit tpnccr0 register intccpn0 signal topn0 pin output tpnccr1 register intccpn1 signal topn1 pin output d 00 d 01 d 02 d 03 d 04 d 05 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 11 d 10 d 12 d 13 d 14 interval period (d 10 + 1) interval period (10000h + d 11 ? d 10 ) interval period (10000h + d 12 ? d 11 ) interval period (10000h + d 13 ? d 12 ) interval period (d 00 + 1) interval period (10000h + d 01 ? d 00 ) interval period (d 02 ? d 01 ) interval period (10000h + d 03 ? d 02 ) interval period (10000h + d 04 ? d 03 ) when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the co rresponding tpnccra register must be re-set in the interrupt servicing that is executed when the intccpna signal is detected. the set value for re-setting the tpnccra register ca n be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 396 (b) pulse width measurement with capture register when pulse width measurement is performed with t he tpnccra register used as a capture register, software processing is necessary for reading the capture register each time the intccpna signal has been detected and for calculating an interval. 0000h d 00 d 01 d 02 d 03 d 04 d 10 d 00 d 11 d 01 d 12 d 04 d 13 d 02 d 03 d 10 0000h d 11 d 12 d 13 ffffh 16-bit counter 0000h tpnce bit intppn0 pin input tpnccr0 register intccpn0 signal intppn1 pin input tpnccr1 register intccpn1 signal intovpn signal tpnovf bit pulse interval (d 00 ) pulse interval (10000h + d 01 - d 00 ) pulse interval (d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) pulse interval (10000h + d 04 ? d 03 ) pulse interval (d 10 ) pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (10000h + d 13 ? d 12 ) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction when executing pulse width measurement in the fr ee-running timer mode, two pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calculated by reading the value of the tpnccra register in synchronization with the intccpna signal, and calc ulating the difference between the read value and the previously read value. remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 397 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tpnce bit intppn0 pin input tpnccr0 register intppn1 pin input tpnccr1 register intovpn signal tpnovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tpnccr0 register (setting of t he default value of the intppn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the intppn1 pin input). <3> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tpnccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). remark n = 0 to 2 when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 398 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tpnce bit intovpn signal tpnovf bit tpnovf0 flag note intppn0 pin input tpnccr0 register tpnovf1 flag note intppn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of t he default value of the intppn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the intppn1 pin input). <3> an overflow occurs. set the tpnovf0 and tpnovf 1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tpnccr0 register. read the tpnovf0 flag. if the tpnovf0 flag is 1, clear it to 0. because the tpnovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tpnccr1 register. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0 (the tpnovf0 flag is cleared in <4>, and the tpnovf1 flag remains 1). because the tpnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 399 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tpnce bit intovpn signal tpnovf bit tpnovf0 flag note intppn0 pin input tpnccr0 register tpnovf1 flag note intppn1 pin input tpnccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tpnovf0 and tpnovf1 flags are set on the internal ram by software. <1> read the tpnccr0 register (setting of t he default value of the intppn0 pin input). <2> read the tpnccr1 register (setting of t he default value of the intppn1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tpnccr0 register. read the overflow flag. if the overflow flag is 1, set only the tpnovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tpnccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tpnovf1 flag. if the tpnovf1 flag is 1, clear it to 0. because the tpnovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3> remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 400 (d) processing of overflow if capture trigger interval is long if the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tpnce bit intppna pin input tpnccra register intovpn signal tpnovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when long pulse width is measured in the free-running timer mode. <1> read the tpnccra register (setting of t he default value of the intppna pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tpnccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. remark n = 0 to 2 a = 0, 1 if an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 401 example when capture trigger interval is long ffffh 16-bit counter 0000h tpnce bit intppna pin input tpnccra register intovpn signal tpnovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tpnccra register (setting of t he default value of the intppna pin input). <2> an overflow occurs. increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tpnccra register. read the overflow counter. when the overflow counter is ?n?, the pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h). remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 402 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tpnovf bit to 0 with the clr instruction after reading the tpnovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to the tpnopt0 register after reading the tpnovf bit when it is 1. (3) note on capture operation if the capture operation is used and if a slow clock is selected as the count clock, ffffh, not 0000h, may be captured to the tpnccra register if the capture trigger is input immediately after the tpnctl0.tpnce bit is set to 1. count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0001h 0000h intppn0 pin input capture trigger input 16-bit counter sampling clock capture trigger input remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 403 8.6.7 pulse width measurement mode (tpnmd2 to tpnmd0 bits = 110) in the pulse width measurement mode, 16-bit timer/even t counter p starts counting when the tpnctl0.tpnce bit is set to 1. each time the valid edge input to the intppna pin has been detected, the count value of the 16-bit counter is stored in the tpnccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by reading the tpnccra register after a capture interrupt request signal (intccpna) occurs. as shown in figure 8-39, select eit her the intppn0 or intppn1 pin as t he capture trigger input pin and set the unused pins to ?no edge detection? by using the tpnioc1 register. when the external event count input signal (evtpn pin) is used as the count clock, measure the pulse width of the intppn1 pin because the evtpn pin functions alternately as a capture trigger input signal (intppn0 pin). at this time, clear the tpnioc1.tpnis1 and tpnioc1.tpnis0 bits to 00 (capture trigger input (intppn0 pin): no edge detection). figure 8-38. configuration in pulse width measurement mode tpnccr0 register (capture) tpnce bit tpnccr1 register (capture) edge detector count clock selection edge detector edge detector evtpn/intppn0 pin (external event count input/capture trigger input) intppn1 pin (capture trigger input) internal count clock clear intovpn signal intccpn0 signal intccpn1 signal 16-bit counter remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 404 figure 8-39. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tpnce bit intppna pin input tpnccra register intccpn signal intovpn signal tpnovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark n = 0 to 2 a = 0, 1 when the tpnce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the intppna pin is later detected, the count value of the 16- bit counter is stored in the tpnccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (intccpna) is generated. the pulse width is calculated as follows. pulse width = d n count clock cycle if the valid edge is not input to the tipnm pin even when the 16-bit counter counted up to ffffh, an overflow interrupt request signal (intovpn) is generated at the ne xt count clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tpnopt0.t pnovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tpnovf bit set (1) count + d n ) count clock cycle remark n = 0 to 2 a = 0, 1
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 405 figure 8-40. register setting in pu lse width measurement mode (1/2) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce note setting is invalid when the tpnctl1.tpneee bit = 1. (b) tmpn control register 1 (tpnctl1) 0 0 0/1 0 0 tpnctl1 110 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tpncks0 to tpncks2 bits 1: count external event count input signal tp2sye (c) tmpn i/o control register 1 (tpnioc1) 0 0 0 0 0/1 tpnioc1 select valid edge of intppn0 pin input note select valid edge of intppn1 pin input 0/1 0/1 0/1 tpnis2 tpnis1 tpnis0 tpnis3 note set the valid edge selection of the unused alter nate external input signals to ?no edge detection?. (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 tpnioc2 select valid edge of external event count input (evtpn pin) note 0/1 0 0 tpnees0 tpnets1 tpnets0 tpnees1 note set the valid edge selection of the unused alter nate external input signals to ?no edge detection?.
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 406 figure 8-40. register setting in pu lse width measurement mode (2/2) (e) tmpn option register 0 (tpnopt0) 00000 tpnopt0 overflow flag 0 0 0/1 tpnccs0 tpnovf tpnccs1 (f) tmpn counter read bu ffer register (tpncnt) the value of the 16-bit counter can be read by reading the tpncnt register. (g) tmpn capture/compare regist ers 0 and 1 (tpnccr0 and tpnccr1) these registers store the count value of the 16-bit counter when the valid edge input to the intppn0 and intppn1 pins is detected. remarks 1. tmpn i/o control register 0 (tpnioc0) is not used in the pulse wid th measurement mode. 2. n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 407 (1) operation flow in pul se width measurement mode figure 8-41. software processing flow in pulse width measurement mode tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits), tpnctl1 register, tpnioc1 register, tpnioc2 register, tpnopt0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. start stop <1> count operation start flow <2> count operation stop flow <1> <2> ffffh 16-bit counter 0000h tpnce bit intppn0 pin input tpnccr0 register intccpn0 signal d 0 0000h 0000h d 1 d 2 remark n = 0 to 2
chapter 8 16-bit timer/event counter p (tmp) user?s manual u16397ej3v0ud 408 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing the tpnovf bit to 0 with the clr instruction after reading the tpnovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to the tpnopt0 register after reading the tpnovf bit when it is 1. (3) notes on capture operation if a slow clock is selected as the count clock, ffffh, not 0000h, may be captured to the tpnccra register if the capture trigger is input immediately afte r the tpnctl0.tpnce bit has been set to 1. count clock 0000h ffffh tpnce bit tpnccr0 register ffffh 0002h 0000h intppn0 pin input capture trigger input 16-bit counter sampling clock capture trigger input remark n = 0 to 2 a = 0, 1
user?s manual u16397ej3v0ud 409 chapter 9 16-bit timer/event counter q (tmq) timer q (tmq) is a 16-bit timer/event counter. the v850e/ma3 incorporates tmq0. 9.1 overview an outline of tmq0 is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 4 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 4 ? capture/compare match interrupt request signals: 4 ? timer output pins note : 4 note this is the number of output pins of tmq0; it does not include the output pins of tmqop0. for details of the output pins of tmqop0, see chapter 12 motor control function . 9.2 functions tmq0 has the following functions. ? 6-phase pwm output note ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement note this is connected to tmqop0. for details, see chapter 12 motor control function .
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 410 9.3 configuration tmq0 includes the following hardware. table 9-1. tmq0 configuration item configuration timer register 16-bit counter registers tmq0 counter read buffer register (tq0cnt) tmq0 capture/compare registers 0 to 3 (tq0ccr0 to tq0ccr3) ccr0 to ccr3 buffer registers timer input total of 6 (tiq, evtq, intpq0 to intpq3 pins) timer output total of 4 (toq0 to toq3 pins) control registers tmq0 control registers 0, 1 (tq0ctl0, tq0ctl1) tmq0 i/o control registers 0 to 2 (tq0ioc0 to tq0ioc2) tmq0 option register 0 (tq0opt0) figure 9-1. tmq0 block diagram selector selector f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 internal bus internal bus tq0cnt tq0ccr0 ccr1 buffer register tq0ccr1 intpq0 evtq intpq1 intpq2 intpq3 edge detector edge detector output controller ccr0 buffer register tq0ccr2 ccr3 buffer register tq0ccr3 ccr2 buffer register clear intovq intccq0 intccq1 intccq2 intccq3 toq0 toq1 toq2 toq3 16-bit counter tiq remark f xx : peripheral clock
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 411 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tq0cnt register. when the tq0ctl0.tq0ce bit = 0, the va lue of the 16-bit counter is ffffh. if the tq0cnt register is read at this time, 0000h is read. reset input clears the tq0ce bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr0 register is used as a compare regist er, the value written to the tq0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interr upt request signal (intccq0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, and the tq0ccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr1 register is used as a compare regist er, the value written to the tq0ccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interr upt request signal (intccq1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, and the tq0ccr1 register is cleared to 0000h. (4) ccr2 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr2 register is used as a compare regist er, the value written to the tq0ccr2 register is transferred to the ccr2 buffer register. when the count value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interr upt request signal (intccq2) is generated. the ccr2 buffer register cannot be read or written directly. the ccr2 buffer register is cleared to 0000h after reset, and the tq0ccr2 register is cleared to 0000h. (5) ccr3 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tq0ccr3 register is used as a compare regist er, the value written to the tq0ccr3 register is transferred to the ccr3 buffer register. when the count value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interr upt request signal (intccq3) is generated. the ccr3 buffer register cannot be read or written directly. the ccr3 buffer register is cleared to 0000h after reset, and the tq0ccr3 register is cleared to 0000h. (6) edge detector this circuit detects the valid edges input to the tiq, evtq, and intpq0 to intpq3 pins. no edge, rising edge, falling edge, or both the ri sing and falling edges can be selected as the valid edge by using the tq0ioc1 and tq0ioc2 registers. (7) output controller this circuit controls the output of the toq0 to toq3 pins. the output controller is controlled by the tq0ioc0 register.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 412 (8) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 413 9.4 registers (1) tmq0 control register 0 (tq0ctl0) the tq0ctl0 register is an 8-bit register that controls the operation of tmq0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tq0ctl0 register by software. tq0ce tmq0 operation disabled (tmq0 reset asynchronously note ). tmq0 operation enabled. tmq0 operation started. tq0ce 0 1 tmq0 operation control tq0ctl0 0 0 0 0 tq0cks2 tq0cks1 tq0cks0 654321 after reset: 00h r/w address: fffff600h <7> 0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 tq0cks2 0 0 0 0 1 1 1 1 internal count clock selection tq0cks1 0 0 1 1 0 0 1 1 tq0cks0 0 1 0 1 0 1 0 1 note the tpnopt0.tpnovf bit and the 16-bi t counter are reset simultaneously. moreover, timer outputs (toqn0 to toqn3 pins) are reset to the tq0ioc0 regi ster set status at the same time as the 16-bit counter. cautions 1. set the tq0cks2 to tq0 cks0 bits when the tq0ce bit = 0. when the value of the tq0ce bit is changed from 0 to 1, the tq0cks2 to tq0cks0 bits can be set simultaneously. 2. be sure to set bits 3 to 6 to ?0?. remark f xx : peripheral clock
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 414 (2) tmq0 control register 1 (tq0ctl1) the tq0ctl1 register is an 8-bit register that controls the operation of tmq0. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tq0est 0 1 software trigger control tq0ctl1 tq0est tq0eee 0 0 tq0md2 tq0md1 tq0md0 654321 after reset: 00h r/w address: fffff601h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tq0est bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tq0est bit as the trigger. disable operation with external event count input (evtq pin). (perform counting with the count clock selected by the tq0ctl0.tq0cks0 to tq0cks2 bits.) tq0eee 0 1 count clock selection the tq0eee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode 6-phase pwm output mode note tq0md2 0 0 0 0 1 1 1 1 timer mode selection tq0md1 0 0 1 1 0 0 1 1 tq0md0 0 1 0 1 0 1 0 1 enable operation with external event count input (evtq pin). (perform counting at the valid edge of the external event count input signal.) ? read value of the tq0est bit is always 0. note the 6-phase pwm output mode cannot be used when only tmq0 is used. for details, see chapter 12 motor control function . cautions 1. the tq0est bit is valid only in the ex ternal trigger pulse output mode or one-shot pulse output mode. in any other mode, wr iting 1 to this bit is ignored. 2. external event count input is selected in th e external event count mode regardless of the value of the tq0eee bit. 3. set the tq0eee and tq0md2 to tq0md0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) the operation is not guaranteed when rewriting is performed with the tq0ce bit = 1. if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 4. be sure to set bits 3, 4, and 7 to ?0?.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 415 (3) tmq0 i/o control register 0 (tq0ioc0) the tq0ioc0 register is an 8-bit re gister that controls the timer out put (toq0 to toq3, toqt1 to toqt3 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0ol3 tq0olm 0 1 toqm, toqtb pin output level setting note (m = 0 to 3, b = 1 to 3) toqm, toqtb pin starts output at high level. toqm, toqtb pin starts output at low level. tq0ioc0 tq0oe3 tq0ol2 tq0oe2 tq0ol1 tq0oe1 tq0ol0 tq0oe0 <6> 5 <4> 3 <2> 1 after reset: 00h r/w address: fffff602h tq0oem 0 1 toqm, toqtb pin output setting (m = 0 to 3, b = 1 to 3) timer output disabled ? when tq0olm bit = 0: low level is output from the toqm, toqtb pin ? when tq0olm bit = 1: high level is output from the toqm, toqtb pin 7 <0> timer output enabled (a pulse is output from the toqm, toqtb pin). note the output level of the timer output pins (toqm and toqtb) specified by the tq0olm bit is shown below. tq0ce bit toqm and toqtb output pins 16-bit counter ? when tq0olm bit = 0 tq0ce bit toqm and toqtb output pins 16-bit counter ? when tq0olm bit = 1 cautions 1. if the setting of the tq0ioc0 register is changed when toqm and toqtb are set in the output mode, the output of the pins change. set the port in the input mode and make the port go into a high-impedance state, noting changes in the pin status. 2. rewrite the tq0olm and tq0oem bits wh en the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear (0) the tq0ce bit and then set the bits again. 3. if the tq0olm bit is manipulated when th e tq0ce and tq0oem bits are 0, the output level of the toqm and toqtb pins changes. 4. to generate the toqtb pin output and the a/d conversion start trigger signal of a/d converter in the 6-phase pwm output mode, be su re to set the toqtb pin output using the tq0ioc0 register. at this time, be sure to cl ear the tq0ol0 bit to 0 and set the tq0oe0 bit to 1 (b = 1 to 3). remark m = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 416 (4) tmq0 i/o control register 1 (tq0ioc1) the tq0ioc1 register is an 8-bit regi ster that controls the valid edge of the capture trigger input signals (intpq0 to intpq3 pins). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0is7 tq0is7 0 0 1 1 tq0is6 0 1 0 1 capture trigger input signal (intpq3 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc1 tq0is6 tq0is5 tq0is4 tq0is3 tq0is2 tq0is1 tq0is0 654321 after reset: 00h r/w address: fffff603h tq0is5 0 0 1 1 tq0is4 0 1 0 1 capture trigger input signal (intpq2 pin) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 tq0is3 0 0 1 1 tq0is2 0 1 0 1 capture trigger input signal (intpq1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0is1 0 0 1 1 tq0is0 0 1 0 1 capture trigger input signal (intpq0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges cautions 1. rewrite the tq0is7 to tq0is0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear th e tq0ce bit to 0 and then set the bits again. 2. the tq0is7 to tq0is0 bits ar e valid only in the free-running timer mode (only when the tq0opt0.tq 0ccsm bit = 1) and the pulse width measurement mode. in all other modes, a capture operation is not possible.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 417 (5) tmq0 i/o control register 2 (tq0ioc2) the tq0ioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tiq pin) and external trigger input signal (evtq pin). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tq0ees1 0 0 1 1 tq0ees0 0 1 0 1 external event count input signal (evtq pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc2 0 0 0 tq0ees1 tq0ees0 tq0ets1 tq0ets0 654321 after reset: 00h r/w address: fffff604h tq0ets1 0 0 1 1 tq0ets0 0 1 0 1 external trigger input signal (tiq pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tq0ees1, tq0 ees0, tq0ets1, and tq0ets0 bits when the tq0ctl0.tq0ce bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0ce bit to 0 and then set the bits again. 2. the tq0ees1 and tq0ees0 bits are valid only when the tq0ctl1.tq0eee bit = 1 or when the external event count mode (tq0ctl1.tq0md2 to tq0ctl1.tq0md 0 bits = 001) has been set. 3. the tq0ets1 and tq0ets0 bits ar e valid only in the external trigger pulse output mode or one-s hot pulse output mode.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 418 (6) tmq0 option register 0 (tq0opt0) the tq0opt0 register is an 8-bit register used to set the capture/co mpare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0ccs3 tq0ccsm 0 1 tq0ccrm register capture/compare selection (m = 0 to 3) the tq0ccsm bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by tq0ctl0.tq0ce bit = 0) tq0opt0 tq0ccs2 tq0ccs1 tq0ccs0 0 tq0cms note tq0cuf note tq0ovf <6> <5> <4> 3 <2> <1> after reset: 00h r/w address: fffff605h tq0ovf set (1) reset (0) tmq0 overflow flag  the tq0ovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode.  an overflow interrupt request signal (intovq) is generated at the same time that thetq0ovf bit is set to 1. the intovq signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode.  the tq0ovf bit is not cleared to 0 even when the tq0ovf bit or the tq0opt0 register are read when the tq0ovf bit = 1.  before clearing the tq0ovf bit to 0 after generation of the intovq signal, be sure to confirm (by reading) that the tq0ovf bit is set to 1.  the tq0ovf bit can be both read and written, but the tq0ovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmq0. overflow occurred tq0ovf bit 0 written or tq0ctl0.tq0ce bit = 0 <7> <0> note for details of the tq0cms and tq0cuf bits, see chapter 12 motor control function . cautions 1. rewrite the tq0ccs3 to tq0ccs 0 bits when the tq0c e bit = 0. (the same value can be written when the tq0ce bit = 1.) if rewriting was mistakenly performed, clear the tq0c e bit to 0 and then set the bits again. 2. be sure to set bit 3 to 0.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 419 (7) tmq0 capture/compare register 0 (tq0ccr0) the tq0ccr0 register can be used as a capture register or a com pare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tq0o pt0.tq0ccs0 bit. in the pulse width measurement mode, the tq0ccr0 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tq0ccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff606h 14 0 13 11 9 7 5 3 15 1
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 420 (a) function as compare register the tq0ccr0 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (intccq0) is generated. if toq0 pin output is enabled at this time, the output of the toq0 pin is inverted. when the tq0ccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. the compare register is not cleared by setting the tq0ctl0.tq0ce bit to 0. (b) function as capture register when the tq0ccr0 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tq0ccr0 register if the valid ed ge of the capture trigger input pin (intpq0 pin) is detected. in the pulse-width measurement mode, t he count value of the 16-bit counter is stored in the tq0ccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (intpq 0 pin) is detected. even if the capture operation and reading the tq0c cr0 register conflict, the correct value of the tq0ccr0 register can be read. the capture register is cleared by setting the tq0ctl0.tq0ce bit = 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 9-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tq0ccr1 register is the trigger. remark for anytime write and batch write, see 9.6 (2) anytime write and batch write .
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 421 (8) tmq0 capture/compare register 1 (tq0ccr1) the tq0ccr1 register, which consists of 16 bits, can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tq0o pt0.tq0ccs1 bit. in the pulse width measurement mode, the tq0ccr1 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tq0ccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff608h 14 0 13 11 9 7 5 3 15 1
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 422 (a) function as compare register the tq0ccr1 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (intccq1) is generated. if toq1 pin output is enabled at this time, the output of the toq1 pin is inverted. the compare register is not cleared by setting the tq0ctl0.tq0ce bit to 0. (b) function as capture register when the tq0ccr1 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tq0ccr1 register if the valid ed ge of the capture trigger input pin (intpq1 pin) is detected. in the pulse-width measurement mode, t he count value of the 16-bit counter is stored in the tq0ccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (intpq 1 pin) is detected. even if the capture operation and reading the tq0c cr1 register conflict, the correct value of the tq0ccr1 register can be read. the capture register is cleared by setting the tq0ctl0.tq0ce bit to 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 9-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tq0ccr1 register is the trigger. remark for anytime write and batch write, see 9.6 (2) anytime write and batch write .
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 423 (9) tmq0 capture/compare register 2 (tq0ccr2) the tq0ccr2 register, which consists of 16 bits, can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tq0o pt0.tq0ccs2 bit. in the pulse width measurement mode, the tq0ccr2 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tq0ccr2 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0ccr2 12 10 8 6 4 2 after reset: 0000h r/w address: fffff60ah 14 0 13 11 9 7 5 3 15 1
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 424 (a) function as compare register the tq0ccr2 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr2 register is transferred to the ccr2 buffer register. when the value of the 16-bit counter matches the value of the ccr2 buffer register, a compare match interrupt request signal (intccq2) is generated. if toq2 pin output is enabled at this time, the output of the toq2 pin is inverted. the compare register is not cleared by setting the tq0ctl0.tq0ce bit to 0. (b) function as capture register when the tq0ccr2 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tq0ccr2 register if the valid ed ge of the capture trigger input pin (intpq2 pin) is detected. in the pulse-width measurement mode, t he count value of the 16-bit counter is stored in the tq0ccr2 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (intpq 2 pin) is detected. even if the capture operation and reading the tq0c cr2 register conflict, the correct value of the tq0ccr2 register can be read. the capture register is cleared by setting the tq0ctl0.tq0ce bit to 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 9-4. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tq0ccr1 register is the trigger. remark for anytime write and batch write, see 9.6 (2) anytime write and batch write .
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 425 (10) tmq0 capture/compare register 3 (tq0ccr3) the tq0ccr3 register, which consists of 16 bits, can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tq0o pt0.tq0ccs3 bit. in the pulse width measurement mode, the tq0ccr3 register can be used only as a capture register. in any other m ode, this register can be used only as a compare register. the tq0ccr3 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0ccr3 12 10 8 6 4 2 after reset: 0000h r/w address: fffff60ch 14 0 13 11 9 7 5 3 15 1
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 426 (a) function as compare register the tq0ccr3 register can be rewritten even when the tq0ctl0.tq0ce bit = 1. the set value of the tq0ccr3 register is transferred to the ccr3 buffer register. when the value of the 16-bit counter matches the value of the ccr3 buffer register, a compare match interrupt request signal (intccq3) is generated. if toq3 pin output is enabled at this time, the output of the toq3 pin is inverted. the compare register is not cleared by setting the tq0ctl0.tq0ce bit to 0. (b) function as capture register when the tq0ccr3 register is used as a capture register in the free- running timer mode, the count value of the 16-bit counter is stored in the tq0ccr3 register if the valid ed ge of the capture trigger input pin (intpq3 pin) is detected. in the pulse-width measurement mode, t he count value of the 16-bit counter is stored in the tq0ccr3 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (intpq 3 pin) is detected. even if the capture operation and reading the tq0c cr3 register conflict, the correct value of the tq0ccr3 register can be read. the capture register is cleared by setting the tq0ctl0.tq0ce bit to 0. the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 9-5. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note writing to the tq0ccr1 register is the trigger. remark for anytime write and batch write, see 9.6 (2) anytime write and batch write .
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 427 (11) tmq0 counter read buffer register (tq0cnt) the tq0cnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tq0ctl0.tq0ce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tq0cnt register is cleared to 0000h when the tq0ce bit = 0. if the tq0cnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tq0cnt register is cleared to 0000h after reset, and the tq0ce bit is cleared to 0. tq0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff60eh 14 0 13 11 9 7 5 3 15 1
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 428 9.5 timer output operations the following table shows the operations and out put levels of the toq0 to toq3 pins. table 9-6. timer output control in each mode operation mode toq0 pin toq1 pin toq2 pin toq3 pin interval timer mode pwm output external event count mode none external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output pwm output free-running timer mode pwm output (only when compare function is used) pulse width measurement mode none table 9-7. truth table of toq0 to toq3 pins under control of timer output control bits tq0ioc0.tq0ola bit tq0ioc0.tq0oea bit tq0ctl0.tq0ce bit level of toq0a pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 429 9.6 operation tmq0 can perform the following functions. operation tq0ctl1.tq0est bit (software trigger bit) tiq pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode invalid invalid compare only anytime write external trigger pulse output mode va lid valid compare only batch write one-shot pulse output mode valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode invalid invalid capture only not applicable
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 430 (1) counter basic operation this section explains the basic oper ation of the 16-bit counter. for details, refer to the description of the operation in each mode. (a) counter start operation the 16-bit counter of tmq0 starts counti ng from the default value ffffh in all modes. it counts up from ffffh to 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its value matches the value of the compare register and when its value is captured. the counting operation from ff ffh to 0000h that takes place immediately after the counter has started counting or when the counter overflows is not a clearing operation. therefore, the intccqm interrupt signal is not generated (m = 0 to 3). (c) overflow operation the 16-bit counter overflows when the counter counts up from ffffh to 0000h in the free-running mode or pulse width measurement mode. if the counter overflows, the tq0o pt0.tq0ovf bit is set to 1 and an interrupt request signal (intovq) is generated. note that the intovq signal is not generated under the following conditions. ? immediately after a count operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured in the pulse width measur ement mode and the counter counts up from ffffh to 0000h caution after the overflow interru pt request signal (intovq) has been generated, be sure to check that the overflow flag (tq0ovf bit) is set to 1. (d) counter read operation during counting operation the value of the 16-bit counter of tmq0 can be re ad by using the tq0cnt r egister during the count operation. when the tq0ctl0.tq0ce bit = 1, the val ue of the 16-bit counter c an be read by reading the tq0cnt register. when the tq0ce bit = 0, the 16-bit counter is fff fh and the tq0cnt register is 0000h. (e) interrupt operation tmq0 generates the following five interrupt request signals. ? intccq0 interrupt: this signal functions as a match interrupt request signal of the ccr0 buffer register and as a capture interrupt request signal to the tq0ccr0 register. ? intccq1 interrupt: this signal functions as a match interrupt request signal of the ccr1 buffer register and as a capture interrupt request signal to the tq0ccr1 register. ? intccq2 interrupt: this signal functions as a match interrupt request signal of the ccr2 buffer register and as a capture interrupt request signal to the tq0ccr2 register. ? intccq3 interrupt: this signal functions as a match interrupt request signal of the ccr3 buffer register and as a capture interrupt request signal to the tq0ccr3 register. ? intovq interrupt: this signal functions as an overflow interrupt request signal.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 431 (2) anytime write and batch write the tq0ccr0 to tq0ccr3 registers can be rewritten in the tmq0 during timer operation (tq0ctl0.tq0ce bit = 1), but the write method (anytime write, batch wr ite) of the ccr0 to ccr3 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the tq0ccr0 to tq0ccr3 registers to the ccr0 to ccr3 buffer registers during the timer operation. figure 9-2. flowchart of basic operation for anytime write start initial settings ? set values to tq0ccra register ? timer operation enable (tq0ce bit = 1) transfer values of tq0ccra register to ccra buffer register timer operation ? match between 16-bit counter and ccrb buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start intccq0 signal output tq0ccra register rewrite transfer to ccra buffer register intccqb signal output note the 16-bit counter is not cleared upon a match between the 16-bit counter value and the ccrb buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. a = 0 to 3 b = 1 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 432 figure 9-3. timing of anytime write tq0ce bit = 1 16-bit counter tq0ccr0 register tq0ccr1 register tq0ccr2 register tq0ccr3 register intccq0 signal intccq1 signal intccq2 signal intccq3 signal ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 11 d 11 d 12 d 11 d 11 d 12 d 12 d 21 d 21 d 21 d 01 d 01 d 02 d 02 d 01 d 12 d 21 0000h d 01 d 02 0000h d 21 d 31 0000h d 31 d 31 d 31 d 31 d 31 0000h ffffh remarks 1. d 01 , d 02 : setting values of tq0ccr0 register d 11 , d 12 : setting values of tq0ccr1 register d 21 : setting value of tq0ccr2 register d 31 : setting value of tq0ccr3 register 2. the above timing chart illustrates an example of the operation in the interval timer mode.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 433 (b) batch write in this mode, data is transferred all at once from the tq0ccr0 to tq0ccr3 registers to the ccr0 to ccr3 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the tq0ccr1 register. whether to enable or disable the next transfer timing is controlled by writing or not writing to the tq0ccr1 register. in order for the setting value when the tq0ccr0 to tq 0ccr3 registers are rewritten to become the 16-bit counter comparison value (in other words, in order fo r this value to be transferred to the ccr0 to ccr3 buffer registers), it is necessary to rewrite tq0ccr0 and finally write to the tq0ccr1 register before the 16-bit counter value and the ccr0 buffer register val ue match. the values of the tq0ccr0 to tq0ccr3 registers are transferred to the ccr0 to ccr3 buffer registers upon a match bet ween the count value of the 16-bit counter and the value of the ccr0 buffer re gister. thus, even when wishing only to rewrite the value of the tq0ccr0, tq0ccr2, or tq0ccr3 register, also write the same value (same as preset value of the tq0ccr1 register) to the tq0ccr1 register.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 434 figure 9-4. flowchart of basic operation for batch write start initial settings ? set values to tq0ccra register ? timer operation enable (tq0ce bit = 1) transfer of values of tq0ccra register to ccra buffer register timer operation ? match between 16-bit counter and ccrb buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of tq0ccra register to ccra buffer register intccqb signal output tq0ccry register rewrite tq0ccr1 register rewrite intccq0 signal output batch write enable note the 16-bit counter is not cleared upon a match between the 16-bit counter value and the ccrb buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. caution writing to the tq0ccr1 regi ster includes enabling of batch write. thus, rewrite the tq0ccr1 register after rewriting the tq0ccr0 , tq0ccr2, and tq0ccr3 registers. remarks 1. the above flowchart illustrates an example of the operation in the pwm output mode. 2. a = 0 to 3 b = 1 to 3 y = 0, 2, 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 435 figure 9-5. timing of batch write tq0ce bit = 1 16-bit counter tq0ccr0 register tq0ccr1 register tq0ccr2 register tq0ccr3 register intccq0 signal intccq1 signal intccq2 signal intccq3 signal ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 02 d 03 0000h d 11 0000h d 21 d 12 d 21 d 12 0000h d 31 d 32 d 33 d 31 d 32 d 33 d 01 d 02 d 03 d 11 d 12 d 12 d 21 d 31 d 11 d 01 d 21 d 21 d 12 d 12 d 12 d 12 d 32 d 32 d 32 d 02 d 02 d 03 toq0 pin output toq1 pin output toq2 pin output toq3 pin output d 21 d 21 note 1 note 1 same value write 0000h ffffh note 1 note 1 note 1 note 1 note 1 note 1 note 2 note 3 d 21 d 21 notes 1. because the tq0ccr1 register was not rewritten, d 02 is not transferred. 2. because tq0ccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit ti mer and the value of the tq0ccr0 register (d 01 ). 3. because tq0ccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of the 16-bit ti mer and the value of the tq0ccr0 register (d 12 ). remarks 1. d 01 , d 02 , d 03 : setting values of tq0ccr0 register d 11 , d 12 : setting values of tq0ccr1 register d 21 : setting value of tq0ccr2 register d 31 , d 32 , d 33 : setting values of tq0ccr3 register 2. the above flowchart illustrates the operation in the pwm output mode as an example.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 436 9.6.1 interval timer mode (t q0md2 to tq0md0 bits = 000) in the interval timer mode, an interrupt request signal (i ntccq0) is generated at the interval set by the tq0ccr0 register if the tq0ctl0. tq0ce bit is set to 1. a pwm waveform with a duty factor of 50% whose half cycle is equal to the interval can be output from the toq0 pin. the tq0ccr1 to tq0ccr3 registers are not used in the interval timer mode. however, the set value of the tq0ccr1 to tq0ccr3 registers is transferred to the ccr1 to ccr3 buffer registers and, when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 bu ffer registers, compare match interrupt request signals (intccq1 to intccq3) ar e generated. in addition, a pwm waveform with a duty factor of 50%, which is inverted when the intccq1 to intccq3 signals are generated, can be output from the toq1 to toq3 pins. the value of the tq0ccr1 to tq0ccr3 registers c an be rewritten even while the timer is operating. figure 9-6. interval timer configuration 16-bit counter output controller ccr0 buffer register tq0ce bit tq0ccr0 register count clock selection clear match signal toq0 pin intccq0 signal figure 9-7. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq0 pin output intccq0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1)
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 437 when the tq0ce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the toq0 pin is inverted. additionally, the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, the output of the t oq0 pin is inverted, and a compare match interrupt request signal (intccq0) is generated. the interval can be calculated by the following expression. interval = (set value of tq0ccr0 register + 1) count clock cycle figure 9-8. register setting for in terval timer mode operation (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 note 00 tq0ctl1 0, 0, 0: interval timer mode 000 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0: operate on count clock selected by tq0cks0 to tq0cks2 bits 1: count with external event count input signal note the tq0eee bit can be set to 1 only when timer output (toq0, toqb) is used. however, set the tq0ccr0 and tq0ccrb registers to the same value (b = 1 to 3).
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 438 figure 9-8. register setting for in terval timer mode operation (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq0 pin output 1: enable toq0 pin output setting of output level with operation of toq0 pin disabled 0: low level 1: high level 0: disable toq1 pin output 1: enable toq1 pin output setting of output level with operation of toq1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tq0oe1 tq0ol0 tq0oe0 tq0ol1 0: disable toq2 pin output 1: enable toq2 pin output setting of output level with operation of toq2 pin disabled 0: low level 1: high level 0: disable toq3 pin output 1: enable toq3 pin output setting of output level with operation of toq3 pin disabled 0: low level 1: high level tq0oe3 tq0ol2 tq0oe2 tq0ol3 (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 note tq0ioc2 0/1 note 00 tq0ees0 tq0ets1 tq0ets0 tq0ees1 select valid edge of external event count input (evtq pin). note the tq0ees1 and tq0ees0 bits can be set only when timer output (toq0 to toq3) is used. however, set the tq0ccr0 to tq0ccr3 registers to the same value. (e) tmq0 counter read buffer register (tq0cnt) by reading the tq0cnt register, the count va lue of the 16-bit counter can be read. (f) tmq0 capture/compare register 0 (tq0ccr0) if the tq0ccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 439 figure 9-8. register setting for in terval timer mode operation (3/3) (g) tmq0 capture/compare regist ers 1 to 3 (tq0ccr1 to tq0ccr3) the tq0ccr1 to tq0ccr3 registers ar e not used in the interval timer mode. however, the set value of the tq0ccr1 to tq0ccr3 registers are transferred to the ccr1 to ccr3 buffer registers. the compare match interrupt request signals (intccq1 to intccq3) is generated when the count value of the 16-bit counter matches the value of the ccr1 to ccr3 buffer registers. when the tq0ccr1 to tq0ccr3 registers are not us ed, it is recommended to set their values to ffffh. also mask the registers by the interrupt mask flags (p01ic1.p01mk 1 to p01ic3.p01mk3). remark tmq0 i/o control register 1 (tq0ioc1) and tm q0 option register 0 (tq0opt0) are not used in the interval timer mode.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 440 (1) interval timer mode operation flow figure 9-9. software processing flow in interval timer mode tq0ce bit = 1 tq0ce bit = 0 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register note , tq0ccr0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. the output level of the toq0 pin is as specified by the tq0ioc0 register. start stop <1> count operation start flow <2> count operation stop flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq0 pin output intccq0 signal note the tq0ees1 and tq0ees0 bits can be set only when timer output (toq0, toqb) is used. however, set the tq0ccr0 and tq0ccrb registers to the same value (b = 1 to 3).
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 441 (2) interval timer mode operation timing (a) operation if tq0ccr0 re gister is set to 0000h if the tq0ccr0 register is set to 0000h, the intccq 0 signal is generated at each count clock, and the output of the toq0 pin is inverted. the value of the 16-bit counter is always 0000h. count clock 16-bit counter tq0ce bit tq0ccr0 register toq0 pin output intccq0 signal 0000h interval time count clock cycle interval time count clock cycle interval time count clock cycle ffffh 0000h 0000h 0000h 0000h (b) operation if tq0ccr0 re gister is set to ffffh if the tq0ccr0 register is set to ffffh, the 16-bit co unter counts up to ffffh. the counter is cleared to 0000h in synchronization with the next count-up timing . the intccq0 signal is generated and the output of the toq0 pin is inverted. at this time, an over flow interrupt request signal (intovq) is not generated, nor is the overflow flag (tq0opt0.tq0ovf bit) set to 1. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq0 pin output intccq0 signal ffffh interval time 10000h count clock cycle interval time 10000h count clock cycle interval time 10000h count clock cycle
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 442 (c) notes on rewriting tq0ccr0 register if the value of the tq0ccr0 register is rewritten to a smaller value duri ng counting, the 16-bit counter may overflow. when the overflow may occur, stop counting once and then change the set value. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register tq0ol0 bit toq0 pin output intccq0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 l interval time (1) interval time (ng) interval time (2) remark interval time (1): (d 1 + 1) count clock cycle interval time (ng): (10000h + d 2 + 1) count clock cycle interval time (2): (d 2 + 1) count clock cycle if the value of the tq0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tq0ccr0 register has been rewritten. consequently, the value of the 16-bit counter that is compared is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the intccq0 signal is generated and the output of the toq0 pin is inverted. therefore, the intccq0 signal may not be generated at the interval time ?(d 1 + 1) count clock cycle? or ?(d 2 + 1) count clock cycle? originally expected, but may be generated at an interval of ?(10000h + d 2 + 1) count clock period?.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 443 (d) operation of tq0ccr1 to tq0ccr3 registers figure 9-10. configuration of tq0ccr1 to tq0ccr3 registers ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal intccq0 signal toq3 pin intccq3 signal toq0 pin tq0ccr1 register ccr1 buffer register match signal toq1 pin intccq1 signal tq0ccr3 register ccr3 buffer register match signal toq2 pin intccq2 signal tq0ccr2 register ccr2 buffer register match signal output controller count clock selection output controller output controller output controller 16-bit counter
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 444 if the set value of the tq0ccrb regi ster is less than the set value of the tq0ccr0 register, the intccqb signal is generated once per cycle. at the same time, the output of the toqb pin is inverted. the toqb pin outputs a pwm waveform with a duty factor of 50% with the same cycle as that output by the toq0 pin. remark b = 1 to 3 figure 9-11. timing chart when d 01 d b1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq0 pin output intccq0 signal tq0ccr1 register toq1 pin output intccq1 signal tq0ccr2 register toq2 pin output intccq2 signal tq0ccr3 register toq03 pin output intccq3 signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 445 if the set value of the tq0ccrb register is greater than the set value of the tq0ccr0 register, the count value of the 16-bit counter does not match the va lue of the tq0ccrb register. consequently, the intccqb signal is not generated, nor is the output of the toqb pin changed. when the tq0ccrb register is not used, it is recommended to set it s value to ffffh. remark b = 1 to 3 figure 9-12. timing chart when d 01 < d b1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register toq0 pin output intccq0 signal tq0ccr1 register toq1 pin output intccq1 signal tq0ccr2 register toq2 pin output intccq2 signal tq0ccr3 register toq3 pin output intccq3 signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 446 (3) operation by external event count input (evtq) (a) operation to count the 16-bit counter at the valid edge of exte rnal event count input (evtq) in the interval timer mode, the valid edge of the external event count input is necessary once because the 16-bit counter is cleared from ffffh to 0000h immediately afte r the tq0ce bit is set from 0 to 1. when 0001h is set to both the tq0ccr0 and tq0ccrb r egisters, the output of the toq0 and toqb pins is inverted each time the 16-bit counter counts twice (b = 1 to 3). the tq0ctl1.tq0eee bit can be set to 1 in the in terval timer mode only when the timer output (toq0, toqb) is used with the external event count input. tq0ce bit 16-bit counter toq0 pin output tq0ccr0 register toq1 pin output tq0ccr1 register toq2 pin output tq0ccr2 register toq3 pin output tq0ccr3 register ffffh 0000h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h 0001h external event count input (evtq pin input) number of external events: 3 number of external events: 2 number of external events: 2 2-count width 2-count width 2-count width
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 447 9.6.2 external event count mode (tq0md2 to tq0md0 bits = 001) in the external event count mode, the valid edge of the external event count input (evtq) is counted when the tq0ctl0.tq0ce bit is set to 1, and an interrupt request signal (intccq0) is generated each time the specified number of edges set by the tq0ccr0 register have been c ounted. the toq0 to toq3 pins cannot be used. when using the toq0 and toq3 pins for external event count inpu t, set the tq0ctl1.tq0eee bit to 1 in the interval timer mode (see 9.6.1 (3) operation by external event count input (evtq) ). the tq0ccr1 to tq0ccr3 registers are not used in the external event count mode. caution in the external event count mode, the tq0 ccr0 to tq0ccr3 registers must not be cleared to 0000h. figure 9-13. configuration in external event count mode 16-bit counter ccr0 buffer register tq0ce bit tq0ccr0 register edge detector clear match signal intccq0 signal evtq pin (external event count input)
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 448 figure 9-14. basic timing in external event count mode ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal d 0 d 0 d 0 d 0 16-bit counter external event count input (evtq pin input) d 0 external event count: (d 0 ) note external event count: (d 0 + 1) external event count: (d 0 + 1) d 0 - 1 d 0 0000 0001 tq0ccr0 register intccq0 signal note in the external event count mode, when the tq0ctl0.tq0ce bit is set to 1 (operation starts), the 16-bit counter is cleared from ffffh to 0000h at the same time. the first count operation starts from 0001h every time the valid edge of the external event count input is detected. therefore, the count of the firs t count operation is one number sm aller than the count of second or subsequent count operation. caution this figure shows the basic timing when the risi ng edge is specified as the valid edge of the external event count input. when the tq0ce bit is set to 1, the value of the 16-bit count er is cleared from ffffh to 0000h. the counter counts each time the valid edge of external event count input is detec ted. additionally, the set value of the tq0ccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer register, the 16-bit counter is cleared to 0000h, and a compare match interrupt request signal (intccq0) is generated. the intccq0 signal is generated for the first time when t he valid edge of the external event count input has been detected ?value set to tq0ccr0 register? times. after tha t, the intccq0 signal is generated each time the valid edge of the external event count has been detected ?value set to tq0ccr0 register + 1? times.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 449 figure 9-15. register setting for oper ation in external event count mode (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 0: stop counting 1: enable counting 000 tq0cks2 tq0cks1 tq0cks0 tq0ce (b) tmq0 control register 1 (tq0ctl1) 00000 tq0ctl1 0, 0, 1: external event count mode 001 tq0md2 tq0md1 tq0md0 tq0eee tq0est (c) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input (evtq pin) 0/1 0 0 tq0ees0 tq0ees1 tq0ets0 tq0ets1 (d) tmq0 counter read buffer register (tq0cnt) the count value of the 16-bit counter can be read by reading the tq0cnt register. (e) tmq0 capture/compare register 0 (tq0ccr0) if the tq0ccr0 register is set to d 0 , the count is cleared when the number of external events has reached (d 0 ) and the first compare match interrupt request signal (intccq0) is generated. the second compare match interrupt request signal (intccq0) is generated when the number of external events has reached (d 0 + 1). (f) tmq0 capture/compare register s 1 to 3 (tq0ccr1 to tq0ccr3) the tq0ccr1 to tq0ccr3 registers are not used in t he external event count mode. however, the set value of the tq0ccr1 to tq0ccr3 registers are trans ferred to the ccr1 to ccr3 buffer registers. when the count value of the 16-bit counter matches t he value of the ccr1 to ccr3 buffer registers, compare match interrupt request signals (intccq1 to intccq3) are generated. when the tq0ccr1 to tq0ccr3 registers are not us ed, it is recommended to set their values to ffffh. also mask the registers by the interrupt mask flags (p01ic1.p01mk 1 to p01ic3.p01mk3). remark tmq0 i/o control register 0 (tq0ioc0), tmq0 i/o control register 1 (tq0ioc1), and tmq0 option register 0 (tq0opt0) are not used in the external event count mode.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 450 (1) external event count mode operation flow figure 9-16. software processing flow in external event count mode tq0ce bit = 1 tq0ce bit = 0 register initial setting tq0ctl1 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow d 0 d 0 d 0 d 0 <1> <2> ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 451 (2) operation timing in external event count mode cautions 1. in the external event count mode, the tq0ccr0 to tq0ccr3 registers must not be cleared to 0000h. 2. in the external event count mode, use of th e timer output (toq0 to toq3) is disabled. if using timer output (toq0, toqb) with external event count input (evtq), set the interval timer mode, and select the operation enabled by the external event count input for the count clock (tq0ctl1.tq0eee bit = 1) (see 9.6. 1 (3) operation by external event count input (evtq)) (b = 1 to 3). (a) operation if tq0ccr0 re gister is set to ffffh if the tq0ccr0 register is set to ffffh, the 16-bit counter counts to ffffh each time the valid edge of the external event count signal has been detected. the 16-bit counter is cleared to 0000h in synchronization with the next count-up timing, and the intccq0 signal is generated. at this time, the tq0opt0.tq0ovf bit is not set. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal ffffh external event count: ffffh external event count: 10000h external event count: 10000h
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 452 (b) notes on rewriting the tq0ccr0 register if the value of the tq0ccr0 register is rewritten to a smaller value duri ng counting, the 16-bit counter may overflow. when the overflow may occur, stop counting once and then change the set value. ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal d 1 d 2 d 1 d 1 d 2 d 2 d 2 external event count (1) (d 1 ) external event count (ng) (10000h + d 2 + 1) external event count (2) (d 2 + 1) if the value of the tq0ccr0 register is changed from d 1 to d 2 while the count value is greater than d 2 but less than d 1 , the count value is transferred to the ccr0 buff er register as soon as the tq0ccr0 register has been rewritten. consequently, the value t hat is compared with the 16-bit counter is d 2 . because the count value has already exceeded d 2 , however, the 16-bit c ounter counts up to ffffh, overflows, and then counts up again from 0000h. when the count value matches d 2 , the intccq0 signal is generated. therefore, the intccq0 signal may not be generated at the valid edge count of ?(d 1 + 1) times? or ?(d 2 + 1) times? originally expected, but may be ge nerated at the valid edge count of ?(10000h + d 2 + 1) times?.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 453 (c) operation of tq0ccr1 to tq0ccr3 registers figure 9-17. configuration of tq0ccr1 to tq0ccr3 registers ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal intccq0 signal intccq3 signal evtq pin (external event count input) tq0ccr1 register ccr1 buffer register match signal intccq1 signal tq0ccr3 register ccr3 buffer register match signal intccq2 signal tq0ccr2 register ccr2 buffer register match signal 16-bit counter edge detector
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 454 if the set value of the tq0ccrb register is smalle r than the set value of t he tq0ccr0 register, the intccqb signal is gener ated once per cycle. remark b = 1 to 3 figure 9-18. timing chart when d 01 d b1 d 01 d 11 d 21 d 31 d 21 d 11 d 31 d 01 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 d 01 d 21 d 11 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal tq0ccr1 register intccq1 signal tq0ccr2 register intccq2 signal tq0ccr3 register intccq3 signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 455 if the set value of the tq0ccrb register is greate r than the set value of the tq0ccr0 register, the intccqb signal is not generated bec ause the count value of the 16- bit counter and the value of the tq0ccrb register do not match. when the tq0ccrb register is not used, it is recommended to set it s value to ffffh. remark b = 1 to 3 figure 9-19. timing chart when d 01 < d b1 d 01 d 11 d 21 l l l d 31 d 01 d 01 d 01 d 01 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal tq0ccr1 register intccq1 signal tq0ccr2 register intccq2 signal tq0ccr3 register intccq3 signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 456 9.6.3 external trigger pulse output m ode (tq0md2 to tq0md0 bits = 010) in the external trigger pulse output mode, 16-bit ti mer/event counter q waits for a trigger when the tq0ctl0.tq0ce bit is set to 1. when the valid edge of an external trigger input signal (tiq) is detected, 16-bit timer/event counter q starts counting, an d outputs a pwm waveform (up to 3-phase) from the toq1 to toq3 pins. a pwm waveform with a duty factor of 50% whose half cycle is the set value of the tq0ccr0 register + 1 can also be output from the toq0 pin. pulses can also be output by generating a software trigger instead of using the external trigger. figure 9-20. configuration in external trigger pulse output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal intccq0 signal toq3 pin intccq3 signal toq0 pin tiq pin transfer s r tq0ccr1 register ccr1 buffer register match signal toq1 pin intccq1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq2 pin intccq2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count start control edge detector software trigger generation output controller (rs-ff) output controller output controller (rs-ff) output controller evtq pin (external event count input) internal count clock edge detector count clock selection
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 457 figure 9-21. basic timing in exte rnal trigger pulse output mode d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 2 d 3 d 1 d 1 d 2 d 3 d 0 d 1 d 3 d 2 d 0 d 0 d 0 d 0 active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 3 ) active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) wait for trigger active level width (d 3 ) cycle (d 0 + 1) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq pin input) tq0ccr0 register intccq0 signal toq0 pin output tq0ccr1 register intccq1 signal toq1 pin output tq0ccr2 register intccq2 signal toq2 pin output tq0ccr3 register intccq3 signal toq3 pin output active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 )
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 458 16-bit timer/event counter q waits for a trigger when the tq0ce bit is set to 1. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing at the same time, and out puts a pwm waveform from the toqb pin. if the trigger is generated again while the counter is operating, the c ounter is cleared to 0000h and restarted. (the output of the toq0 pin is inverted. the toqb pin outputs a high-level regardless of the status (high/low) when a trigger occurs.) the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tq0ccrb register) count clock cycle cycle = (set value of tq0ccr0 register + 1) count clock cycle duty factor = (set value of tq0ccrb regist er)/(set value of tq0ccr0 register + 1) the compare match request signal intccq 0 is generated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and th e 16-bit counter is cleared to 0000h. the compare match interrupt request signal intccqb is generated when the count value of the 16-bit counter matches the value of the ccrb buffer register. the value set to the tq0ccra register is transferred to t he ccra buffer register when the count value of the 16-bit counter matches the value of the ccr0 buffer regi ster and the 16-bit counter is cleared to 0000h. the valid edge of an external trigger input signal (tiq), or setting the software trigger (tq0ctl1.tq0est bit) to 1 is used as the trigger. remark a = 0 to 3 b = 1 to 3 figure 9-22. setting of registers in exte rnal trigger pulse output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note the setting is invalid when the tq0ctl1.tq0eee bit = 1.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 459 figure 9-22. setting of registers in exte rnal trigger pulse output mode (2/3) (b) tmq0 control register 1 (tq0ctl1) 0 0/1 0/1 0 0 tq0ctl1 0: operate on count clock selected by tq0cks0 to tq0cks2 bits 1: count with external event count input signal generate software trigger when 1 is written 010 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0, 1, 0: external trigger pulse output mode (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq0 pin output 1: enable toq0 pin output setting of output level while operation of toq0 pin is disabled 0: low level 1: high level 0: disable toq1 pin output 1: enable toq1 pin output setting of output level while operation of toq1 pin is disabled 0: low level 1: high level 0/1 0/1 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 toqb pin output 16-bit counter ? when tq0olb bit = 0 toqb pin output 16-bit counter ? when tq0olb bit = 1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of output level while operation of toq3 pin is disabled 0: low level 1: high level 0: disable toq2 pin output 1: enable toq2 pin output setting of output level while operation of toq2 pin is disabled 0: low level 1: high level 0: disable toq3 pin output 1: enable toq3 pin output note clear this bit to 0 when the toq0 pin is not used in the external trigger pulse output mode.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 460 figure 9-22. setting of registers in exte rnal trigger pulse output mode (3/3) (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external trigger input (tiq pin) select valid edge of external event count input (evtq pin) 0/1 0/1 0/1 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if d 0 is set to the tq0ccr0 register, d 1 to the tq0ccr1 register, d 2 to the tq0ccr2 register, and d 3 , to the tq0ccr3 register, the cycle and active level of the pwm waveform are as follows. cycle = (d 0 + 1) count clock cycle toq1 pin pwm waveform active level width = d 1 count clock cycle toq2 pin pwm waveform active level width = d 2 count clock cycle toq3 pin pwm waveform active level width = d 3 count clock cycle remark tmq0 i/o control register 1 (tq0ioc1) and tm q0 option register 0 (tq0opt0) are not used in the external trigger pulse output mode.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 461 (1) operation flow in extern al trigger pulse output mode figure 9-23. software processing flow in ex ternal trigger pulse output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register ccr0 buffer register intccq0 signal toq0 pin output tq0ccr1 register ccr1 buffer register intccq1 signal toq1 pin output tq0ccr2 register ccr2 buffer register intccq2 signal toq2 pin output tq0ccr3 register ccr3 buffer register intccq3 signal toq3 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 11 d 20 d 10 external trigger input (tiq pin input)
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 462 figure 9-23. software processing flow in ex ternal trigger pulse output mode (2/2) start <1> count operation start flow tq0ce bit = 1 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. writing of the tq0ccr1 register must be performed when the set duty factor is only changed after writing the tq0ccr2 and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer register. writing same value (same as preset value of the tq0ccr1 register) to the tq0ccr1 register is necessary only when the set duty factor of the toq2 and toq3 pin outputs is changed. when the counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer register. only writing of the tq0ccr1 register must be performed when the set duty factor of the toq1 is only changed. when counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer register. counting is stopped. the tq0cks0 to tq0cks2 bits can be set at the same time when counting is enabled (tq0ce bit = 1). trigger wait status writing of the tq0ccr1 register must be performed after writing the tq0ccr0, tq0ccr2, and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer registers. writing same value (same as preset value of the tq0ccr1 register) to the tq0ccr1 register is necessary only when the set cycle is changed. <2> tq0ccr0 to tq0ccr3 register setting change flow <3> tq0ccr0 register setting change flow <4> tq0ccr1 to tq0ccr3 register setting change flow <5> tq0ccr2, tq0ccr3 register setting change flow <6> tq0ccr1 register setting change flow <7> count operation stop flow tq0ce bit = 0 setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register stop setting of tq0ccr1 register setting of tq0ccr0 register setting of tq0ccr1 register setting of tq0ccr0, tq0ccr2, and tq0ccr3 registers tq0ccr1 register when the counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer register. remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 463 (2) external trigger pulse output mode operation timing (a) note on changing pulse width during operation to change the pwm waveform while the counter is operating, write the tq0ccr1 register last. rewrite the tq0ccrb register after writing the tq0ccr1 register after the intccq0 signal is detected. remark b = 1 to 3 ffffh 16-bit counter 0000h tq0ce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tq0ccr0 register ccr0 buffer register intccq0 signal tq0ccr1 register ccr1 buffer register intccq1 signal toq1 pin output tq0ccr2 register ccr2 buffer register intccq2 signal toq2 pin output tq0ccr3 register ccr3 buffer register intccq3 signal toq3 pin output toq0 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01 external trigger input (tiq pin input)
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 464 in order to transfer data from the tq0ccra register to the ccra buffer register, the tq0ccr1 register must be written. to change both the cycle and active level width of the pwm waveform at this time, first set the cycle to the tq0ccr0 register, set the active level width to t he tq0ccr2 and tq0ccr3 registers, and then set an active level to the tq0ccr1 register. to change only the cycle of the pwm waveform, first set the cycle to the tq0ccr0 register, and then write the same value (same as preset value of t he tq0ccr1 register) to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform, first set an active level to the tq0ccr2 and tq0ccr3 registers and then set an active level to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toq1 pin, only the tq0ccr1 register has to be set. to change only the active level width (duty facto r) of the pwm waveform output by the toq2 and toq3 pins, first set an active level width to the tq0 ccr2 and tq0ccr3 registers, and then write the same value (same as preset value of the tq0 ccr1 register) to the tq0ccr1 register. after data is written to the tq0ccr1 register, the val ue written to the tq0ccra register is transferred to the ccra buffer register in synchr onization with clearing of the 16-bi t counter, and is used as the value compared with the 16-bit counter. to write the tq0ccr0 to tq0ccr3 registers again afte r writing the tq0ccr1 register once, do so after the intccq0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because timing of transferring data from the tq0ccra register to the ccra buffer register conflicts with writing the tq0ccra register. remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 465 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tq0ccrb register to 0000h. the 16-bit counter is cleared to 0000h and the intccq0 and intccqb signals are generated at the next timing after a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrb register intccq0 signal intccqb signal toqb pin output external trigger input (tiq pin input) d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark b = 1 to 3 to output a 100% waveform, set a value of (set value of tq0ccr0 register + 1) to the tq0ccrb register. if the set value of the tq0ccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrb register intccq0 signal intccqb signal toqb pin output d 0 ? 1d 0 ? 1 external trigger input (tiq pin input) remark b = 1 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 466 (c) conflict between trigger detection and match with ccrb buffer register if the trigger is detected immediately after the in tccqb signal is generated, the 16-bit counter is immediately cleared to 0000h, the output signal of the toqb pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccrb buffer register intccqb signal toqb pin output external trigger input (tiq pin input) d b d b ? 1d b 0000 ffff 0000 shortened remark b = 1 to 3 if the trigger is detected immediately before the int ccqb signal is generated, t he intccqb signal is not generated, and the 16-bit counter is cleared to 0000h and continues counting. the output signal of the toqb pin remains active. consequently, the active period of the pwm waveform is extended. 16-bit counter ccrb buffer register intccqb signal toqb pin output d b d b ? 2d b ? 1d b 0000 ffff 0000 0001 extended external trigger input (tiq pin input) remark b = 1 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 467 (d) conflict between trigger detection and match with ccr0 buffer register if the trigger is detected immediately after the intccq 0 signal is generated, the 16 -bit counter is cleared to 0000h and continues counting up. therefore, the active period of the toqb pin is extended by time from generation of the intccq0 signal to trigger detection. 16-bit counter ccr0 buffer register intccq0 signal toqb pin output d 0 d 0 ? 1d 0 0000 ffff 0000 0000 extended external trigger input (tiq pin input) remark b = 1 to 3 if the trigger is detected immediately before the int ccq0 signal is generated, t he intccq0 signal is not generated. the 16-bit counter is cleared to 0000h, the toqb pin is asserted, and the counter continues counting. consequently, the inactive peri od of the pwm waveform is shortened. 16-bit counter ccr0 buffer register intccq0 signal toqb pin output external trigger input (tiq pin input) d 0 d 0 ? 1d 0 0000 ffff 0000 0001 shortened remark b = 1 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 468 (e) generation timing of compare matc h interrupt request signal (intccqb) the timing of generation of the intccqb signal in the external trigger pulse output mode differs from the timing of intccqb signals in other mode; the intccqb signal is genera ted when the count value of the 16-bit counter matches the value of the ccrb buffer register. count clock 16-bit counter ccrb buffer register toqb pin output intccqb signal d b d b ? 2d b ? 1d b d b + 1 d b + 2 remark b = 1 to 3 usually, the intccqb signal is generated in synchroniza tion with the next count up after the count value of the 16-bit counter matches the value of the ccrb buffer register. in the external trigger pulse output mode, however, it is generated one clock earlier. this is because the timing is changed to match the timing of cha nging the output signal of the toqb pin.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 469 9.6.4 one-shot pulse output mode (tq0md2 to tq0md0 bits = 011) in the one-shot pulse output mode, 16-bit timer/event coun ter q waits for a trigger when the tq0ctl0.tq0ce bit is set to 1. when the valid edge of an external trigger input (tiq) is detected, 16-bit ti mer/event counter q starts counting, and outputs a one-shot pulse from the toq1 to toq3 pins. instead of the external trigger, a software trigger can also be generated to output the puls e. the toq0 pin outputs the active level while the 16-bit counter is counting, and th e inactive level when the counter is stopped (waiting for a trigger). figure 9-24. configuration in one-shot pulse output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal intccq0 signal toq3 pin intccq3 signal toq0 pin tiq pin transfer s r s r tq0ccr1 register ccr1 buffer register match signal toq1 pin intccq1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq2 pin intccq2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count start control edge detector software trigger generation output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) output controller (rs-ff) evtq pin (external event count input) internal count clock edge detector count clock selection
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 470 figure 9-25. basic timing in one-shot pulse output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 1 ) active level width (d 0 ? d 1 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 2 ) active level width (d 0 ? d 2 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) delay (d 3 ) active level width (d 0 ? d 3 + 1) ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq pin input) tq0ccr0 register intccq0 signal toq0 pin output tq0ccr1 register intccq1 signal toq1 pin output tq0ccr2 register intccq2 signal toq2 pin output tq0ccr3 register intccq3 signal toq3 pin output
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 471 when the tq0ce bit is set to 1, 16-bit timer/event counter q waits for a trigger. when the trigger is generated, the 16-bit counter is cleared from ffffh to 0000h, starts count ing, and outputs a one- shot pulse from the toqb pin. after the one-shot pulse is output, the 16- bit counter is set to 0000h, stops count ing, and waits for a trigger. when the trigger is generated again, the 16-bi t counter starts counting from 0000h. if a trigger is generated again while the one-shot pulse is being output, it is ignored. the output delay period and active level width of the one-shot pulse can be calculated as follows. output delay period = (set value of tq0ccrb register) count clock cycle active level width = (set value of tq0ccr0 register ? set value of tq0ccrb register + 1) count clock cycle the compare match interrupt request signal intccq0 is g enerated when the 16-bit counter counts after its count value matches the value of the ccr0 buffer register. the compare match interrupt request signal intccqb is generated when the count value of the 16-bit counter matches the val ue of the ccrb buffer register. the valid edge of an external trigger input (tiq pin) or setting the software trigger (tq0ctl1.tq0est bit) to 1 is used as the trigger. remark b = 1 to 3 figure 9-26. setting of registers in one-shot pulse output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note the setting is invalid when the tq0ctl1.tq0eee bit = 1. (b) tmq0 control register 1 (tq0ctl1) 0 0/1 0/1 0 0 tq0ctl1 0: operate on count clock selected by tq0cks0 to tq0cks2 bits 1: count external event input signal generate software trigger when 1 is written 011 tq0md2 tq0md1 tq0md0 tq0eee tq0est 0, 1, 1: one-shot pulse output mode
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 472 figure 9-26. register setting in one-shot pulse output mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq0 pin output 1: enable toq0 pin output setting of output level while operation of toq0 pin is disabled 0: low level 1: high level 0: disable toq1 pin output 1: enable toq1 pin output setting of output level while operation of toq1 pin is disabled 0: low level 1: high level 0/1 0/1 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of output level while operation of toq3 pin is disabled 0: low level 1: high level 0: disable toq2 pin output 1: enable toq2 pin output setting of output level while operation of toq2 pin is disabled 0: low level 1: high level 0: disable toq3 pin output 1: enable toq3 pin output note clear this bit to 0 when the toq0 pin is not used in the one-shot pulse output mode. toqb pin output 16-bit counter ? when tq0olb bit = 0 toqb pin output 16-bit counter ? when tq0olb bit = 1 (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external trigger input (tiq pin) select valid edge of external event count input (evtq pin) 0/1 0/1 0/1 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 473 figure 9-26. register setting in one-shot pulse output mode (3/3) (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if d 0 is set to the tq0ccr0 register and d b to the tq0ccrb register, the active level width and output delay period of the one-shot pulse are as follows. active level width = (d b ? d 0 + 1) count clock cycle output delay period = d b count clock cycle remarks 1. tmq0i/o control register 1 (tq0ioc1) and tmq0 option register 0 (tq0opt0) are not used in the one-shot pulse output mode. 2. b = 1 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 474 (1) operation flow in one-shot pulse output mode figure 9-27. software processing flow in one-shot pulse output mode (1/2) d 00 d 00 d 11 d 10 d 21 d 20 d 31 d 30 d 10 d 20 d 30 d 11 d 21 d 31 d 00 d 01 <3> <1> <2> ffffh 16-bit counter 0000h tq0ce bit external trigger input (tiq pin input) tq0ccr0 register intccq0 signal toq0 pin output tq0ccr1 register intccq1 signal toq1 pin output tq0ccr2 register intccq2 signal toq2 pin output tq0ccr3 register intccq3 signal toq3 pin output
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 475 figure 9-27. software processing flow in one-shot pulse output mode (2/2) start stop tq0ce bit = 1 tq0ce bit = 0 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). trigger wait status count operation is stopped <1> count operation start flow <2> count operation stop flow setting of tq0ccr0 to tq0ccr3 registers <2> tq0ccr0 to tq0ccr3 register setting change flow as rewriting the tq0ccra register immediately forwards to the ccra buffer register, rewriting immediately after the generation of the intccq0 signal is recommended. remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 476 (2) operation timing in one-shot pulse output mode (a) note on rewriti ng tq0ccra register to change the set value of the tq0ccra register to a smaller value, stop c ounting once, and then change the set value. when the overflow may occur, st op counting once, and then change the set value. d b0 d b1 d 01 d 01 d 00 d b1 d 01 d b0 d b0 d b1 d 00 d 00 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal toq0 pin output tq0ccrb register intccqb signal toqb pin output delay (d b0 ) active level width (d 0 ? d b0 + 1) active level width (d 01 ? d b1 + 1) active level width (d 01 ? d b1 + 1) delay (d b1 ) delay (10000h + d b1 ) external trigger input (tiq pin input) when the tq0ccr0 register is rewritten from d 00 to d 01 and the tq0ccrb register from d b0 to d b1 where d 00 > d 01 and d b0 > d b1 , if the tq0ccrb register is rewritten when the count va lue of the 16-bit counter is greater than d b1 and less than d b0 and if the tq0ccr0 register is rewritten when the count value is greater than d 01 and less than d 00 , each set value is reflected as soon as the register has been rewritten and compared with the count value. the counter counts up to ffffh and then counts up again from 0000h. when the count value matches d b1 , the counter generates the intccqb signal and asserts the toqb pin. when the count value matches d 01 , the counter generates the intccq0 signal, deasserts the toqb pin, and stops counting. therefore, the counter may output a pulse with a delay period or ac tive period different from that of the one-shot pulse that is originally expected. remark a = 0 to 3, b = 1 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 477 (b) generation timing of compare matc h interrupt request signal (intccqb) the generation timing of the int ccqb signal in the one-shot pulse output mode is different from intccqb signals in other mode; the intccqb signal is generated when the count value of the 16-bit counter matches the value of the tq0ccrb register. count clock 16-bit counter tq0ccrb register toqb pin output intccqb signal d b d b ? 2d b ? 1d b d b + 1 d b + 2 remark b = 1 to 3 usually, the intccqb signal is generated when the 16-bit counter counts up next time after its count value matches the value of the tq0ccrb register. in the one-shot pulse output mode, howe ver, it is generated one clock earlier. this is because the timing is changed to match the change timing of the toqb pin.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 478 9.6.5 pwm output mode (tq0md 2 to tq0md0 bits = 100) in the pwm output mode, a pwm waveform is output from the toq1 to toq3 pins when the tq0ctl0.tq0ce bit is set to 1. in addition, a pwm waveform with a duty factor of 50% with the set value of the tq0ccr0 register + 1 as half its cycle is output from the toq0 pin. figure 9-28. configuration in pwm output mode ccr0 buffer register tq0ce bit tq0ccr0 register clear match signal intccq0 signal toq3 pin intccq3 signal toq0 pin transfer s r tq0ccr1 register ccr1 buffer register match signal toq1 pin intccq1 signal transfer transfer s r tq0ccr3 register ccr3 buffer register match signal transfer toq2 pin intccq2 signal s r tq0ccr2 register ccr2 buffer register match signal 16-bit counter count start control output controller (rs-ff) output controller output controller (rs-ff) output controller (rs-ff) evtq pin (external event count input) internal count clock edge detector count clock selection
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 479 figure 9-29. basic timing in pwm output mode d 0 d 1 d 2 d 3 d 1 d 2 d 3 d 0 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 d 0 d 1 d 2 d 3 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal toq0 pin output tq0ccr1 register intccq1 signal toq1 pin output tq0ccr2 register intccq2 signal toq2 pin output tq0ccr3 register intccq3 signal toq3 pin output active level width (d 3 ) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) cycle (d 0 + 1) active level width (d 3 ) active level width (d 3 ) active level width (d 3 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 1 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 ) active level width (d 2 )
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 480 when the tq0ce bit is set to 1, the 16-bit counter is cleared from ffffh to 0000h, starts counting, and outputs pwm waveform from the toqb pin. the active level width, cycle, and duty factor of the pwm waveform can be calculated as follows. active level width = (set value of tq0ccrb register) count clock cycle cycle = (set value of tq0ccr0 register + 1) count clock cycle duty factor = (set value of tq0ccrb regist er)/(set value of tq0ccr0 register + 1) the pwm waveform can be changed by rewriting the tq0ccra register while the counter is operating. the newly written value is reflected when the count value of the 16-bit counter matches the value of the ccr0 buffer register and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal intccq0 is gene rated when the 16-bit counter counts next time after its count value matches the value of the ccr0 buffer register, and the 16-bit counter is cleared to 0000h. the compare match interrupt request signal intccqb is gene rated when the count value of the 16-bit counter matches the value of the ccrb buffer register. remark a = 0 to 3 b = 1 to 3 figure 9-30. setting of registers in pwm output mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note the setting is invalid when the tq0ctl1.tq0eee bit = 1. (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 0 0 tq0ctl1 100 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 0, 0: pwm output mode 0: operate on count clock selected by tq0cks0 to tq0cks2 bits 1: count with external event count input signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 481 figure 9-30. setting of registers in pwm output mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq0 pin output 1: enable toq0 pin output setting of output level while operation of toq0 pin is disabled 0: low level 1: high level 0: disable toq1 pin output 1: enable toq1 pin output setting of output level while operation of toq1 pin is disabled 0: low level 1: high level 0/1 0/1 0/1 note tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of output level while operation of toq3 pin is disabled 0: low level 1: high level 0: disable toq2 pin output 1: enable toq2 pin output setting of output level while operation of toq2 pin is disabled 0: low level 1: high level 0: disable toq3 pin output 1: enable toq3 pin output note clear this bit to 0 when the toq0 pin is not used in the pwm output mode. toqb pin output 16-bit counter ? when tq0olb bit = 0 toqb pin output 16-bit counter ? when tq0olb bit = 1 (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input (evtq pin). 0/1 0 0 tq0ees0 tq0ees1 (e) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 482 figure 9-30. register setting in pwm output mode (3/3) (f) tmq0 capture/compare register s 0 to 3 (tq0ccr0 to tq0ccr3) if d 0 is set to the tq0ccr0 register and d b to the tq0ccrb register, the cycle and active level of the pwm waveform are as follows. pwm waveform cycle = (d 0 + 1) count clock cycle pwm waveform active level width = d b count clock cycle remark tmq0 i/o control register 1 (tq0ioc1) and tm q0 option register 0 (tq0opt0) are not used in the pwm output mode.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 483 (1) operation flow in pwm output mode figure 9-31. software processing flow in pwm output mode (1/2) d 10 d 10 d 10 d 20 d 30 d 00 d 11 d 21 d 01 d 31 d 11 d 21 d 00 d 31 d 20 d 30 d 00 d 21 d 00 d 31 d 11 d 21 d 00 d 31 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register ccr0 buffer register intccq0 signal toq0 pin output tq0ccr1 register ccr1 buffer register intccq1 signal toq1 pin output tq0ccr2 register ccr2 buffer register intccq2 signal toq2 pin output tq0ccr3 register ccr3 buffer register intccq3 signal toq3 pin output d 00 d 01 d 00 d 00 d 01 d 00 d 10 d 11 d 10 d 10 d 11 d 10 d 11 d 10 d 11 d 11 d 20 d 21 d 20 d 21 d 20 d 21 d 21 d 30 d 31 d 30 d 31 d 30 d 31 d 30 d 31 <1> <2> <3> <4> <5> <6> <7> d 11 d 10 d 20
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 484 figure 9-31. software processing flow in pwm output mode (2/2) start <1> count operation start flow tq0ce bit = 1 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0ccr0 to tq0ccr1 registers initial setting of these registers is performed before setting the tq0ce bit to 1. only writing of the tq0ccr1 register must be performed when the set duty factor is only changed after writing the tq0ccr2 and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer register. writing same value (same as preset value of the tq0ccr1 register) to the tq0ccr1 register is necessary only when the set duty factor of toq2 and toq3 pin outputs is changed. when the counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer register. only writing of the tq0ccr1 register must be performed when the set duty factor of toq1 (toqh01) pin is only changed. when counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer register. counting is stopped. the tq0cks0 to tq0cks2 bits can be set at the same time when counting is enabled (tq0ce bit = 1). writing of the tq0ccr1 register must be performed after writing the tq0ccr0, tq0ccr2, and tq0ccr3 registers. when the counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer registers. writing same value (same as preset value of the tq0ccr1 register) to the tq0ccr1 register is necessary only when the set cycle is changed. <2> tq0ccr0 to tq0ccr3 register setting change flow <3> tq0ccr0 register setting change flow <4> tq0ccr1, tq0ccr3 register setting change flow <5> tq0ccr2, tq0ccr3 register setting change flow <6> tq0ccr1 register setting change flow <7> count operation stop flow tq0ce bit = 0 setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register setting of tq0ccr2, tq0ccr3 registers setting of tq0ccr1 register stop setting of tq0ccr1 register setting of tq0ccr0 register setting of tq0ccr1 register setting of tq0ccr0, tq0ccr2, and tq0ccr3 registers tq0ccr1 register when the counter is cleared after setting, the value of the tq0ccra register is transferred to the ccra buffer register. remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 485 (2) pwm output mode operation timing (a) changing pulse width during operation to change the pwm waveform while the counter is operating, write the tq0ccr1 register last. rewrite the tq0ccra register after writing the tq0ccr1 register after the intccq1 signal is detected. ffffh 16-bit counter 0000h tq0ce bit d 30 d 00 d 01 d 30 d 30 d 20 d 20 d 20 d 21 d 11 d 00 d 00 d 31 d 01 d 01 d 21 d 11 d 31 tq0ccr0 register ccr0 buffer register intccq0 signal tq0ccr1 register ccr1 buffer register intccq1 signal toq1 pin output tq0ccr2 register ccr2 buffer register intccq2 signal toq2 pin output tq0ccr3 register ccr3 buffer register intccq3 signal toq3 pin output toq0 pin output d 10 d 10 d 10 d 00 d 11 d 10 d 11 d 10 d 21 d 20 d 21 d 20 d 31 d 30 d 31 d 30 d 00 d 01
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 486 to transfer data from the tq0ccra register to the ccra buffer register, the tq0ccr1 register must be written. to change both the cycle and active level of the pwm waveform at this time, first set the cycle to the tq0ccr0 register, set the active level width to the tq0ccr2 and tq0ccr3 registers, and then set an active level width to the tq0ccr1 register. to change only the cycle of the pwm waveform, first set a cycle to the tq0ccr0 register, and then write the same value (same as preset value of t he tq0ccr1 register) to the tq0ccr1 register. to change only the active level width (duty factor) of pwm wave, first set the active level to the tq0ccr2 and tq0ccr3 registers, and then set an active level to the tq0ccr1 register. to change only the active level width (duty factor) of the pwm waveform output by the toq1 pin, only the tq0ccr1 register has to be set. to change only the active level width (duty facto r) of the pwm waveform output by the toq2 and toq3 pins, first set an active level width to the tq0ccr2 and tq0ccr3 registers, and then write the same value (same as preset value of the tq0 ccr1 register) to the tq0ccr1 register. after the tq0ccr1 register is written, the value wr itten to the tq0ccra register is transferred to the ccra buffer register in synchronization with the ti ming of clearing the 16-bit counter, and is used as a value to be compared with the value of the 16-bit counter. to write the tq0ccr0 to tq0ccr3 registers again a fter writing the tq0ccr1 register once, do so after the intccq0 signal is generated. otherwise, the value of the ccra buffer register may become undefined because the timing of transferring data from the tq0ccra register to the ccra buffer register conflicts with writing the tq0ccra register. remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 487 (b) 0%/100% output of pwm waveform to output a 0% waveform, set the tq0ccrb register to 0000h. the 16-bit counter is cleared to 0000h and the intccq0 and intccqb signals are generated at t he next timing after a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrb register intccq0 signal intccqb signal toqb pin output d 0 l 0000h d 0 0000h d 0 0000h d 0 ? 1d 0 0000 ffff 0000 d 0 ? 1d 0 0000 0001 remark b = 1 to 3 to output a 100% waveform, set a value of (set value of tq0ccr0 register + 1) to the tq0ccrb register. if the set value of the tq0ccr0 register is ffffh, 100% output cannot be produced. d 0 d 0 + 1 d 0 d 0 + 1 d 0 d 0 + 1 d 0 0000 ffff 0000 d 0 0000 0001 count clock 16-bit counter tq0ce bit tq0ccr0 register tq0ccrb register intccq0 signal intccqb signal toqb pin output d 0 ? 1d 0 ? 1 remark b = 1 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 488 (c) generation timing of compare matc h interrupt request signal (intccqb) the timing of generation of the intccqb signal in the pwm output m ode differs from the timing of intccqb signals in other mode; the intccqb signal is generated when the count value of the 16-bit counter matches the value of the tq0ccrb register. count clock 16-bit counter ccrb buffer register toqb pin output intccqb signal d b d b ? 2d b ? 1d b d b + 1 d b + 2 remark b = 1 to 3 usually, the intccqb signal is generated in synchroni zation with the next counting up after the count value of the 16-bit counter matches the value of the tq0ccrb register. in the pwm output mode, however, it is generated one clock earlier. this is because the timing is changed to match the change timing of the output signal of the toqb pin.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 489 9.6.6 free-running timer mode (t q0md2 to tq0md0 bits = 101) the compare function is valid in both tmq0 and tmq1 . the capture function is valid in tmq0 only. in the free-running timer mode, 16-bit timer/event counter q starts counting when the tq 0ctl0.tq0ce bit is set to 1. at this time, the tq0ccra register can be used as a compare register or a capture register, depending on the setting of the tq0opt0.tq0ccsa bit. remark a = 0 to 3 figure 9-32. configuration in free-running timer mode toq3 pin note output toq2 pin note output toq1 pin note output toq0 pin note output intovq signal tq0ccs0, tq0ccs1 bits (capture/compare selection) intccq3 signal intccq2 signal intccq1 signal intccq0 signal intpq3 pin note (capture trigger input) tq0ccr3 register (capture) evtq pin (external event count input) internal count clock tq0ce bit intpq1 pin note (capture trigger input) intpq2 pin note (capture trigger input) tq0ccr0 register (capture) tq0ccr1 register (capture) tq0ccr2 register (capture) tq0ccr3 register (compare) tq0ccr2 register (compare) tq0ccr1 register (compare) 0 1 0 1 0 1 0 1 16-bit counter tq0ccr0 register (compare) output controller output controller output controller output controller count clock selection edge detector edge detector edge detector edge detector edge detector intpq0 pin note (capture trigger input) note because the capture trigger input pin (intpqa) and timer output pin (toqa) are the same alternate- function pin, these functions cannot be used at the same time.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 490 ? compare operation when the tq0ce bit is set to 1, 16-bit timer/event coun ter q starts counting, and the output signals of the toq0 to toq3 pins are inverted. when the count value of the 16-bit counter later matc hes the set value of the tq0ccra register, a compare match interrupt request si gnal (intccqa) is generated, and the output signal of the toqa pin is inverted. the 16-bit counter continues counting in synchronization with the count cl ock. when it counts up to ffffh, it generates an overflow interrupt request signal (intovq) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tq0opt0.tq0ovf bi t) is also set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by ex ecuting the clr instruction via software. the tq0ccra register can be rewritten while the counter is operating. if it is rewritten, the new value is reflected at that time, and compared with the count value. remark a = 0 to 3 figure 9-33. basic timing in free-r unning timer mode (compare function) d 10 d 20 d 30 d 00 d 20 d 31 d 31 d 30 d 00 d 11 d 11 d 21 d 01 d 11 d 21 d 01 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h toq1 pin output tq0ccr2 register intccq2 signal toq2 pin output tq0ccr3 register intccq3 signal toq3 pin output intovq signal tq0ovf bit toq0 pin output tq0ccr1 register intccq1 signal tq0ce bit tq0ccr0 register intccq0 signal d 00 d 01 d 11 d 10 d 21 d 20 d 31 d 30
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 491 ? capture operation when the tq0ce bit is set to 1, the 16-bit counter starts counting. when the valid edge input to the intpqa pin is detected, the count value of the 16-bit counter is stored in the tq 0ccra register, and a capture interrupt request signal (intccqa) is generated. the 16-bit counter continues counting in synchronization with the count cl ock. when it counts up to ffffh, it generates an overflow interrupt request signal (intovq) at the next clock, is cleared to 0000h, and continues counting. at this time, the overflow flag (tq0ovf bit) is al so set to 1. confirm that the overflow flag is set to 1 and then clear it to 0 by executing the clr instruction via software. remark a = 0 to 3 figure 9-34. basic timing in free-r unning timer mode (capture function) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h intpq2 pin input tq0ccr2 register intccq2 signal intpq3 pin input tq0ccr3 register intccq3 signal intovq signal tq0ovf bit intpq1 pin input tq0ccr1 register intccq1 signal tq0ce bit intpq0 pin input tq0ccr0 register intccq0 signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 492 figure 9-35. register setting in free-running timer mode (1/3) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note the setting is invalid when the tq0ctl1.tq0eee bit = 1 (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 0 0 tq0ctl1 101 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 0, 1: free-running mode 0: operate with count clock selected by tq0cks0 to tq0cks2 bits 1: count on external event count input signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 493 figure 9-35. register setting in free-running timer mode (2/3) (c) tmq0 i/o control register 0 (tq0ioc0) 0/1 0/1 0/1 0/1 0/1 tq0ioc0 0: disable toq0 pin output 1: enable toq0 pin output 0: disable toq1 pin output 1: enable toq1 pin output setting of output level with operation of toq1 pin disabled 0: low level 1: high level 0/1 0/1 0/1 tq0oe1 tq0ol0 tq0oe0 tq0ol1 tq0oe3 tq0ol2 tq0oe2 tq0ol3 setting of output level with operation of toq3 pin disabled 0: low level 1: high level 0: disable toq2 pin output 1: enable toq2 pin output setting of output level with operation of toq2 pin disabled 0: low level 1: high level 0: disable toq3 pin output 1: enable toq3 pin output setting of output level with operation of toq0 pin disabled 0: low level 1: high level (d) tmq0 i/o control register 1 (tq0ioc1) 0/1 0/1 0/1 0/1 0/1 tq0ioc1 select valid edge of intpq0 pin input select valid edge of intpq1 pin input 0/1 0/1 0/1 tq0is2 tq0is1 tq0is0 tq0is3 tq0is6 tq0is5 tq0is4 tq0is7 select valid edge of intpq2 pin input select valid edge of intpq3 pin input
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 494 figure 9-35. register setting in free-running timer mode (3/3) (e) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input (evtq pin) 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1 (f) tmq0 option register 0 (tq0opt0) 0/1 0/1 0/1 0/1 0 tq0opt0 overflow flag specifies if tq0ccr0 register functions as capture or compare register 0: compare register 1: capture register specifies if tq0ccr1 register functions as capture or compare register 0: compare register 1: capture register 0 0 0/1 tq0ccs0 tq0ovf tq0ccs1 tq0ccs2 tq0ccs3 specifies if tq0ccr2 register functions as capture or compare register 0: compare register 1: capture register specifies if tq0ccr3 register functions as capture or compare register 0: compare register 1: capture register tq0cms tq0cuf (g) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (h) tmq0 capture/compare regist ers 0 to 3 (tq0ccr0 to tq0ccr3) these registers function as capt ure registers or compare registers depending on the setting of the tq0opt0.tq0ccsa bit. when the registers function as captur e registers, they store the count value of the 16-bit counter when the valid edge input to the intpqa pin is detected. when the registers function as compare registers and when d a is set to the tq0ccra register, the intccqa signal is generated when the counter reaches (d a + 1), and the output signal of the toqa pin is inverted. remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 495 (1) operation flow in free-running timer mode (a) when using capture/compare register as compare register figure 9-36. software processing flow in fr ee-running timer mode (c ompare function) (1/2) d 10 d 20 d 30 d 00 d 10 d 20 d 30 d 00 d 11 d 31 d 01 d 21 d 21 d 11 d 11 d 31 d 01 d 00 d 10 d 20 d 30 d 01 d 11 d 21 d 31 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal toq0 pin output tq0ccr1 register intccq1 signal toq1 pin output tq0ccr2 register intccq2 signal toq2 pin output tq0ccr3 register intccq3 signal toq3 pin output intovq signal tq0ovf bit
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 496 figure 9-36. software processing flow in fr ee-running timer mode (c ompare function) (2/2) tq0ce bit = 1 read tq0opt0 register (check overflow flag). register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc0 register, tq0ioc2 register, tq0opt0 register, tq0ccr0 to tq0ccr3 registers initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). start execute instruction to clear tq0ovf bit (clr tq0ovf). <1> count operation start flow <2> overflow flag clear flow tq0ce bit = 0 counter is initialized and counting is stopped by clearing tq0ce bit to 0. stop <3> count operation stop flow tq0ovf bit = 1 no yes
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 497 (b) when using capture/compare register as capture register figure 9-37. software processing flow in fr ee-running timer mode (c apture function) (1/2) d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 22 d 32 d 03 d 13 d 33 d 23 0000 d 00 d 01 d 02 d 03 0000 0000 0000 0000 0000 d 10 d 11 d 12 d 13 0000 d 20 d 21 d 23 d 22 0000 d 30 d 31 d 32 d 33 cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction <3> <1> <2> <2> <2> ffffh 16-bit counter 0000h tq0ce bit intpq2 pin input tq0ccr2 register intccq2 signal intpq3 pin input tq0ccr3 register intccq signal intovq signal tq0ovf bit intpq1 pin input tq0ccr1 register intccq1 signal intpq0 pin input tq0ccr0 register intccq0 signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 498 figure 9-37. software processing flow in fr ee-running timer mode (c apture function) (2/2) tq0ce bit = 1 read tq0opt0 register (check overflow flag). register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits) tq0ctl1 register, tq0ioc1 register, tq0opt0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). start execute instruction to clear tq0ovf bit (clr tq0ovf). <1> count operation start flow <2> overflow flag clear flow tq0ce bit = 0 counter is initialized and counting is stopped by clearing tq0ce bit to 0. stop <3> count operation stop flow tq0ovf bit = 1 no yes
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 499 (2) operation timing in free-running timer mode (a) interval operation with compare register when 16-bit timer/event counter q is used as an inte rval timer with the tq0ccra register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the intccqa signal has been detected. d 00 d 10 d 20 d 01 d 30 d 12 d 03 d 22 d 31 d 21 d 23 d 02 d 13 ffffh 16-bit counter 0000h tq0ce bit tq0ccr0 register intccq0 signal toq0 pin output tq0ccr1 register intccq1 signal toq1 pin output tqccr2 register intccq2 signal toq2 pin output tq0ccr3 register intccq3 signal toq3 pin output interval period (d 00 + 1) interval period (10000h + d 02 ? d 01 ) interval period (d 01 ? d 00 ) interval period (d 03 ? d 02 ) interval period (d 04 ? d 03 ) d 00 d 01 d 02 d 03 d 04 d 05 interval period (d 10 + 1) interval period (10000h + d 12 ? d 11 ) interval period (d 11 ? d 10 ) interval period (d 13 ? d 12 ) d 10 d 11 d 12 d 13 d 14 interval period (d 20 + 1) interval period (10000h + d 21 ? d 20 ) interval period (10000h + d 23 ? d 22 ) interval period (d 22 ? d 21 ) interval period (d 30 + 1) interval period (10000h + d 31 ? d 30) d 20 d 21 d 22 d 23 d 31 d 30 d 32 d 04 d 11
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 500 when performing an interval operation in the free-running timer mode, two intervals can be set with one channel. to perform the interval operation, the value of the co rresponding tq0ccra register must be re-set in the interrupt servicing that is executed when the intccqa signal is detected. the set value for re-setting the tq0ccra register c an be calculated by the following expression, where ?d a ? is the interval period. compare register default value: d a ? 1 value set to compare register second and subsequent time: previous set value + d a (if the calculation result is greate r than ffffh, subtract 10000h from the result and set this value to the register.) remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 501 (b) pulse width measurement with capture register when pulse width measurement is performed with the tq0ccra register used as a capture register, software processing is necessary for reading the capt ure register each time the intccqa signal has been detected and for calculating an interval. d 20 d 00 d 30 d 10 d 11 d 21 d 31 d 12 d 01 d 02 d 32 d 13 d 03 d 22 d 33 d 23 0000 pulse interval (10000h + d 01 ? d 00 ) pulse interval (10000h + d 02 ? d 01 ) pulse interval (10000h + d 03 ? d 02 ) d 00 d 01 d 02 d 03 pulse interval (d 00 + 1) 0000 pulse interval (10000h + d 11 ? d 10 ) pulse interval (10000h + d 12 ? d 11 ) pulse interval (d 13 ? d 12 ) d 10 d 11 d 12 d 13 pulse interval (d 10 + 1) 0000 pulse interval (10000h + d 21 ? d 20 ) pulse interval (20000h + d 22 ? d 21 ) pulse interval (d 23 ? d 22 ) d 20 d 21 d 23 d 22 pulse interval (d 20 + 1) 0000 pulse interval (10000h + d 31 ? d 30 ) pulse interval (10000h + d 32 ? d 31 ) pulse interval (10000h + d 33 ? d 32 ) d 30 d 31 d 32 d 33 pulse interval (d 30 + 1) cleared to 0 by clr instruction cleared to 0 by clr instruction cleared to 0 by clr instruction ffffh 16-bit counter 0000h tq0ce bit intpq0 pin input tq0ccr0 register intccq0 signal intpq2 pin input tq0ccr2 register intccq2 signal intpq3 pin input tq0ccr3 register intccq3 signal intovq signal tq0ovf bit intpq1 pin input tq0ccr1 register intccq1 signal
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 502 when executing pulse width measurement in the fr ee-running timer mode, four pulse widths can be measured with one channel. to measure a pulse width, the pulse width can be calculated by reading the value of the tq0ccra register in synchronization with t he intccqa signal, and calculating the difference between the read value and the previously read value. remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 503 (c) processing of overflow when two capture registers are used care must be exercised in processing the overflow flag when two capture registers are used. first, an example of incorrect processing is shown below. example of incorrect processing when two capture regi sters are used ffffh 16-bit counter 0000h tq0ce bit intpq0 pin input tq0ccr0 register intpq1 pin input tq0ccr1 register intovq signal tq0ovf bit d 00 d 01 d 10 d 11 d 10 <1> <2> <3> <4> d 00 d 11 d 01 the following problem may occur when two pulse widt hs are measured in the free-running timer mode. <1> read the tq0ccr0 register (setting of t he default value of the intpq0 pin input). <2> read the tq0ccr1 register (setting of t he default value of the intpq1 pin input). <3> read the tq0ccr0 register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <4> read the tq0ccr1 register. read the overflow flag. because the flag is cleared in <3>, 0 is read. because the overflow flag is 0, the pulse width can be calculated by (d 11 ? d 10 ) (incorrect). when two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other capture register may not obtain the correct pulse width. use software when using two capture registers. an example of how to use software is shown below.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 504 (1/2) example when two capture registers are used (usi ng overflow interrupt) ffffh 16-bit counter 0000h tq0ce bit intovq signal tq0ovf bit tq0ovf0 flag note intpq0 pin input tq0ccr0 register tq0ovf1 flag note intpq1 pin input tq0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tq0ovf0 and tq0ovf1 flags are set on the internal ram by software. <1> read the tq0ccr0 register (setting of t he default value of the intpq0 pin input). <2> read the tq0ccr1 register (setting of t he default value of the intpq1 pin input). <3> an overflow occurs. set the tq0ovf0 and tq0ovf1 flags to 1 in the overflow interrupt servicing, and clear the overflow flag to 0. <4> read the tq0ccr0 register. read the tq0ovf0 flag. if the tq0o vf0 flag is 1, clear it to 0. because the tq0ovf0 flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tq0ccr1 register. read the tq0ovf1 flag. if the tq0ovf1 flag is 1, clear it to 0 (the tq0ovf0 flag is cleared in <4>, and the tq0ovf1 flag remains 1). because the tq0ovf1 flag is 1, the puls e width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 505 (2/2) example when two capture re gisters are used (without using overflow interrupt) ffffh 16-bit counter 0000h tq0ce bit intovq signal tq0ovf bit tq0ovf0 flag note intpq0 pin input tq0ccr0 register tq0ovf1 flag note intpq1 pin input tq0ccr1 register d 10 d 11 d 00 d 01 d 10 <1> <2> <5> <6> <3> <4> d 00 d 11 d 01 note the tq0ovf0 and tq0ovf1 flags are set on the internal ram by software. <1> read the tq0ccr0 register (setting of t he default value of the intpq0 pin input). <2> read the tq0ccr1 register (setting of t he default value of the intpq1 pin input). <3> an overflow occurs. nothing is done by software. <4> read the tq0ccr0 register. read the overflow flag. if the overflow flag is 1, set only the tq0ovf1 flag to 1, and clear the overflow flag to 0. because the overflow flag is 1, the pulse width can be calculated by (10000h + d 01 ? d 00 ). <5> read the tq0ccr1 register. read the overflow flag. because the overflow flag is cleared in <4>, 0 is read. read the tq0ovf1 flag. if the tq0o vf1 flag is 1, clear it to 0. because the tq0ovf1 flag is 1, the pulse width can be calculated by (10000h + d 11 ? d 10 ) (correct). <6> same as <3>
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 506 (d) processing of overflow if capture trigger interval is long if the pulse width is greater t han one cycle of the 16-bit counter, ca re must be exercised because an overflow may occur more than once from the first captur e trigger to the next. first, an example of incorrect processing is shown below. example of incorrect processing when capture trigger interval is long ffffh 16-bit counter 0000h tq0ce bit intpqa pin input tq0ccra register intovq signal tq0ovf bit d a0 d a1 d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width the following problem may occur when a long pulse width in the free-running timer mode. <1> read the tq0ccra register (setting of t he default value of the intpqa pin input). <2> an overflow occurs. nothing is done by software. <3> an overflow occurs a second time. nothing is done by software. <4> read the tq0ccra register. read the overflow flag. if the overflow flag is 1, clear it to 0. because the overflow flag is 1, the pul se width can be calculated by (10000h + d a1 ? d a0 ) (incorrect). actually, the pulse width must be (20000h + d a1 ? d a0 ) because an overflow occurs twice. remark a = 0 to 3 if an overflow occurs twice or more when the capture tr igger interval is long, the correct pulse width may not be obtained. if the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use software. an example of how to use software is shown next.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 507 example when capture trigger interval is long ffffh 16-bit counter 0000h tq0ce bit intpqa pin input tq0ccra register intovq signal tq0ovf bit overflow counter note d a0 d a1 1h 0h 2h 0h d a0 d a1 <1> <2> <3> <4> 1 cycle of 16-bit counter pulse width note the overflow counter is set arbitrarily by software on the internal ram. <1> read the tq0ccra register (setting of t he default value of the intpqa pin input). <2> an overflow occurs. increment the overflow count er and clear the overflow flag to 0 in the overflow interrupt servicing. <3> an overflow occurs a second time. increment (+1) the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing. <4> read the tq0ccra register. read the overflow counter. when the overflow counter is ?n?, t he pulse width can be calculated by (n 10000h + d a1 ? d a0 ). in this example, the pulse width is (20000h + d a1 ? d a0 ) because an overflow occurs twice. clear the overflow counter (0h). remark a = 0 to 3 (e) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tq0ovf bit to 0 with the clr instruction after reading the tq0ovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to t he tq0opt0 register after reading the tq0ovf bit when it is 1.
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 508 (3) note on capture operation if the capture operation is used and if a slow clock is selected as the count clock, ffffh, not 0000h, may be captured to the tq0ccra register if the capture trigger is input immedi ately after the tq0ctl0.tq0ce bit is set to 1 (a = 0 to 3). count clock 0000h ffffh tq0ce bit tq0ccr0 register ffffh 0001h 0000h intpq0 pin input capture trigger input 16-bit counter sampling clock capture trigger input
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 509 9.6.7 pulse width measurement mode (tq0md2 to tq0md0 bits = 110) in the pulse width measurement mode, 16-bit timer/even t counter q starts counting when the tq0ctl0.tq0ce bit is set to 1. each time the valid edge input to the intpqa pin has been detected, the count value of the 16-bit counter is stored in the tq0ccra register, and the 16-bit counter is cleared to 0000h. the interval of the valid edge can be measured by readin g the tq0ccra register after a capture interrupt request signal (intccqa) occurs. as shown in figure 9-39, select either of the intpq0 to in tpq3 pins as the capture tri gger input pin. specify ?no edge detection? by using the tq0ioc1 register for the unused pins. remark a = 0 to 3 figure 9-38. configuration in pulse width measurement mode intovq signal intccq0 signal intccq1 signal intccq2 signal intccq3 signal intpq3 pin (capture trigger input) tq0ccr3 register (capture) evtq pin (external event count input) internal count clock tq0ce bit intpq1 pin (capture trigger input) intpq2 pin (capture trigger input) tq0ccr0 register (capture) tq0ccr1 register (capture) tq0ccr2 register (capture) 16-bit counter clear edge detector edge detector edge detector edge detector edge detector count clock selection intpq0 pin (capture trigger input)
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 510 figure 9-39. basic timing in pulse width measurement mode ffffh 16-bit counter 0000h tq0ce bit intpqa pin input tq0ccra register intccqa signal intovq signal tq0ovf bit d 0 0000h d 1 d 2 d 3 cleared to 0 by clr instruction remark a = 0 to 3 when the tq0ce bit is set to 1, the 16-bit counter starts co unting. when the valid edge input to the intpqa pin is later detected, the count value of the 16-bit counter is stored in the tq0ccra register, the 16-bit counter is cleared to 0000h, and a capture interrupt request signal (intccqa) is generated. the pulse width is calculated as follows. pulse width = d n count clock cycle if the valid edge is not input to t he tiq0m pin even when the 16-bit counter counted up to ffffh, an overflow interrupt request signal (intovq) is generated at the next c ount clock, and the counter is cleared to 0000h and continues counting. at this time, the overflow flag (tq0opt0.t q0ovf bit) is also set to 1. clear the overflow flag to 0 by executing the clr instruction via software. if the overflow flag is set to 1, the pu lse width can be calculated as follows. pulse width = (10000h tq0ovf bit set (1) count + d n ) count clock cycle remark a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 511 figure 9-40. register setting in pu lse width measurement mode (1/2) (a) tmq0 control register 0 (tq0ctl0) 0/1 0 0 0 0 tq0ctl0 select count clock note 0: stop counting 1: enable counting 0/1 0/1 0/1 tq0cks2 tq0cks1 tq0cks0 tq0ce note setting is invalid when the tq0ctl1.tq0eee bit = 1. (b) tmq0 control register 1 (tq0ctl1) 0 0 0/1 0 0 tq0ctl1 110 tq0md2 tq0md1 tq0md0 tq0eee tq0est 1, 1, 0: pulse width measurement mode 0: operate with count clock selected by tq0cks0 to tq0cks2 bits 1: count external event count input signal (c) tmq0 i/o control register 1 (tq0ioc1) 0/1 0/1 0/1 0/1 0/1 tq0ioc1 select valid edge of intpq0 pin input select valid edge of intpq1 pin input 0/1 0/1 0/1 tq0is2 tq0is1 tq0is0 tq0is3 tq0is6 tq0is5 tq0is4 tq0is7 select valid edge of intpq2 pin input select valid edge of intpq3 pin input (d) tmq0 i/o control register 2 (tq0ioc2) 0 0 0 0 0/1 tq0ioc2 select valid edge of external event count input (evtq pin) 0/1 0 0 tq0ees0 tq0ets1 tq0ets0 tq0ees1
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 512 figure 9-40. register setting in pu lse width measurement mode (2/2) (e) tmq0 option register 0 (tq0opt0) 00000 tq0opt0 overflow flag 0 0 0/1 tq0ccs0 tq0ovf tq0ccs1 tq0ccs2 tq0ccs3 (f) tmq0 counter read buffer register (tq0cnt) the value of the 16-bit counter can be read by reading the tq0cnt register. (g) tmq0 capture/compare regist ers 0 to 3 (tq0ccr0 to tq0ccr3) these registers store the count valu e of the 16-bit counter when the va lid edge input to the intpqa pin is detected. remarks 1. tmq0 i/o control register 0 (tq0ioc0) is not used in the pulse width measurement mode. 2. a = 0 to 3
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 513 (1) operation flow in pul se width measurement mode figure 9-41. software processing flow in pulse width measurement mode tq0ce bit = 1 tq0ce bit = 0 register initial setting tq0ctl0 register (tq0cks0 to tq0cks2 bits), tq0ctl1 register, tq0ioc1 register, tq0ioc2 register, tq0opt0 register initial setting of these registers is performed before setting the tq0ce bit to 1. the tq0cks0 to tq0cks2 bits can be set at the same time when counting has been started (tq0ce bit = 1). the counter is initialized and counting is stopped by clearing the tq0ce bit to 0. start stop <1> count operation start flow <2> count operation stop flow <1> <2> ffffh 16-bit counter 0000h tq0ce bit intpq0 pin input tq0ccr0 register intccq0 signal d 0 0000h 0000h d 1 d 2
chapter 9 16-bit timer/event counter q (tmq) user?s manual u16397ej3v0ud 514 (2) operation timing in pul se width measurement mode (a) clearing overflow flag the overflow flag can be cleared to 0 by clearing th e tq0ovf bit to 0 with the clr instruction after reading the tq0ovf bit when it is 1 and by writing 8-bi t data (bit 0 is 0) to t he tq0opt0 register after reading the tq0ovf bit when it is 1. (3) note if a slow clock is selected as the count clock, ffffh, not 0000h, may be captured to the tq0ccra register if the capture trigger is input immediately after t he tq0ctl0.tq0ce bit is set to 1 (a = 0 to 3). 0000h ffffh ffffh 0002h 0000h capture trigger input capture trigger input count clock tq0ce bit tq0ccr0 register intpq0 pin input 16-bit counter sampling clock
user?s manual u16397ej3v0ud 515 chapter 10 16-bit interval timer d (tmd) timer d (tmd) is a 16-bit interval timer. the v850e/ma3 incorporates tmd0 to tmd3. 10.1 features tmd functions as a 16-bit interval timer. 10.2 function overview ? 16-bit interval timer: 4 channels ? compare registers: 4 ? interrupt request sources: 4 ? count clock selected from division of peripheral clock
chapter 10 16-bit interval timer d (tmd) user?s manual u16397ej3v0ud 516 10.3 configuration table 10-1. timer d configuration timer count clock register read/write generated interrupt signal capture trigger timer output s/r other functions tmd0 read ? ? ? ? cmd0 read/write intcmd0 ? ? ? tmd1 read ? ? ? ? cmd1 read/write intcmd1 ? ? ? tmd2 read ? ? ? ? cmd2 read/write intcmd2 ? ? output trigger in d/a real-time output mode tmd3 read ? ? ? ? timer d f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, f xx /512 cmd3 read/write intcmd3 ? ? output trigger in d/a real-time output mode remark f xx : peripheral clock s/r: set/reset figure 10-1. time r d block diagram tmdn (16 bits) cmdn intcmdn 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 f xx /2 clear & start remarks 1. n = 0 to 3 2. f xx : peripheral clock
chapter 10 16-bit interval timer d (tmd) user?s manual u16397ej3v0ud 517 10.3.1 timers d0 to d3 (tmd0 to tmd3) the tmdn register is a 16-bit timer. it is mainly used as an interval timer for software (n = 0 to 3). starting and stopping the tmdn register is cont rolled by the tmcdn.tmdcen bit (n = 0 to 3). division by the prescaler can be sele cted for the count clock from among f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256, and f xx /512 by the tmcdn.csn0 to tmcdn.csn2 bits (f xx : peripheral clock). the tmdn register is read-only, in 16-bit units. reset input clears these registers to 0000h. tmdn (n = 0 to 3) 654321 after reset: 0000h r address: tmd0 fffff540h, tmd1 fffff550h, tmd2 fffff560h, tmd3 fffff570h 70 14 13 12 11 10 9 15 8 the conditions for which the tmdn register becomes 0000h are shown below (n = 0 to 3). ? reset input ? tmcdn.tmdcaen bit = 0 ? tmcdn.tmdcen bit = 0 ? match of tmdn register and cmdn register ? overflow cautions 1. if the tmdcaen bit is cleared (0), a reset is performed asynchronously. 2. if the tmdcen bit is cleared (0), a reset is performed, in synchroni zation with the peripheral clock. similarly, a synchroni zed reset is performed after a match with the cmdn register and after an overflow. 3. the count clock must not be changed during a ti mer operation. if it is to be overwritten, it should be overwritten after th e tmdcen bit is cleared (0). 4. up to 4 peripheral clocks are required after a value is set in the tmdcen bit until the set value is transferred to intern al units. when a count operation begins, the count cycle from 0000h to 0001h differs from subsequent cycles. 5. after a compare match is gene rated, the timer is cleared at th e next count clock. therefore, if the division ratio is large, the timer value may not be zero e ven if the timer value is read immediately after a match interrupt is generated. 6. to initialize the status of the tmdn register and start counting again, set the tmdcen bit to 1 after the lapse of 4 peripheral clocks.
chapter 10 16-bit interval timer d (tmd) user?s manual u16397ej3v0ud 518 10.3.2 compare registers d0 to d3 (cmd0 to cmd3) the cmdn register and the tmdn regi ster count value are compared, and an interrupt request signal (intcmdn) is generated when a match occurs. the tmdn register is cleared, in synchronization with this match. if the tmcdn.tmdcaen bit is set to 0, a reset is performed asyn chronously, and the registers are initialized (n = 0 to 3). the cmdn registers are configured usin g a master/slave configuration. when a cmdn register is written, data is first written to the master register and t hen the master register data is transferr ed to the slave register. in a compare operation, the slave register value is compared with the count value of the tmdn register. when a cmdn register is read, data from the master side is read out. the cmdn register can be read or written in 16-bit units. reset input clears these registers to 0000h. cautions 1. a write operation to a cmdn register re quires 4 peripheral clocks until the value that was set in the cmdn register is transferred to internal units. when writing continuously to the cmdn register, be sure to reserve a time in terval of at least 4 peripheral clocks. 2. the cmdn register can be overwritten only once in a single tmdn regi ster cycle (from 0000h until an intcmdn signal is gene rated due to a match of the tmdn register and cmdn register). if this cannot be se cured by the application, make su re that the cmdn register is not overwritten during timer operation. 3. note that the intcmdn signa l will be generated after an over flow if a value less than the counter value is written to the cmdn register during tmdn register operation (see figure 10- 2). cmdn (n = 0 to 3) 654321 after reset: 0000h r/w address: cmd0 fffff542h, cmd1 fffff552h, cmd2 fffff562h, cmd3 fffff572h 70 14 13 12 11 10 9 15 8
chapter 10 16-bit interval timer d (tmd) user?s manual u16397ej3v0ud 519 figure 10-2. example of ti ming during tmdn operation (a) when tmdn < cmdn tmdn tmdcaen bit tmdcen bit cmdn register intcmdn signal mn n n remarks 1. m = tmdn value when overwritten n = cmdn register value when overwritten m < n 2. n = 0 to 3 (b) when tmdn > cmdn tmdn tmdcaen bit tmdcen bit cmdn register intcmdn signal m ffffh n n n remarks 1. m = tmdn value when overwritten n = cmdn register value when overwritten m > n 2. n = 0 to 3
chapter 10 16-bit interval timer d (tmd) user?s manual u16397ej3v0ud 520 10.4 control registers (1) timer mode control register s d0 to d3 (tmcd0 to tmcd3) the tmcdn registers control the operation of timer dn (n = 0 to 3). these registers can be read or wr itten in 8-bit or 1-bit units. reset input clears these registers to 00h. caution tmdcaen and other bits cannot be set at the same time. the other bits and the registers of the other tmdn units should always be set after the tmdcaen bit has been set. 0 count disabled (stops at 0000h and does not operate) counting operation is performed tmdcen 0 1 timer dn operation control tmcdn (n = 0 to 3) csn2 csn1 csn0 0 0 tmdcen tmdcaen 65432<1> after reset: 00h r/w address: tmcd0 fffff544h, tmcd1 fffff554h, tmcd2 fffff564h, tmcd3 fffff574h the tmdcen bit is not cleared even if a match is detected by the compare operation. to stop the count operation, clear the tmdcen bit. the csn2 to csn0 bits must not be changed during timer operation. if they are to be changed, they must be changed after clearing the tmdcen bit to 0. if these bits are overwritten during timer operation, operation cannot be guaranteed. the entire tmdn unit is reset asynchronously. the supply of input clocks to the tmdn unit stops. clocks are supplied to the tmdn unit tmdcaen 0 1 count clock control ? when the tmdcaen bit is set to 0, the tmdn unit can be asynchronously reset. ? when the tmdcaen bit is set to 0, the tmdn unit is in a reset state. therefore, to operate tmdn, the tmdcaen bit must be set to 1. ? if the tmdcaen bit is cleared to 0, all the registers of the tmdn unit are initialized. if tmdcaen bit is set to 1 again, be sure to set all the registers of the tmdn unit again. 7 <0> f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 csn2 0 0 0 0 1 1 1 1 internal count clock selection csn1 0 0 1 1 0 0 1 1 csn0 0 1 0 1 0 1 0 1 remark f xx : peripheral clock
chapter 10 16-bit interval timer d (tmd) user?s manual u16397ej3v0ud 521 10.5 operation 10.5.1 compare operation timer dn can be used for a compare operation in which t he value that was set in a compare register (cmdn) is compared with the count valu e of the tmdn register. if a match is detected by the compar e operation, an interrupt request si gnal (intcmdn) is generated. the generation of the interrupt request signal causes the tmdn re gister to be cleared (0) at the next count timing. this function enables timer d to be used as an interval timer. the cmdn register can also be set to 0. in this case, when an overflow occurs and the tmdn register becomes 0, a match is detected and the intcmdn signal is generated. although the value of the tmdn register is cleared (0) at the next count timing, the intcmdn signal is not generated by this match. remark n = 0 to 3 figure 10-3. tmd0 compare operation example (1/2) (a) when cmd0 register is set to n (non-zero) 1 0 n n tmd0 count clock cmd0 register tmd0 clear match detected (intcmd0) count up clear remark interval time = (n + 1) (count clock cycle) n = 1 to 65,536 (ffffh)
chapter 10 16-bit interval timer d (tmd) user?s manual u16397ej3v0ud 522 figure 10-3. tmd0 compare operation example (2/2) (b) when cmd0 register is set to 0 1 0 0 0 ffffh overflow tmd0 count clock cmd0 register tmd0 clear match detected (intcmd0) count up clear remark interval time = (ffffh + 2) (count clock cycle)
chapter 10 16-bit interval timer d (tmd) user?s manual u16397ej3v0ud 523 10.6 application examples (1) interval timer this section explains an example in which timer d is used as an interval timer with 16-bit precision. interrupt request signals (intcmdn) are output at equal intervals (see figure 10-3 tmd0 compare operation example ). the setup procedure is shown below (n = 0 to 3). <1> set (1) the tmcdn.tmdcaen bit. <2> set each register. ? select the count clock using the tmcdn.csn0 to tmcdn.csn2 bits. ? set the compare value in the cmdn register. <3> start counting by setting (1) the tmcdn.tmdcen bit. <4> if the tmdn register and cmdn register va lues match, an intcmdn signal is generated. <5> intcmdn signals are generated thereafter at the same interval. remark n = 0 to 3 10.7 cautions various cautions concerning timer d are shown below. (1) to operate tmdn, first set (1) the tmcdn.tmdcaen bit. (2) up to 4 peripheral clocks are required after a value is set to the tmcdn.tmdcen bit until the set value is transferred to internal units. when a count operation begi ns, the count cycle from 0000h to 0001h differs from subsequent cycles. (3) to initialize the tmdn register status and start counting again, clear (0) the tmdcen bit and then set (1) the tmdcen bit after an interval of 4 peripheral clocks has elapsed. (4) up to 4 peripheral clocks are required until the value that was set to the cmdn register is transferred to internal units. when writing continuously to the cmdn register, be sure to secure a time interval of at least 4 peripheral clocks. (5) the cmdn register can be ov erwritten only once during a timer/c ounter operation (from 0000h until an intcmdn signal is generated due to a match of the tmdn register and cmdn register). if this cannot be secured, make sure that the cmdn register is not overwritten during a ti mer/counter operation. (6) the count clock must not be changed during a timer o peration. if it is to be overwritten, it should be overwritten after the tmdcen bit is cleared (0). if t he count clock is overwritten during a timer operation, operation cannot be guaranteed. (7) the intcmdn signal will be generated after an overflow if a value less than the counter value is written to the cmdn register during tmdn register operation. remark n = 0 to 3
user?s manual u16397ej3v0ud 524 chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) timer enc1 (tmenc1) is a 16-bit 2-phase encoder input up/down counter general-purpose timer. the v850e/ma3 incorporates tmenc10. 11.1 functions timer enc1 (tmenc1) has the following functions. ? general-purpose timer mode (see 11.5.1 operation in general-purpose timer mode ) free-running timer timer output ? up/down counter mode (see 11.5.2 operation in udc mode ) udc mode a (mode 1, mode 2, mode 3, mode 4) udc mode b (mode 1, mode 2, mode 3, mode 4) 11.2 features ? 16-bit 2-phase encoder input up/down counter general-purpose timer: 1 channel ? compare registers: 2 ? capture/compare registers: 2 ? interrupt request sources ? capture/compare match interrupt request: 2 ? compare match interrupt request: 2 ? capture request signal: 2 types ? the tmenc10 value can be latched using the valid edge of the intp10 and intp11 pins corresponding to the capture/compare register as the capture trigger. ? count clock selectable through division by prescaler (s et the frequency of the count clock to 10 mhz or less) ? timer output function in the general-purpose timer mode, 16-bit resolution timer can be output from the to10 pin. ? timer clear the following timer clear operations are perfo rmed according to the mode that is used. (a) general-purpose timer mode: timer clear operati on is possible upon occurrence of match with cm100 register set value. (b) up/down counter mode: the timer clear operation can be selected from among the following four conditions. (i) timer clear performed upon occurrence of match with cm100 register set value during tmenc10 count-up operation, and timer clear performed upon occurrence of match with cm101 register set value during tmenc10 count-down operation. (ii) timer clear performed only by external input. (iii) timer clear performed upon occurrence of matc h between tmenc10 count value and cm100 register set value. (iv) timer clear performed upon occurrence of external input and match between tmenc10 count value and cm100 register set value. ? external pulse output (to10): 1
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 525 11.3 configuration the basic configuration is shown below. table 11-1. timer enc1 configuration timer count clock register read/write generated interrupt request signal capture trigger tmenc10 read/write ? ? cm100 read/write intcm100 ? cm101 read/write intcm101 ? cc100 read/write intcc100 intp10 timer enc1 f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256 cc101 read/write intcc101 intp11 remark f xx : peripheral clock figure 11-1 shows the block diagram of timer enc1. figure 11-1. block di agram of timer enc1 clock division & selector output control selector selector edge detector/ noise eliminator edge detector/ noise eliminator edge detector/ noise eliminator edge detector/ noise eliminator clock control edge detector/ noise eliminator cm101 cm100 tmenc10 tmenc10 clear controller cc101 cc100 clear internal bus internal bus tclr10/ intp11 f xx /2 tcud10/ intp10 tiud10 sampling clock f xx 3 intcc100 intcc101 to10 intcm100 intcm101 remark f xx : peripheral clock
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 526 (1) timer enc10 (tmenc10) tmenc10 is a general-purpose timer (in general-pur pose mode) and 2-phase encoder input up/down counter (in udc mode). this timer counts up in the general-purpose oper ation mode and counts up/down in the udc mode. this register can be read or written in 16-bit units. reset input clears this register to 0000h. cautions 1. writing to tmenc10 is enabled only when the tmc10.ce101 bit is 0 (count operation disabled). 2. continuous reading of tmenc10 is prohib ited. if tmenc10 is continuously read, the second read value may differ from the actual value. if tmenc 10 must be read twice, be sure to read another register between the first and the second read operation. 3. writing the same value to the tmenc10, cc100, and cc101 registers, and the status10 register is prohibited. writing the same value to the ccr10, tum10, tmc10, sesa 10, and prm10 registers, and cm100 and cm101 registers is permitted (w riting the same value is guaranteed even during a count operation). tmenc10 654321 after reset: 0000h r/w address: fffff5c0h 70 14 13 12 11 10 9 15 8 tmenc10 start and stop is controlled by the tmc10.ce101 bit. the tmenc10 operation consists of the following two modes. (a) general-purpose timer mode in the general-purpose timer mode, tmenc10 operates as a 16-bit interval timer, free-running timer, or timer output. counting is performed based on the clock selected by so ftware. division by the prescaler can be selected for the count clock from among f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, or f xx /256, using the prm10.prm102 to prm10.prm100 bits (f xx : peripheral clock). (b) up/down counter mode (udc mode) in the udc mode, tmenc10 functions as a 16-bit up/do wn counter that performs counting based on the tcud10 and tiud10 input signals. this mode is divided into the udc a mode and udc b mode, depending on the condition of clearing tmenc10. cautions 1. tcud10 and intp10 are alternate-func tion pins. therefore, when the tcud10 pin is used in the udc mode, the external capture func tion of the intp10 pin cannot be used. 2. tclr10 and intp11 are alternate-function pins. therefore, when the tclr10 input is used in udc mode a, the external capture function of the intp11 pin cannot be used.
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 527 the conditions for clearing tmenc10 are as follows, according to the operation mode. table 11-2. clear conditions of timer enc1 (tmenc10) tum10 register tmc10 register operation mode t1cmd0 bit msel0 bit enmd10 bit clr101 bit clr100 bit tmenc10 clear 0 clearing not performed (free-running timer) general-purpose timer mode 0 0 1 cleared upon match with cm100 register set value 0 0 cleared only by tclr10 input 0 1 cleared upon match with cm100 register set value during count-up operation 1 0 cleared by tclr10 input or upon match with cm100 register set value during count-up operation udc mode a 1 0 1 1 clearing not performed udc mode b 1 1 cleared upon match with cm100 register set value during count-up operation or upon match with cm101 register set value during count-down operation other than above setting prohibited remark : indicates that the set value of that bit is ignored.
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 528 11.4 control registers (1) timer unit mode register 10 (tum10) the tum10 register is an 8-bit register used to s pecify the tmenc10 operatio n mode or to control the operation of the timer output pin. this register can be read or written in 8-bit units. reset input clears this register to 00h. cautions 1. changing the value of the tum10 regi ster during tmenc10 operation (tmc10.ce101 bit = 1) is prohibited. 2. when the t1cmd0 bit = 0 (general-purpo se timer mode), setting msel0 = 1 (udc mode b) is prohibited. t1cmd0 general-purpose timer mode (count-up) udc mode (count-up/-down) t1cmd0 0 1 tmenc10 operation mode specification tum10 0 0 0 toe100 alvt100 0 msel0 654321 after reset: 00h r/w address: fffff5cbh timer output disabled timer output enabled toe100 0 1 specification of timer output (to10) enable when t1cmd0 bit = 1 (udc mode), timer output is not performed regardless of the setting of the toe100 bit. at this time, timer output is the inverted phase level of the level set by the alvt100 bit. active level is high level active level is low level alvt100 0 1 specification of timer output (to10) active level when t1cmd0 bit = 1 (udc mode), timer output is not performed regardless of the setting of the toe100 bit. at this time, timer output is the inverted phase level of the level set by the alvt100 bit. when udc mode b is set, the tmc10.enmd10, tmc10.clr101, and tmc10.clr100 bits become invalid. udc mode a tmenc10 can be cleared by setting the tmc10.clr101 and tmc10.clr100 bits. udc mode b tmenc10 is cleared in the following cases. ? upon match with cm100 register during tmenc10 count-up operation ? upon match with cm101 register during tmenc10 count-down operation msel0 0 1 specification of operation in udc mode (count-up/-down) 7 0
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 529 (2) timer control register 10 (tmc10) the tmc10 register is used to enable/disable tmen c10 operation and to set transfer and timer clear operations. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution changing the values of th e tmc10 register bits other th an the ce101 bit during tmenc10 operation (ce101 = 1) is prohibited. 0 count operation disabled count operation enabled ce101 0 1 tmenc10 operation control tmc10 ce101 clr100 0 1 0 1 0 0 rlen10 enmd10 clr101 clr100 <6>54 32 1 after reset: 00h r/w address: fffff5cch transfer operation disabled transfer operation enabled rlen10 0 1 specification of transfer operation from cm100 register to tmenc10 ? when rlen10 = 1, the value set to cm100 register is transferred to tmenc10 upon occurrence of a tmenc10 underflow. ? the rlen10 bit is valid only in udc mode a (tum10.t1cmd0 bit = 1, msel0 bit = 0). in the general-purpose timer mode (t1cmd0 bit = 0) and in udc mode b (t1cmd0 bit = 1, msel0 bit =1), a transfer operation is not performed even if the rlen10 bit is set (1). cleared only by external input (tclr10) cleared upon match of tmenc10 count value and cm100 register set value cleared by tclr10 input or upon match of tmenc10 count value and cm100 register set value not cleared clr101 0 0 1 1 tmenc10 clear source specification clear disabled (free-running mode) clearing is not performed even when tmenc10 and cm100 register values match. clear enabled clearing is performed when tmenc10 and cm100 register values match. enmd10 0 1 control of tmenc10 clear operation in general-purpose timer mode when in the udc mode (tum10.t1cmd0 bit) = 1, the enmd10 bit setting becomes invalid. ? clearing by match of the tmenc10 count value and cm100 register set value is valid only during a tmenc10 count-up operation (tmenc10 is not cleared during a tmenc10 count-down operation). ? when in the general-purpose timer mode (tum10.t1cmd0 bit = 0), the clr101 and clr100 bit settings are invalid. ? when in the udc mode b (tum10.msel0 bit = 1), the clr101 and clr100 bit settings are invalid. ? when clearing by tclr10 has been enabled by bits clr101 and clr100, clearing is performed regardless of whether the value of the ce101 bit is 1 or 0. 7 0
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 530 (3) capture/compare control register 10 (ccr10) the ccr10 register specifie s the operation mode of the cc100 and cc101 registers. this register can be read or written in 8-bit units. reset input clears this register to 00h. cautions 1. overwriting the ccr10 register dur ing tmenc10 operation (tmc10.ce101 bit = 1) is prohibited. 2. tcud10 and intp10 are alternate-function pi ns. therefore, when the tcud10 pin is used in the udc mode, the external capture func tion of the intp10 pin cannot be used. 3. tclr10 and intp11 are alternate-function pins. therefore, when the tclr10 input is used in udc mode a, the external capture function of the intp11 pin cannot be used. 0 operates as capture register operates as compare register cms01 0 1 cc101 register operation mode specification ccr10 0 0 0 0 0 cms01 cms00 654321 operates as capture register operates as compare register cms00 0 1 cc100 register operation mode specification after reset: 00h r/w address: fffff5cah 7 0 (4) valid edge select re gister 10 (sesa10) the sesa10 register is used to specif y the valid edge of external interru pt request signals (intp10, intp11, tiud10, tcud10, tclr10) from the external pins. the valid edge (rising edge, falling edge, or both edges ) can be specified independently for each pin. this register can be read or written in 8-bit units. reset input clears this register to 00h. cautions 1. changing the values of the sesa 10 register bits dur ing tmenc10 operation (tmc10.ce101 = 1) is prohibited. 2. before setting the trigger mode of th e intp10, intp11, tiud10, tcud10, and tclr10 pins, set the pmc0 and pmc2 registers. if the pmc0 and pmc2 registers are set after the sesa10 register has been set, an illegal inte rrupt, incorrect counting, and incorrect clearing may occur, depending on the timing of setting the pmc0 and pmc2 registers.
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 531 tesud01 tiud10, tcud10 tclr10 intp11 intp10 sesa10 tesud00 tesud00 0 1 0 1 cesud01cesud00 ies101 ies100 ies001 ies000 654321 after reset: 00h r/w address: fffff5cdh falling edge rising edge setting prohibited both rising and falling edges tesud01 0 0 1 1 specification of valid edge of tiud10 and tcud10 pins ? the setting of the tesud01 and tesud00 bits is valid only in udc mode a and udc mode b. ? if mode 4 is specified as the operation mode of tmenc10 (specified by the prm10.prm102 to prm10.prm100 bits), the valid edge specifications for the tiud10 and tcud10 pins (tesud01 and tesud00 bits) are not valid. ies100 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges ies101 0 0 1 1 specification of valid edge of intp11 pin ies000 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges ies001 0 0 1 1 specification of valid edge of intp10 pin cesud00 0 1 0 1 falling edge (tmenc10 cleared after edge detection) rising edge (tmenc10 cleared after edge detection) low level (tmenc10 cleared status held) high level (tmenc10 cleared status held) cesud01 0 0 1 1 specification of valid edge of tclr10 pin ? the setting of the cesud01 and cesud00 bits is valid only in udc mode a. 7 0
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 532 (5) prescaler mode register 10 (prm10) the prm10 register is used to perform the following selections. ? selection of count clock in general-pur pose timer mode (tum10.t1cmd0 bit = 0) ? selection of count operation mode in udc mode (tum10.t1cmd0 = 1) prm10 can be read or written in 8-bit units. reset input sets this register to 07h. cautions 1. overwriting the prm10 register dur ing tmenc10 operation (tmc10.ce101 bit = 1) is prohibited. 2. in the udc mode (the t1cmd0 bit of the tum10 register = 1), setting the values of the prm102 bit to 0 is prohibited. 3. when tmenc10 is in mode 4, specificati on of the valid edge for the tiud10 and tcud10 pins is invalid. 0 prm10 0 0 0 0 prm102 t1cmd0 = 0 t1cmd0 = 1 tiud10 mode 1 mode 2 mode 3 mode 4 setting prohibited prm101 prm100 654321 after reset: 07h r/w address: fffff5ceh 7 0 setting prohibited f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 prm102 0 0 0 0 1 1 1 1 count clock count clock udc mode prm101 0 0 1 1 0 0 1 1 prm100 0 1 0 1 0 1 0 1 remark f xx : peripheral clock (a) in general-purpose timer m ode (tum10.t1cmd0 bit = 0) the count clock is specified by the prm102 to prm100 bits. (b) udc mode (tum10.t1cmd0 bit = 1) the tmenc10 count triggers in the udc mode are as follows. operation mode tmenc10 operation mode 1 counts down when tcud10 = high level counts up when tcud10 = low level mode 2 counts up upon detection of valid edge of tiud10 input counts down upon detection of valid edge of tcud10 input mode 3 counts up upon detection of valid edge of tiud10 input when tcud10 = high level counts down upon detection of valid edge of tiud10 input when tcud10 = low level mode 4 automatic judgment upon detection of both edges of tiud10 input and both edges of tcud10 input
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 533 (6) status register 10 (status10) the status10 register indicates the operating status of tmenc10. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. 0 status10 0 0 0 0 udf10 ovf10 ubd10 6543 <2> <1> after reset: 00h r address: fffff5cfh no tmenc10 count underflow tmenc10 count underflow udf10 0 1 tmenc10 underflow flag the udf10 bit is cleared (0) upon completion of a read access to the status10 register from the cpu. no tmenc10 count overflow tmenc10 count overflow ovf10 0 1 tmenc10 overflow flag the ovf10 bit is cleared (0) upon completion of a read access to the status10 register from the cpu. tmenc10 count-up in progress tmenc10 count-down in progress ubd10 0 1 tmenc10 count-up/-down operation status the state of the ubd10 bit differs according to the mode as follows. ? the ubd10 bit is fixed to 0 in the general-purpose timer mode (tum10.t1cmd0 bit = 0). ? the ubd10 bit indicates the tmenc10 count-up/-down status in the udc mode (tum10.t1cmd0 bit = 1). 7 <0>
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 534 (7) compare register 100 (cm100) the cm100 register is a 16-bit regi ster that always compares its value with the value of tmenc10. when the value of the compare register matches the value of tm enc10, an interrupt request signal is generated. the interrupt request signal generation timing in the various modes is described below. ? in the general-purpose timer mode (tum10.t1cmd0 bit = 0) and udc mode a (tum10.msel0 bit = 0), an interrupt request signal (intcm100) is always generated upon occurrence of a match. ? in udc mode b (tum10.msel0 bit = 1), an interr upt request signal (intcm100) is generated only upon occurrence of a match during a count-down operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution when the tmc10.ce101 bit is 1, it is prohib ited to overwrite the value of the cm100 register. cm100 654321 after reset: 0000h r/w address: fffff5c2h 70 14 13 12 11 10 9 15 8 (8) compare register 101 (cm101) the cm101 register is a 16-bit regi ster that always compares its value with the value of tmenc10. when the value of the compare register matches the value of tm enc10, an interrupt request signal is generated. the interrupt request signal generation timing in the various modes is described below. ? in the general-purpose timer mode (tum10.t1cmd0 bit = 0) and udc mode a (tum10.msel0 bit = 0), an interrupt request signal (intcm101) is always generated upon occurrence of a match. ? in udc mode b (tum10.msel0 bit = 1), an interr upt request signal (intcm101) is generated only upon occurrence of a match during a count-down operation. this register can be read or written in 16-bit units. reset input clears this register to 0000h. caution when the tmc10.ce101 bit is 1, it is prohib ited to overwrite the value of the cm101 register. cm101 654321 after reset: 0000h r/w address: fffff5c4h 7 0 14 13 12 11 10 9 15 8
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 535 (9) capture/compare register 100 (cc100) the cc100 register is a 16-bit register. it can be specifie d as a capture register or as a compare register using the ccr10 register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. cautions 1. when used as a captu re register (ccr10.cms00 bit = 0), write access is prohibited. 2. when used as a compare register (ccr10.cms00 bi t = 1) and while tmenc10 is operating (tmc10.ce101 bit is 1), overwriting th e cc100 register values is prohibited. 3. when tmenc10 is stopped (tmc10.ce101 bi t = 0), the capture trigger is disabled. 4. when the operation mode is changed from capture register to compare register, set a new compare value. 5. continuous reading of th e cc100 register is prohibited. if the cc100 register is continuously read, the second read value may differ from the actual value. if the cc100 register must be read twice, be sure to read another regi ster between the first and the second read operation. cc100 654321 after reset: 0000h r/w address: fffff5c6h 70 14 13 12 11 10 9 15 8 (a) when set as a capture register when the cc100 register is set as a capture register , the valid edge of the corresponding external interrupt request signal (intp10) is detected as the capture trigger. tmenc10 latches the count value in synchronization with the capture trigger (capture oper ation). the latched value is held in the capture register until the next capture operation. the valid edge of external interrupt request signals (risi ng edge, falling edge, both rising and falling edges) is selected by the sesa10 register. when the cc100 register is specified as a capture regi ster, interrupts are generated upon detection of the valid edge of the intp10 signal. caution tcud10 and intp10 are alternate-functi on pins. therefore, when the tcud10 pin is used in the udc mode, the external capture function of the intp10 pin cannot be used. (b) when set as a compare register when the cc100 register is set as a compare register, it always compares its own value with the value of tmenc10. if the value of the cc100 register matc hes the value of the tme nc10, the cc100 register generates an interrupt request signal (intcc100).
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 536 (10) capture/compare register 101 (cc101) the cc101 register is a 16-bit register. it can be specif ied as a capture register or as a compare register using the ccr10 register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. cautions 1. when used as a captu re register (ccr10.cms01 bit = 0), write access is prohibited. 2. when used as a compar e register (ccr10.cms01 bit = 1) and while tmenc10 is operating (tmc10.ce101 bit is 1), overwriting th e cc101 register values is prohibited. 3. when tmenc10 is stopped (tmc10.ce101 bi t = 0), the capture trigger is disabled. 4. when the operation mode is changed from capture register to compare register, newly set a compare value. 5. continuous reading of th e cc101 register is prohibited. if the cc101 register is continuously read, the second read value may differ from the actual value. if the cc101 register must be read twice, be sure to read another regi ster between the first and the second read operation. cc101 654321 after reset: 0000h r/w address: fffff5c8h 7 0 14 13 12 11 10 9 15 8 (a) when set as a capture register when the cc101 register is set as a capture register , the valid edge of the corresponding external interrupt request signal (intp11) is detected as the capture trigger. tmenc10 latches the count value in synchronization with the capture trigger (capture oper ation). the latched value is held in the capture register until the next capture operation. the valid edge of external interrupt request signal (ri sing edge, falling edge, both rising and falling edges) is selected by the sesa10 register. when the cc101 register is specified as a capture regi ster, interrupts are generated upon detection of the valid edge of the intp11 signal. caution tclr10 and intp11 are alternate-function pins. therefore, when the tclr10 input is used in udc mode a, the external capture function of the intp11 pin cannot be used. (b) when set as a compare register when the cc101 register is set as a compare register, it always compares its own value with the value of tmenc10. if the value of the cc101 register matc hes the value of the tme nc10, the cc101 register generates an interrupt request signal (intcc101).
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 537 11.5 operation 11.5.1 operation in general-purpose timer mode tmenc10 can perform the following operatio ns in the general-purpose timer mode. (1) interval operation (when tmc10.enmd10 bit = 1) tmenc10 and the cm100 register always compare their values and the intcm100 interrupt request signal is generated upon occurrence of a match. tmenc10 is cl eared (0000h) at the count clock following the match. furthermore, when one more count clock is input, tmenc10 counts up to 0001h. the interval time can be calculated with the following formula. interval time = (cm100 register value + 1) tmenc10 count clock rate (2) free-running operation (whe n tmc10.enmd10 bit = 0) tmenc10 fully counts from 0000h to ffffh, is clear ed to 0000h at the next count clock after the status10.ovf10 bit has been set (1), and continues counting. the free-running cycle can be calc ulated by the following formula. free-running cycle = 65,536 tmenc10 count clock rate (3) compare function tmenc10 connects two compare register (cm100, cm101) channels and two capture/compare register (cc100, cc101) channels. when the tmenc10 count value and the set value of one of the compare registers match, a match interrupt request signal (intcm100, intcm101, intcc100 note , intcc101 note ) is output. particularly in the case of interval operation, tmenc10 is cleared upon generation of the intcm100 interrupt. note this match interrupt request signal is generat ed when the cc100 and cc101 registers are set to the compare register mode.
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 538 (4) capture function tmenc10 connects two capture/compare register (cc100, cc101) channels. when the cc100 and cc101 registers are set to the c apture register mode, the value of tmenc10 is captured in synchronization with the corresponding capture trigger signal. furthermore, an interrupt request signal (intcc100, in tcc101) is generated by the valid edge of the intp10 and intp11 input signals specified as the capture trigger signals. table 11-3. capture trigger signa l to 16-bit capture register capture register capture trigger signal cc100 intp10 cc101 intp11 remark cc100 and cc101 registers are capture/compare registers. which of these registers is used is specified by the ccr10 register. the valid edge of the capture trigger is specified by the sesa10 regist er. if both the rising edge and the falling edge are selected as the capture triggers, it is possible to measure the input pulse width externally. if a single edge is selected as the capture trigger , the input pulse cycle can be measured. (5) timer output operation timer output operation is performed from the to10 pin by setting tmenc10 to the general-purpose timer mode (t1cmd0 bit = 0) using the tum10 register. during the timer output operation, the cycle and dut y (cm100 and cm101 registers) cannot be rewritten. the resolution is 16 bits, and t he count clock can be selected from among seven internal clocks (f xx /4, f xx /8, f xx /16, f xx /32, f xx /64, f xx /128, f xx /256). figure 11-2. tmenc10 block diagram (during timer output operation) tmenc10 (16 bits) compare register (cm100) compare register (cm101) s intcm100 intcm101 alvt100 tum10 register clear 16 16 to10 q r f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 caution be sure to set the count clo ck of tmenc10 to 10 mhz or lower. remark f xx : peripheral clock
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 539 (a) description of operation the cm100 register is a compare register used to se t the timer output cycle. when the value of this register matches the value of tmenc10, the intc m100 interrupt request signal is generated. the compare match is saved by hardware, and tmenc10 is cl eared at the next count clock after the match. the cm101 register is a compare register used to set the timer output duty. set the duty required for the timer cycle. figure 11-3. timer output e xample (when alvt100 bit = 0) cm100 set value cm101 set value tmenc10 to10 intcm100 intcm101 cautions 1. changing the valu es of the cm100 and cm101 registers is prohibited during tmenc10 operation (tmc10.ce101 bit = 1). 2. changing the value of th e tum10.alvt100 bit is prohibited during tmenc10 operation. 3. timer output is performed from the second ti mer cycle after the ce101 bit is set (to 1).
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 540 11.5.2 operation in udc mode (1) overview of operation in udc mode the count clock input to tmenc10 in the udc mode (t um10.t1cmd0 bit = 1) can only be externally input from the tiud10 and tcud10 pins. count-up/-down ju dgment in the udc mode is determined based on the phase difference of the tiud10 and tcud10 pin inputs a ccording to the prm10 register setting (there is a total of four choices). table 11-4. list of count operations in udc mode prm10 register prm102 prm101 prm100 operation mode tmenc10 operation 1 0 0 mode 1 counts down when tcud10 = high level counts up when tcud10 = low level 1 0 1 mode 2 counts up upon detection of valid edge of tiud10 input counts down upon detection of valid edge of tcud10 input 1 1 0 mode 3 counts up upon detection of valid edge of tiud10 input when tcud10 = high level counts down upon detection of valid edge of tiud10 input when tcud10 = low level 1 1 1 mode 4 automatic judgment upon detection of both edges of tiud10 input and both edges of tcud10 input the udc mode is further divided into two modes according to the tmenc10 clear conditions (a count operation is performed only with tiud10 and tcud10 input in both modes). ? udc mode a (tum10.t1cmd0 bit = 1, tum10.msel0 bit = 0) the tmenc10 clear source can be selected as only external clear input (tclr10), a match signal between the tmenc10 count value and the cm10 0 register set value during count-up operation, or the logical sum (or) of the two signals, using tmc10.clr101 and tm c10.clr100 bits. tmenc10 can transfer the value of the cm100 register upon occurrence of a tmenc10 underflow. ? udc mode b (tum10.t1cmd0 bit = 1, tum10.msel0 bit = 1) the status of tmenc10 after a match of the tmenc1 0 count value and cm100 register set value is as follows. <1> in the case of a count-up operation, tmenc1 0 is cleared (0000h), and the intcm100 interrupt request signal is generated. <2> in the case of a count-down operation, the tmenc10 count value is decremented ( ? 1). the status of tmenc10 after a match of the tmenc1 0 count value and cm101 register set value is as follows. <1> in the case of a count-up operation, t he tmenc10 count value is incremented (+1). <2> in the case of a count-down operation, tmenc10 is cleared (0000h), and the intcm101 interrupt request signal is generated.
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 541 (2) count-up/-down operation in udc mode tmenc10 count-up/-down judgment in the udc mode is determined based on the phase difference of the tiud10 and tcud10 pin inputs according to the prm10 register setting. (a) mode 1 (prm10.prm102 bit = 1, prm10. prm101 bit = 0, prm10.prm100 bit = 0) in mode 1, the following count operations are performed based on the level of the tcud10 pin upon detection of the valid edge of the tiud10 pin. ? tmenc10 count-down operation when tcud10 pin = high level ? tmenc10 count-up operation when tcud10 pin = low level figure 11-4. mode 1 (when rising edge is specified as valid edge of tiud10 pin) tiud10 tcud10 tmenc10 0006h 0007h count down count up 0005h 0004h 0005h 0006h 0007h figure 11-5. mode 1 (when rising edge is specified as valid edge of tiud10 pin): in case of simultaneous tcud10, tcud10 pin edge timing 0007h tiud10 tcud10 tmenc10 0006h count down count up 0005h 0004h 0005h 0006h 0007h
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 542 (b) mode 2 (prm10.prm102 bit = 1, prm10. prm101 bit = 0, prm10.prm100 bit = 1) the count conditions in mode 2 are as follows. ? tmenc10 count-up upon detection of valid edge of tiud10 pin ? tmenc10 count-down upon detection of valid edge of tcud10 pin caution if the count clock is simultaneously in put to the tiud10 pin and the tcud10 pin, a count operation is not performed and the i mmediately preceding value is held. figure 11-6. mode 2 (when rising edge is speci fied as valid edge of tiud10, tcud10 pins) 0006h tiud10 tcud10 tmenc10 0007h 0008h count up hold value count down 0007h 0006h 0005h (c) mode 3 (prm10.prm102 = 1, prm 10.prm101 = 1, prm10.prm100 = 0) in mode 3, when two signals 90 degrees out of phase are input to the tiud10 and tcud10 pins, the level of the tcud10 pin is sampled at the input of the valid edge of the tiud10 pin (see figure 11-7 ). if the tcud10 pin level sampled at the valid edge input to the tiud10 pin is low, tmenc10 counts down when the valid edge is input to the tiud10 pin. if the tcud10 pin level sampled at the valid edge in put to the tiud10 pin is high, tmenc10 counts up when the valid edge is input to the tiud10 pin. figure 11-7. mode 3 (when rising edge is specified as valid edge of tiud10 pin) 0007h tiud10 tcud10 tmenc10 0008h count up count down 0009h 000ah 0009h 0008h 0007h
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 543 figure 11-8. mode 3 (when rising edge is specified as valid edge of tiud10 pin): in case of simultaneous tiud 10, tcud10 pin edge timing 0007h tiud10 tcud10 tmenc10 0008h count up count down 0009h 000ah 0009h 0008h 0007h (d) mode 4 (prm10.prm102 = 1, prm 10.prm101 = 1, prm10.prm100 = 1) in mode 4, when two signals out of phase are in put to the tiud10 and tcud10 pins, the up/down operation is automatically judged and counting is performed according to the timing shown in figure 11-9 . in mode 4, counting is executed at both the rising and falling edges of the two signals input to the tiud10 and tcud10 pins. therefore, tmenc10 counts f our times per cycle of an input signal ( 4 count). figure 11-9. mode 4 count up tiud10 tcud10 tmenc10 0004h 0003h 0006h 0005h 0008h 0007h 000ah 0009h 0008h 0009h 0006h 0007h 0005h count down cautions 1. when mode 4 is specified as th e operation mode of tmenc10, the valid edge specifications for th e tiud10 and tcud10 pins are not valid. 2. if the tiud10 pin edge and tcud10 pin e dge are input simultan eously in mode 4, tmenc10 continues the same count operation (u p or down) it was performing immediately before the input.
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 544 (3) operation in udc mode a (a) interval operation the operations at the count clock following a match of the tmenc10 count value and the cm100 register set value are as follows. ? in case of count-up operation: tmenc10 is cleared (0000h) and the intcm100 interrupt request signal is generated. ? in case count-down operation: the tmenc10 count value is decremented ( ? 1) and the intcm100 interrupt request signal is generated. remark the interval operation can be combin ed with the transfer operation. (b) transfer operation if tmenc10 = 0000h during down counting when the tmc10.rlen10 bit = 1, the set value of the cm100 register is transferred to tm enc10 at the next count clock. remarks 1. transfer enable/disable can be set using the tmc10.rlen10 bit. 2. the transfer operation can be combin ed with the interval operation. figure 11-10. example of tmenc10 oper ation when interval operation and transfer operation are combined tmenc10 and cm100 match & timer clear tmenc10 underflow & cm100 data transfer tmenc10 count value cm100 register set value count up count down 0000h (c) compare function tmenc10 connects two compare register (cm100, cm 101) channels and two capture/compare register (cc100, cc101) channels. when the tmenc10 count value and the set value of one of the compare registers match, a match interrupt request signal (intcm100, intcm101, intcc100 note , intcc101 note ) is output. note this match interrupt request signal is generated when the cc100 and cc101 registers are set to the compare register mode. (d) capture function tmenc10 connects two capture/compare register (cc100, cc101) channels. when the cc100 and cc101 registers are set to the capture register mode, the value of tmenc10 is captured in synchronization with the corresponding capture trigger signal. a capture interrupt request signal (intcc100, int cc101) is generated upon detection of the valid edge.
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 545 (4) operation in udc mode b (a) basic operation the operations at the next count clock after the c ount value of tmenc10 and the cm100 register set value match when tmenc10 is in udc mode b are as follows. ? in case of count-up operation: tmenc10 is cleared (0000h) and the intcm100 interrupt request signal is generated. ? in case of count-down operation: the tmenc10 count value is decremented ( ? 1). the operations at the next count clock after the c ount value of tmenc10 and the cm101 register set value match when tmenc10 is in udc mode b are as follows. ? in case of count-up operation: the tm enc10 count value is incremented (+1). ? in case of count-down operation: tmenc10 is cleared (0000h) and the intcm101 interrupt request signal is generated. figure 11-11. example of tmenc10 operation in udc mode cm100 register set value cm101 register set value tmenc10 count value clear tmenc10 not cleared if count clock counts down following match clear tmenc10 not cleared if count clock counts up following match (b) compare function tmenc10 connects two compare register (cm100, cm 101) channels and two capture/compare register (cc100, cc101) channels. when the tmenc10 count value and the set value of one of the compare registers match, a match interrupt request signal (intcm100 (only during count -up operation), intcm101 (only during count-down operation), intcc100 note , intcc101 note ) is output. note this match interrupt request signal is generated when the cc100 and cc101 registers are set to the compare register mode. (c) capture function tmenc10 connects two capture/compare register (cc100, cc101) channels. when cc100 and cc101 registers are set to the capt ure register mode, the value of tmenc10 is captured in synchronization with t he corresponding capture trigger signal. a capture interrupt request signal (intcc100, intcc101) is generated upon detection of the valid edge.
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 546 11.6 supplementary description of internal operation 11.6.1 clearing of count value in udc mode b when tmenc10 is in udc mode b, the conditions to clear the count value are as follows. ? in case of tmenc10 count-up operation: tmenc10 co unt value is cleared upon match with cm100 register ? in case of tmenc10 count-down operation: tmenc10 count value is cleared upon match with cm101 register figure 11-12. clear operation after match of cm 100 register set value and tmenc10 count value (a) count-up count-up count clock (rising edge set as valid edge) cm100 register fffeh tmenc10 cleared tmenc10 ffffh 0000h 0001h ffffh count up count up (b) count-up count-down count clock (rising edge set as valid edge) cm100 register fffeh tmenc10 not cleared tmenc10 ffffh fffeh fffdh ffffh count down count down
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 547 figure 11-13. clear operation after match of cm 101 register set value and tmenc10 count value (a) count-down count-down count clock (rising edge set as valid edge) cm101 register 00ffh tmenc10 cleared tmenc10 00feh 0000h ffffh 00feh count down count up (b) count-down count-up count clock (rising edge set as valid edge) cm101 register 00ffh tmenc10 not cleared tmenc10 00feh 00ffh 0100h 00feh count down count up 11.6.2 transfer operation if tmenc10 = 0000h during down counting when the tmc10.rlen10 bit = 1 in udc mode a, the set value of the cm100 register is transferred to tmenc10 at the next count clock. the transfer operat ion is not performed during up counting. figure 11-14. internal operat ion during transfer operation count clock (rising edge set as valid edge) cm100 register 0001h transfer operation performed. tmenc10 0000h cm100 set value cm100 set value ? 1 ffffh count down count up
chapter 11 16-bit 2-phase encoder input up/down counter/general-purpose timer (tmenc1) user?s manual u16397ej3v0ud 548 11.6.3 interrupt request signal output upon compare match an interrupt request signal is output when the count va lue of tmenc10 matches the set value of the cm100, cm101, cc100 note , or cc101 note register. the interrupt request timing generation timing is as follows. note when the cc100 and cc101 registers are set to the compare register mode. figure 11-15. interrupt request si gnal output upon compare match (cm101 with operation mode set to general-purpose timer mode and count clock set to f xx /4) count clock f xx /2 cm101 register 0007h tmenc10 internal match signal intcm101 0008h 000bh 0009h 0009h 000ah remark f xx : peripheral clock an interrupt request signal such as the one illustrated in figure 11-15 is output at t he next count clock following a match of the tmenc10 count value and the set va lue of the corresponding compare register. 11.6.4 ubd10 flag (bit 0 of status10 register) operation in the udc mode (tum10.t1cmd0 bit = 1), the ubd10 flag changes as follows during a tmenc10 count-up/ -down operation at every internal operation clock. figure 11-16. ubd10 flag operation count clock ubd10 flag 0001h 0000h tmenc10 0000h 0001h 0001h 0000h
user?s manual u16397ej3v0ud 549 chapter 12 motor control function 12.1 functional overview timer q0 (tmq0) and the tmq0 option (tmqop0) can be used as an inverter function that controls a motor. it performs a tuning operation with timer p2 (tmp2) and a/d co nversion of the a/d converter can be started when the value of tmq0 matches the value of tmp2. the following operations can be performed as motor control functions. ? 6-phase pwm output function with 16-bit accura cy (with dead-timer, for upper and lower arms) ? timer tuning operation function (tunable with tmp2) ? cycle setting function (cycle can be changed dur ing operation of crest or valley interrupt) ? compare register rewriting: anytime rewrite, batch rewr ite, or intermittent rewrite (selectable during tmq0 operation) ? interrupt and transfer culling functions ? dead-time setting function ? a/d trigger timing function of the a/d conv erter (four types of timing can be generated) ? 0% output and 100% output available ? 0% output and 100% output selectable by crest interrupt and valley interrupt ? forced output stop function ? at valid edge detection by external pin input (intp000)
chapter 12 motor control function user?s manual u16397ej3v0ud 550 12.2 configuration the motor control function consists of the following hardware. item configuration timer register dead-time counter m compare register tmq0 dead-time co mpare register (tq0dtc register) control registers tmq0 option register 0 (tq0opt0) tmq0 option register 1 (tq0opt1) tmq0 option register 2 (tq0opt2) tmq0 i/o control register 3 (tq0ioc3) high-impedance output control register s 0, 1 (hza0ctl0, hza0ctl1) remark m = 0 to 3 ? 6-phase pwm output can be produced with dead time by using the output of tmq0 (toq1, toq2, toq3) ? the output level of the 6-phase pwm output can be set individually. ? the 16-bit timer/counter of tmq0 counts up/down triangular waves. when the timer/counter underflows and when a cycle match occurs, an interrupt is generated. interrupt generation, however, can be suppressed up to 31 times. ? tmp2 can execute counting at the same time as tmq0 (t imer tuning operation function). tmp2 can be set in four ways as it can generate two types of a/d tri gger sources (intccp20 and intccp21), and two types of interrupts: on underflow interrupt (intovq) and cycle match interrupt (intccq0).
chapter 12 motor control function user?s manual u16397ej3v0ud 551 figure 12-1. block diagram of motor control tmq0 tmq1 option tmp2 tmp0 intc toqt1 toqb1 toqt2 top01 intp000 toqb2 toqt3 toqb3 ? a/d trigger timing generation in tuning operation with tmq0 ? carrier ? 3-phase pwm generation ? 6-phase pwm generation with dead time from 3-phase pwm ? culling control ? a/d trigger selection ? pwm generation ? see figure 12-4 . high-impedance output controller ? interrupt control edge detection crest interrupt (intccq0) valley interrupt (intovq) noise elimination a/d trigger of a/d converter
chapter 12 motor control function user?s manual u16397ej3v0ud 552 figure 12-2. tmq0 option toqt1 high-impedance output controller toqb1 tq0dtc (10-bit dead-time value) toq1 (internal signal) toq2 (internal signal) toq3 (internal signal) tmq0 channel 2 dead-time counter 1 (10 bits) edge detection channel 1 positive phase f/f active setting clear negative phase f/f active setting level control output control level control output control counter mask count buffer interrupt culling circuit a/d trigger generator number of masks crest/valley interrupt selection culling enable mask control internal bus toqt2 toqb2 channel 3 intccp20 intccp21 tmp2 intovq intccq0 intc toqt3 toqb3 a/d converter tqtadt a/d trigger selection (tq0opt2 register) up/down selection
chapter 12 motor control function user?s manual u16397ej3v0ud 553 (1) tmq0 dead-time comp are register (tq0dtc) the tq0dtc register is a 10-bit compare re gister that specifies a dead-time value. rewriting this register is prohibi ted when the tq0ctl0.tq0ce bit = 1. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0dtc 000000 tq0dtc9 to tq0dtc0 10 9 after reset: 0000h r/w address: fffff624h 15 0 (2) dead-time counters 1 to 3 the dead-time counters are 10-bit counters that count dead time. these counters are cleared or count up at the rising or falling edge of the toqm output signal by tmq0, and are cleared or stopped when their count value matches the value of the tq0dtc register. the count clock of these counters is the same as that set by the tq0ctl0.tq0cks2 to tq0ctl0.tq0cks0 bits of tmq0. remarks 1. the operation differs when the tq0o pt2.tq0dtm bit = 1. for details, see 12.4.2 (4) automatic dead-time width narrowi ng function (tq0opt2 .tq0dtm bit = 1) . 2. m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 554 12.3 control registers (1) tmq0 option register 0 (tq0opt0) the tq0opt0 register is an 8-bit register that controls the timer q0 option function. this register can be read or written in 8-bit or 1- bit units. however, the tq0cuf bit is read-only. reset input clears this register to 00h. caution the tq0cms and tq0cuf bits can be set only in the 6-phase pwm output mode. be sure to clear these bits to 0 when tmq0 is used alone. 0 tq0opt0 0 0 0 0 tq0cms tq0cuf tq0ovf note 6 5 4 3 <2> <1> after reset: 00h r/w address: fffff605h tq0cms 0 1 compare register rewrite mode selection ? the tq0cms bit is valid only when the 6-phase pwm output mode is set (when the tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits = 111). clear the tq0cms bit to 0 in any other mode. ? the tq0cms bit can be rewritten while the timer is operating (when the tq0ctl0.tq0ce bit = 1). ? the following compare registers are rewritten in the batch write mode. tq0ccr0 to tq0ccr3, tp2ccr0, tp2ccr1, and tq0opt1 registers batch rewrite mode (transfer operation) anytime rewrite mode tq0cuf 0 1 count-up/count-down flag of timer q0 the tq0cuf bit is valid only when the 6-phase pwm output mode is set (when the tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits = 111). timer q0 is counting up. timer q0 is counting down. 7 <0> note for details of the tq0ovf bit, see chapter 9 16-bit timer/event counter q (tmq) . caution be sure to clear bits 7 to 3 to ?0?.
chapter 12 motor control function user?s manual u16397ej3v0ud 555 (2) tmq0 option register 1 (tq0opt1) the tq0opt1 register is an 8-bit regist er that controls the interrupt requ est signal generated by the timer q0 option function. this register can be rewritten w hen the tq0ctl0.tq0ce bit is 1. two rewrite modes (batch write m ode and anytime write mode) can be selected, depending on the setting of the tq0opt0.tq0cms bit. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0ice tq0ice 0 1 crest interrupt (intccq0 signal) enable do not use intccq0 signal (do not use it as count signal for interrupt culling). use intccq0 signal (use it as count signal for interrupt culling). tq0opt1 tq0ioe 0 tq0id4 tq0id3 tq0id2 tq0id1 tq0id0 <6>54 32 1 tq0ioe 0 1 valley interrupt (intovq signal) enable do not use intovq signal (do not use it as count signal for interrupt culling). use intovq signal (use it as count signal for interrupt culling). after reset: 00h r/w address: fffff620h <7> 0 not culled (all interrupts are output) 1 masked (one of two interrupts is output) 2 masked (one of three interrupts is output) 3 masked (one of four interrupts is output) : 28 masked (one of 29 interrupts is output) 29 masked (one of 30 interrupts is output) 30 masked (one of 31 interrupts is output) 31 masked (one of 32 interrupts is output) tq0id4 0 0 0 0 : 1 1 1 1 number of times of interrupt tq0id3 0 0 0 0 : 1 1 1 1 tq0id2 0 0 0 0 : 1 1 1 1 tq0id1 0 0 1 1 : 0 0 1 1 tq0id0 0 1 0 1 : 0 1 0 1
chapter 12 motor control function user?s manual u16397ej3v0ud 556 (3) tmq0 option register 2 (tq0opt2) the tq0opt2 register is an 8-bit register that controls the timer q0 option function. this register can be rewritten when the tq0ctl0.tq0ce bit is 1. however, rewriting the tq0dtm bit is prohibited when the tq0ce bit is 1. the same value can be rewritten. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. (1/2) tq0rde tq0opt2 tq0dtm tq0atm3 tq0atm2 tq0at3 tq0at2 tq0at1 tq0at0 <6> <5> <4> <3> <2> <1> tq0atm3 0 1 tq0atm3 mode selection rewriting the tq0dtm bit is disabled during timer operation. if it is rewritten by mistake, stop the timer operation by clearing the tq0ce bit to 0, and re-set the tq0dtm bit. output a/d trigger signal (tqtadt) for intccp21 interrupt while dead-time counter is counting up. output a/d trigger signal (tqtadt) for intccp21 interrupt while dead-time counter is counting down. tq0atm2 0 1 tq0atm2 mode selection output a/d trigger signal (tqtadt) for intccp20 interrupt while dead-time counter is counting up. output a/d trigger signal (tqtadt) for intccp20 interrupt while dead-time counter is counting down. tq0dtm 0 1 dead-time counter operation mode selection dead-time counter counts up normally and, if toqm output of tmq0 is at a narrow interval (toqm output width < dead-time width), the dead-time counter is cleared and counts up again. dead-time counter counts up normally and, if toqm output of tmq0 is at a narrow interval (toqm output width < dead-time width), the dead-time counter counts down and the dead-time control width is automatically narrowed. after reset: 00h r/w address: fffff621h <7> <0> tq0rde 0 1 transfer culling enable do not cull transfer (transfer timing is generated every time at crest and valley). cull transfer at the same interval as interrupt culling set by the tq0opt1 register. caution when using interrupt culling (the tq 0opt1.tq0id4 to tq0opt1.tq0id0 bits are set to other than 00000), be sure to set the tq0rde bit to 1. therefore, the interrupt and transfer are generated at the same timing. the interrupt and transfer cannot be set separately. if the interrupt and transfer are set separately (tq0rde bi t = 0), transfer is not performed normally. remark m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 557 (2/2) tq0at3 note 0 1 a/d trigger output control 3 disable output of a/d trigger signal (tqtadt) for intccp21 interrupt. enable output of a/d trigger signal (tqtadt) for intccp21 interrupt. tq0at2 note 0 1 a/d trigger output control 2 disable output of a/d trigger signal (tqtadt) for intccp20 interrupt. enable output of a/d trigger signal (tqtadt) for intccp20 interrupt. tq0at1 note 0 1 a/d trigger output control 1 disable output of a/d trigger signal (tqtadt) for intccq0 (crest interrupt). enable output of a/d trigger signal (tqtadt) for intccq0 (crest interrupt). tq0at0 note 0 1 a/d trigger output control 0 disable output of a/d trigger signal (tqtadt) for intovq (valley interrupt). enable output of a/d trigger signal (tqtadt) for intovq (valley interrupt). note for the setting of the tq0at3 to tq0at0 bits, see chapter 14 a/d converter .
chapter 12 motor control function user?s manual u16397ej3v0ud 558 (4) tmq0 i/o control register 3 (tq0ioc3) the tq0ioc3 register is an 8-bit register that c ontrols the output of the timer q0 option function. to output from the toqtm pin, se t the tq0ioc0.tq0oem bit to 1 and then set the tq0ioc3 register. the tq0ioc3 register can be rewritten only when the tq0ctl0.tq0ce bit is 0. rewriting each bit of the tq0ioc3 register is prohibit ed when the tq0ctl0.tq0ce bit is 1; however the same value can be rewritten to each bit of the tq0 ioc3 register when the tq0ctl0.tq0ce bit is 1. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to a8h. caution set the tq0ioc3 register to the default value (a8h) when the timer is used in a mode other than the 6-phase pwm output mode. remark set the output level of the toqt m pin by the tq0ioc0 register. tq0olb3 tq0ioc3 tq0oeb3 tq0olb2 tq0oeb2 tq0olb1 tq0oeb1 0 0 <6> <5> <4> <3> <2> 1 setting of toqbm pin output level (m = 1 to 3) disable inversion of output of toqbm pin enable inversion of output of toqbm pin tq0oebm 0 1 tq0olbm 0 1 toqbm pin output (m = 1 to 3) disable toqbm pin output. ? when tq0olbm bit = 0, low level is output from toqbm pin. ? when tq0olbm bit = 1, high level is output from toqbm pin. enable toqbm pin output. after reset: a8h r/w address: fffff622h <7> 0
chapter 12 motor control function user?s manual u16397ej3v0ud 559 (a) output from toqtm and toqbm pins the toqtm pin output is controlled by the tq0ioc 0.tq0olm and tq0ioc0.tq0oem bits. the toqbm pin output is controlled by the tq0 ioc3.tq0olbm and tq0ioc3.tq0oebm bits. the timer output with each setting in the 6- phase pwm output mode is shown below. figure 12-3. output control of toqtm and toqbm pins 16-bit counter fixed to low-level output fixed to high-level output toqtm pin output tq0oem bit = 0, tq0olm bit = 0 (status after reset) tq0oebm bit = 0, tq0olbm bit = 1 (status after reset) tq0oem bit = 1, tq0olm bit = 0 (positive-phase output) tq0oebm bit = 1, tq0olbm bit = 1 (negative-phase output) tq0oem bit = 1, tq0olm bit = 0 (positive-phase output) tq0oebm bit = 1, tq0olbm bit = 0 (positive-phase output) tq0oem bit = 1, tq0olm bit = 1 (negative-phase output) tq0oebm bit = 1, tq0olbm bit = 1 (negative-phase output) toqbm pin output toqtm pin output toqbm pin output toqtm pin output toqbm pin output toqtm pin output toqbm pin output remark m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 560 table 12-1. toqtm pin output tq0olm bit tq0oem bit tq0ce bit toqtm pin output 0 x low-level output 0 low-level output 0 1 1 toqtm positive-phase output 0 x high-level output 0 high-level output 1 1 1 toqtm negative-phase output remark m = 1 to 3 table 12-2. toqbm pin output tq0olbm bit tq0oebm bit tq0ce bit toqbm pin output 0 x low-level output 0 low-level output 0 1 1 toqbm positive-phase output 0 x high-level output 0 high-level output 1 1 1 toqbm negative-phase output remark m = 1 to 3 (5) high-impedance output control registers 00, 01 (hza0ctln) the hza0ctln registers are 8-bit r egisters that control the high-impe dance state of the output buffer. these registers can be read or written in 8-bit or 1-bi t units. however, the hza0dcf1 bit is a read-only bit and cannot be written. 16-bit access is not possible. reset input clears these registers to 00h. the same value can be always rewritten to the hza0ctln register by software. the relationship between detection factor an d the control registers is shown below. pins subject to high-impedance control high-impedance control factor (external pin) control register when top01/p01 is output hza0ctl0 when toqb1/toq0/p10 is output when toqt1/toq1/p11 is output when toqt2/toq2/p12 is output when toqt3/toq3/p13 is output when toqb2/p14 is output when toqb3/p15 is output intp000 hza0ctl1 caution high-impedance control is affected only when the target pin is set as an output pin (including when it is set in the output mode other than timer output mode).
chapter 12 motor control function user?s manual u16397ej3v0ud 561 (1/2) hza0dcen hza0dcen 0 1 high-impedance output control disable high-impedance output control operation. pins can function as output pins. enable high-impedance output control operation. hza0ctln hza0dcmn hza0dcnn hza0dcpn hza0dctn hza0dccn 0 hza0dcfn <6> 5 4 <3> <2> 1 hza0dcnn 0 0 1 1 hza0dcpn 0 1 0 1 intp000 pin input edge specification no valid edge (setting the hza0dcfn bit by intp000 pin input is prohibited). rising edge of the intp000 pin is valid (abnormality is detected by rising edge input). falling edge of the intp000 pin is valid (abnormality is detected by falling edge input). setting prohibited hza0dcmn 0 1 condition of clearing high-impedance state by hza0dccn bit setting of the hza0dccn bit is valid regardless of the intp000 pin input. setting of the hza0dccn bit is invalid while the intp000 pin holds a level detected as abnormal (active level). after reset: 00h r/w address: hza0ctl0 fffff630h, hza0ctl1 fffff631h <7> <0> rewrite the hza0dcmn bit when the hza0dcen bit = 0. hza0dctn 0 1 high-impedance output trigger bit no operation pins are made to go into a high-impedance state by software and the hza0dcfn bit is set to 1. ? if an edge indicating abnormality is input to the intp000 pin (which is detected according to the setting of the hza0dcnn and hza0dcpn bits), the hza0dctn bit is invalid even if it is set to 1. ? the hza0dctn bit is always 0 when it is read because it is a software-triggered bit. ? the hza0dctn bit is invalid even if it is set to 1 when the hza0dcen bit = 0. ? simultaneously setting the hza0dctn and hza0dccn bits to 1 is prohibited. ? rewrite the hza0dcnn and hza0dcpn bits when the hza0dcen bit is 0. ? high-impedance output control is performed when the valid edge is input after the operation is enabled (by setting hza0dcen bit to 1). if the intp000 pin is at the active level when the operation is enabled, therefore, high-impedance output control is not performed. (n = 0, 1)
chapter 12 motor control function user?s manual u16397ej3v0ud 562 (2/2) hza0dccn 0 1 high-impedance output control clear bit no operation pins that have gone into a high-impedance state are output-enabled by software and the hza0dcfn bit is cleared to 0. ? pins can function as output pins when the hza0dcm bit = 0, regardless of the status of the intp000 pin. ? if an edge indicating abnormality is input to the intp000 pin (which is set by the hza0dcnn and hza0dcpn bits) when the hza0dcm bit = 1, the hza0dccn bit is invalid even if it is set to 1. ? the hza0dccn bit is always 0 when it is read. ? the hza0dccn bit is invalid even if it is set to 1 when the hza0dcen bit = 0. ? simultaneously setting the hza0dctn and hza0dccn bits to 1 is prohibited. hza0dcfn high-impedance output status flag indicates that output of the pin is enabled. ? this bit is cleared to 0 when the hza0dcen bit = 0. ? this bit is cleared to 0 when the hza0dccn bit = 1. indicates that the pin goes into a high-impedance state. ? this bit is set to 1 when the hza0dctn bit = 1. ? this bit is set to 1 when an edge indicating abnormality is input to the intp000 pin (which is detected according to the setting of the hza0dcnn and hza0dcpn bits). clear (0) set (1) figure 12-4. high-impedance output controller configuration hza0ctl1 analog delay tmp0 tmq0/tmqop0 hza0ctl0 top01 intp000 (abnormality detection) toqb1 toqt1 toqt2 toqt3 toqb2 toqb3
chapter 12 motor control function user?s manual u16397ej3v0ud 563 (a) setting procedure (i) setting of high-impedance control operation <1> set the hza0dcmn, hza0dcnn, and hza0dcpn bits. <2> set the hza0dcen bit to 1 (enable high-impedance control). (ii) changing setting after enablin g high-impedance control operation <1> clear the hza0dcen bit to 0 (to stop the high-impedance control operation). <2> change the setting of the hza0 dcmn, hza0dcnn, and hza0dcpn bits. <3> set the hza0dcen bit to 1 (to enable t he high-impedance control operation again). (iii) resuming output when pins are in high-impedance state if the hza0dcmn bit is 1, set the hza0dccn bit to 1 to clear the high-impedance state after the valid edge of the intp000 pin is detected. however, t he high-impedance state cannot be cleared unless this bit is set while the input level of the intp000 pin is inactive. <1> set the hza0dccn bit to 1 (command si gnal to clear the high-impedance state). <2> read the hza0dcfn bit and check the flag status. <3> return to <1> if the hza0dcfn bit is 1. the input level of the intp000 pin must be checked. the pin can function as an output pin if the hza0dcfn bit is 0. (iv) to make the pin to go into a high-impedance state by software the hza0dctn bit must be set to 1 by software to make the pin to go into a high-impedance state while the input level of the intp000 pin is inactive. the following procedure is an example in which the setting is not dependent upon the setting of the hza0dcmn bit. <1> set the hza0dctn bit to 1 (high-impedance output command). <2> read the hza0dcfn bit to check the flag status. <3> return to <1> if the hza0dcfn bit is 0. the input level of the intp000 pin must be checked. the pin is in a high-impedance state if the hza0dcfn bit is 1. however, if the intp000 pin is not used with the hza0dcp1 bit and hza0dcnn bit cleared to 0, the pin goes into a high-impedance state when the hza0dctn bit is set to 1.
chapter 12 motor control function user?s manual u16397ej3v0ud 564 12.4 operation 12.4.1 system outline (1) outline of 6-phase pwm output the 6-phase pwm output mode is used to generate a 6-phase pwm output wave, by using tmq0 and the tmq0 option in combination. the 6-phase pwm output mode is enabled by setting t he tq0ctl1.tq0md2 to tq0ctl1.tq0md0 bits of tmq0 to ?111?. one 16-bit counter and four 16-bit compare registers of tmq0 are used to generate a basic 3-phase wave. the functions of the compar e registers are as follows. tmp2 can perform a tuning operation with tmq0 to star t a conversion trigger source for the a/d converter. compare register function settable range tq0ccr0 register setting of cycle 0002h m fffeh tq0ccr1 register specifying output width of phase u 0000h i m + 1 tq0ccr2 register specifying output width of phase v 0000h j m + 1 tq0ccr3 register specifying output width of phase w 0000h k m + 1 remark m = set value of tq0ccr0 register i = set value of tq0ccr1 register j = set value of tq0ccr2 register k = set value of tq0ccr3 register a dead-time interval is generated from the basic 3-phas e wave generated by using three 10-bit dead-time counters and one compare register to create a wave with a reverse phase to that of the basic 3-phase wave. then a 6-phase pwm output wave (u, u, v, v, w, and w) is generated. the 16-bit counter for generating the basic 3-phase wa ve counts up or down. after the operation has been started, this counter counts up. when its count value matches the cycle set to the tq0ccr0 register, the counter starts counting down. w hen the count value matches 0001h, the counter counts up again. this means that a value two times higher than the value se t to the tq0ccr0 register + 1 is the carrier cycle. 10-bit dead-time counters 1 to 3 that generate the dead-time interval count up . therefore, the value set to the tmq0 dead-time compare register (tq0dtc) is used as a dead-time value as is. because three counters are used, dead time can be generated independently in phases u, v, and w. however, because there is only one register that specifies a dead-time value (tq0dtc), the same dead-time value is used in the three phases.
chapter 12 motor control function user?s manual u16397ej3v0ud 565 figure 12-5. outline of 6-phase pwm output mode tot1 toqt1 pin output (u) tob1 toqb1 pin output (u) toqt2 pin output (v) toqb2 pin output (v) toqt3 pin output (w) toqb3 pin output (w) tot2 tob2 tot3 tob3 16-bit counter up/down selection tq0ccr0 register (carrier cycle) toq1 (internal signal) 0001h toq2 (internal signal) toq3 (internal signal) tq0ccr1 register (phase u output data) tq0ccr2 register (phase v output data) tq0ccr3 register (phase w output data) dead-time counter 1 dead-time counter 2 dead-time counter 3 tq0dtc register (dead-time value) intovq signal (valley interrupt) intccq0 signal (crest interrupt)
chapter 12 motor control function user?s manual u16397ej3v0ud 566 figure 12-6. timing chart of 6-phase pwm output mode 16-bit counter m (carrier data) tq0ccr0 register toq1 signal (internal signal) toq2 signal (internal signal) toq3 signal (internal signal) tq0dtc register toqt1 pin output (u) toqb1 pin output (u) dead-time counter 1 dead-time counter 2 dead-time counter 3 tq0ccr1 register tq0ccr2 register tq0ccr3 register n (dead-time value) i (phase u data) j (phase v data) k (phase w data) i ii i j j j j k k k k m + 1 m + 1 basic phase u output width = (m + 1 ? i) 2 basic phase v output width = (m + 1 ? j) 2 basic phase w output width = (m + 1 ? k) 2 phase u output width = (m + 1 ? i) 2 ? n phase v output width = (m + 1 ? j) 2 ? n phase w output width = (m + 1 ? k) 2 ? n dead-time width = n phase u output width = (m + 1 ? i) 2 + n carrier cycle = (m + 1) 2 toqt2 pin output (v) toqb2 pin output (v) toqt3 pin output (w) toqb3 pin output (w) phase v output width = (m + 1 ? j) 2 + n phase w output width = (m + 1 ? k) 2 + n 0000h cautions 1. set the value ?m? of th e tq0ccr0 register in a range of 0002h m fffeh in the 6-phase pwm output mode. 2. only a value of up to ?m + 1? can be set to the tq0ccr1, tq0ccr2, and tq0ccr3 registers. 3. the output is 100% if ?0000h? is set to the tq0ccr1, tq0ccr2, and tq0ccr3 registers. the output is 0% if ?m + 1? is set to the tq0ccr1, tq0ccr2, and tq0ccr3 registers. the output (duty 50%) rises at the crest (m + 1) of the 16-bit counter and falls at the valley (0000h) if ?m + 2? or higher is set to the tq0ccr1, tq0ccr2, and tq0ccr3 registers. 4. if the operation value of an equation (such as (m + 1 ? i) 2 ? n) of the output width of phases u, v, and w is 0 or lower, it is conver ged to 0 (100% output). if the operation value is higher than ?(m + 1) 2?, it is co nverged to (m + 1) 2 (0% output).
chapter 12 motor control function user?s manual u16397ej3v0ud 567 (2) interrupt requests two types of interrupt requests are available: the intccq0 (crest interrupt) signal and intovq (valley interrupt) signal. the intccq0 and intovq signals can be cu lled by using the tq0opt1 register. for details of culling interrupts, see 12.4.3 interrupt culling function . ? intccq0 (crest interrupt) signal: interrupt signal in dicating match between the value of the 16-bit counter that counts up and the value of the tq0ccr0 register ? intovq (valley interrupt) signal: interrupt signal in dicating match between the value of the 16-bit counter that counts down and the value 0001h (3) rewriting registers during timer operation the following registers have a buffer register and can be rewritten in the anytime rewrite mode, batch rewrite mode, or intermittent batch rewrite mode. related unit register timer p2 tmp2 capture/compare register 0 (tp2ccr0) tmp2 capture/compare register 1 (tp2ccr1) timer q0 tmq0 capture/compare register 0 (tq0ccr0) tmq0 capture/compare register 1 (tq0ccr1) tmq0 capture/compare register 2 (tq0ccr2) tmq0 capture/compare register 3 (tq0ccr3) timer q0 option tmq0 option register 1 (tq0opt1) for details of the transfer function of the compare register, see 12.4.4 operation to rewrite register with transfer function . (4) counting-up/down operation of 16-bit counter the operation status of the 16-bit c ounter can be checked by using the tq0 cuf bit of tmq0 option register 0 (tq0opt0). status of tq0cuf bit status of 16-bit counter range of 16-bit counter value tq0cuf bit = 0 counting up 0000h ? m tq0cuf bit = 1 counting down (m + 1) ? 0001h remark m = set value of tq0ccr0 register
chapter 12 motor control function user?s manual u16397ej3v0ud 568 figure 12-7. interrupt and up/down flag 16-bit counter m (carrier data) tq0ccr0 register toqt1 pin output (u) toqb1 pin output (u) tq0ccr1 register tq0ccr2 register tq0ccr3 register i (phase u data) j (phase v data) k (phase w data) i ii i j j j j k k k k m + 1 m + 1 toqt2 pin output (v) toqb2 pin output (v) intccq0 (crest interrupt) intovq (valley interrupt) tq0cuf (up/down flag) toqt3 pin output (w) toqb3 pin output (w) 0000h
chapter 12 motor control function user?s manual u16397ej3v0ud 569 12.4.2 dead-time control (generat ion of negative-phase wave signal) (1) dead-time control mechanism in the 6-phase pwm output mode, compare register s 1 to 3 (tq0ccr1, tq0ccr2, and tq0ccr3) are used to set the duty factor, and compare register 0 (tq0ccr0) is used to set the cycle. by setting these four registers and by starting the operati on of tmq, three types of pwm output waves (basic 3-phase waves) with a variable duty factor are generated. these three pw m output waves are input to the timer q option unit (tmqop0) and their inverted signal with dead-time is created to generate three sets of (six) pwm waves. the tmqop0 unit consists of three 10-bit counters (dead-time counters 1 to 3) that operate in synchronization with the count clock of tmq0, and a tmq0 dead-time compar e register (tq0dtc) that specifies dead time. if ?a? is set to the tq0dtc register, the dead-time value is ?a?, and interval ?a? is created between a positive- phase wave and a negative-phase wave. figure 12-8. pwm output wave with dead time (1) (a) when dead time is in serted (tq0dtc register = a) a a 16-bit counter toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output (b) no dead time (t q0dtc register = 000h) 0 0 0000h 16-bit counter toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output remark m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 570 (2) pwm output of 0%/100% the v850e/ma3 is capable of 0% wave output and 100% wave output for pwm output. a low level is continuously output from toqtm pin as t he 0% wave output. a high level is continuously output from toqtm pin as the 100% wave output. the 0% wave is output by setting the tq0ccrm regi ster to ?m + 1? when the tq0ccr0 register = m. the 100% wave is output by setting t he tq0ccrm register to ?0000h?. rewriting the tq0ccrm register is enabled while the timer is operating, and 0% wave output or 100% wave output can be selected at the point of the crest interrupt (intccq0) and valley interrupt (intovq). remark m = 1 to 3 figure 12-9. 0% pwm output waveform (without dead time) i i 16-bit counter 0% output tq0ccr0 register tq0ccr1 register toqt1 pin output toqb1 pin output ccr1 buffer register i i i i i m i i i m + 1 m + 1 m + 1 m + 1 i i <4> <3> <2> <1> forced timing of timer output 0000h 0% output <1> 0% output is selected by the valley in terrupt (without a match with the 16-bit counter). the valley interrupt forcibly lowers t he timer output. this produces the 0% output. <2> 0% output is canceled by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this cancels the 0% output. <3> 0% output is selected by the crest inte rrupt (with a match with the 16-bit counter). the crest interrupt forcibly raises the timer outpu t, but lowering the timer output takes precedence when the value of the tq0ccrm register matches the value of the 16-bit counter. as a result, the 0% wave is output. <4> 0% output is canceled by the valley inte rrupt (without a match wit h the 16-bit counter). the valley interrupt forcibly lowers the timer output. this cancels the 0% output. remark means forced raising and means forced lowering.
chapter 12 motor control function user?s manual u16397ej3v0ud 571 figure 12-10. 100% pwm output waveform (without dead time) i i i i i i m i i i i i 0000h 0000h 0000h 0000h 0000h i 100% output 100% output <1> <2> <3> <4> 16-bit counter tq0ccr0 register tq0ccr1 register toqt1 pin output toqb1 pin output ccr1 buffer register forced timing of timer output <1> 100% output is selected by the valley in terrupt (with a match with the 16-bit counter). the valley interrupt forcibly lowers the timer output, but raising the timer output takes precedence when the value of the tq0ccrm register ma tches the value of the 16-bit count er. as a result, the 100% output is produced. <2> 100% output is canceled by the valley inte rrupt (without a match with the 16-bit counter). the valley interrupt forcibly lowers the timer output. this cancels the 100% output. <3> 100% output is selected by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this produces the 100% output. <4> 100% output is canceled by the crest inte rrupt (without a match wit h the 16-bit counter). the crest interrupt forcibly raises the ti mer output. this cancels the 100% output. remark means forced raising and means forced lowering.
chapter 12 motor control function user?s manual u16397ej3v0ud 572 figure 12-11. pwm output waveform from 0% to 100% and from 100% to 0% (without dead time) 0% output 0% output m 0000h 0000h 0000h 0000h 0000h 0000h m + 1 m + 1 m + 1 m + 1 0000h 100% output 100% output 100% output <1> <1> <2> <2> <1> 16-bit counter tq0ccr0 register tq0ccr1 register toqt1 pin output toqb1 pin output ccr1 buffer register forced timing of timer output <1> the valley interrupt selects 100% 0% or 0% 100% output. output can be selected from 100% 0% or 0% 100% immediately after the timer has been started. <2> the crest interrupt selects 100% 0% output. the crest interrupt selects 100% 0% output by using the timer output forced raising function and by a match between the 16-bit counter value and the tq0ccr0 register value. (3) output waveform in vicinity of 0% and 100% output if an interrupt is generated because the value of the 16-bi t counter matches the value of the compare register while dead time is being counted, the dead-time counter is cleared and starts its count operation again. the output waveform of dead-time control in the vicinity of 0% and 100% output is shown below.
chapter 12 motor control function user?s manual u16397ej3v0ud 573 figure 12-12. pwm output waveform with dead time (2) (a) 0% output (tq0ccrm register = m + 1, tq 0ccr0 register = m, tq0dtc register = a) 16-bit counter 000h (dead-time counter m does not count.) h l l 0000h toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output (b) in vicinity of 0% output (tq0ccrm register = i m + 1 ? a/2, tq0ccr0 register = m, tq0dtc register = a) dead-time counter is cleared and counts again. negative-phase output width: (m + 1 ? i) 2 + a (e.g., output width is 2 + a where tq0ccrm register = m.) l 16-bit counter 0000h toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output 000h (c) in vicinity of 100% output (tq0ccrm register = i a/2, tq0ccr0 register = m, tq0dtc register = a) counter is cleared and counts again. positive-phase output width: (m + 1 ? i) 2 ? a) (e.g., output width is 2 ? a where tq0ccrm register = 0001h.) 16-bit counter 0000h toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output 000h (d) 100% output (tq0ccrm regist er = 0000h, tq0ccr0 register = m, tq0dtc register = a) 000h (dead-time counter m does not count.) 16-bit counter 0000h toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output remark m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 574 (4) automatic dead-time width narro wing function (tq0opt2.tq0dtm bit = 1) the dead-time width can be automatically narrowed in the vicinity of 0% output or 100% output by setting the tq0opt2.tq0dtm bit to 1. by setting the tq0dtm bit to 1, the dead-time counter is not cleared, but starts down counting if the toqm (internal signal) output of timer q changes during dead-time counting. the following timing chart shows the operation of the dea d-time counter when the tq0dtm bit is set to 1. figure 12-13. operation of dead-time counter m (1) (a) in vicinity of 0% output (tq0ccrm register = i m + 1 ? a/2, tq0ccr0 register = m, tq0dtc register = a) dead-time counter m starts counting down. negative-phase wave output width: (m + 1 ? i) 4 (e.g., output width is 4 where tq0ccrm = m). 16-bit counter 0000h toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output 000h (b) in vicinity of 100% output (tq0ccrm register = i a/2, tq0ccr0 register = m, tq0dtc register = a) dead-time counter m starts counting down. positive-phase wave output width: (m + 1 ? i) 2 ? (i 2) (e.g., output width is m 2 ? 2 where tq0ccrm = 0001h.) note 16-bit counter 0000h toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output 000h note the output width of the first wave differs from t hat of the second and subsequent waves immediately after the tq0ctl0.tq0ce bit has been set. the fi rst wave is shorter than the second wave because the dead time is fully counted. remark m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 575 (5) dead-time control in case of incorrect setting usually, the toqm (internal signal) output of tmq0 chan ges only once during dead-time counting, only in the vicinity of 0% and 100% output. this section shows an example where the tq0ccr0 register (carrier cycle) and tq0dtc register (dead-time value) are incorrectly set. if these registers are incorrectly set, the toqm (internal signal) output of tmq0 c hanges more than once during dead-time counting. the following flowchart shows the 6-phase pwm output wave in this case. figure 12-14. operation of dead-time counter m (2) (a) when tq0opt2.tq0dtm bit = 0, tq0ccr0 register = 0006h, tq0dtc register = 000fh, tq0ccrm register = 0004h counter cleared counter is not cleared but continues counting. 000h 001h 002h 003h 004h 005h 006h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 00bh 00ch 00dh 00eh 00fh 000h 001h 16-bit counter toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output (b) when tq0opt2.tq0dtm bi t = 1, tq0ccr0 register = 0006h, tq0dtc register = 000fh, tq0ccrm register = 0002h starts counting down. output does not change and dead-time counter m continues counting down. 001h 002h 003h 004h 005h 006h 007h 008h 009h 00ah 009h 008h 007h 006h 005h 004h 003h 002h 001h 001h 002h 003h 004h 003h 002h 001h 000h 000h 16-bit counter toqm signal (internal signal) dead-time counter m toqtm pin output toqbm pin output remark m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 576 12.4.3 interrupt culling function ? the interrupts to be culled are intccq0 (cre st interrupt) and intovq (valley interrupt). ? the tq0opt1.tq0ice bit is used to enable output of the intccq0 interrupt and the number of times the interrupt is to be culled. ? the tq0opt1.tq0ioe bit is used to enable output of the intovq interr upt and the number of times the interrupt is to be culled. ? the tq0opt1.tq0id4 to tq0o pt1.tq0id0 bits are used to specify the number of co unts by which a specified interrupt is to be culled. the interrupt is culled for the duration of the specified number of counts and is generated at the next interrupt timing. ? the tq0rde bit of tq0opt2 is used to spec ify whether transfer is to be culled or not. if it is specified that transfer is to be culled, transfer is executed at the same timing as the interrupt output after culling. if it is specified that transfer is not to be cu lled, transfer is executed at the transfer timing after the tq0ccr1 register has been written. ? the tq0opt0.tq0cms bit is used to specify whether the registers with a tr ansfer function are batch rewritten or anytime rewritten. the values of the registers are updated in synchronization with transferring when the tq0cms bit is 0. when the tq0cms bit is 1, the values of t he registers are immediately updated when a new value is written to the registers. transfer is performed from the tq0ccrm register to the ccrm buffer register in synchronization with interrupt culling timing. caution when using the interrupt culling function in the batch rewrite mode (transfer mode), execute the function in the intermittent batch rewrite mode (transfer culling mode).
chapter 12 motor control function user?s manual u16397ej3v0ud 577 (1) interrupt culling operation figure 12-15. interrupt culling operation when tq 0opt1.tq0ice bit = 1, tq 0opt1.tq0ioe bit = 1, tq0opt2.tq0rde bit = 1 (cr est/valley interrupt output) 16-bit counter tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00000 (not culled) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00001 (1 mask) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00010 (2 masks) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00011 (3 masks) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00100 (4 masks) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00101 (5 masks) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00110 (6 masks) intccq0 signal intccq0 signal intccq0 signal intccq0 signal intccq0 signal intccq0 signal intccq0 signal intovq signal intovq signal intovq signal intovq signal intovq signal intovq signal intovq signal remark : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 578 figure 12-16. interrupt culling operation when tq 0opt1.tq0ice bit = 1, tq 0opt1.tq0ioe bit = 0, tq0opt2.tq0rde bit = 1 (crest interrupt output) 16-bit counter tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00000 (not culled) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00001 (1 mask) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00010 (2 masks) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00011 (3 masks) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00100 (4 masks) intccq0 signal intccq0 signal intccq0 signal intccq0 signal intccq0 signal intovq signal intovq signal intovq signal intovq signal intovq signal remark : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 579 figure 12-17. interrupt culling operation when tq 0opt1.tq0ice bit = 0, tq 0opt1.tq0ioe bit = 1, tq0opt2.tq0rde bit = 1 (valley interrupt output) 16-bit counter tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00000 (not culled) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00001 (1 mask) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00010 (2 masks) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00011 (3 masks) tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00100 (4 masks) intccq0 signal intccq0 signal intccq0 signal intccq0 signal intccq0 signal intovq signal intovq signal intovq signal intovq signal intovq signal remark : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 580 (2) to alternately output crest interrupt (intccq0) and valley interrupt (intovq) to alternately output the crest and valley interrupt s, set both the tq0opt1.tq 0ice and tq0opt1.tq0ioe bits to 1. figure 12-18. crest/valley interrupt output (a) tq0opt0.tq0cms bit = 0, tq0opt2.tq0rde bit = 1 (with transfer culling control) 16-bit counter tq0id4 to tq0id0 bits tq0id4 to tq0id0 bits (slave bit) intovq signal 00010 00010 00100 transfer timing of rewriting transfer culling count from 2 to 4 00100 intccq0 signal remarks 1. transfer is performed at the culled interrupt out put timing. the other transfer timing is ignored. 2. : culled interrupt (b) tq0cms bit = 1, tq0rde bit = 0 or 1 (without transfer control) 00010 00010 00100 reflected immediately 00100 timing of rewriting transfer culling count from 2 to 4 16-bit counter tq0id4 to tq0id0 bits tq0id4 to tq0id0 bits (slave bit) intovq signal intccq0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 581 (3) to output only crest interrupt (intccq0) set the tq0opt1.tq0ice bit to 1 and cl ear the tq0opt1.tq0ioe bit to 0. figure 12-19. crest interrupt output (a) tq0opt0.tq0cms bit = 0, tq0opt2.tq0rde bit = 1 (wit h transfer culling control) 00010 l 00010 00011 transfer 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tq0id4 to tq0id0 bits tq0id4 to tq0id0 bits (slave bit) intovq signal intccq0 signal remarks 1. transfer is performed at the culled interrupt out put timing. the other transfer timing is ignored. 2. : culled interrupt (b) tq0cms bit = 1, tq0rde bit = 0 or 1 (without transfer control) 00010 l reflected immediately 00011 00010 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tq0id4 to tq0id0 bits tq0id4 to tq0id0 bits (slave bit) intovq signal intccq0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 582 (4) to output only valley interrupt (intovq) clear the tq0opt1.tq0ice bit to 0 and set the tq0ioe bit to 1. figure 12-20. valley interrupt output (a) tq0opt0.tq0cms bit = 0, tq0opt2.tq0rde bit = 1 (wit h transfer culling control) 00010 l 00010 00011 transfer 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tq0id4 to tq0id0 bits tq0id4 to tq0id0 bits (slave bit) intovq signal intccq0 signal remarks 1. transfer is performed at the culled interrupt out put timing. the other transfer timing is ignored. 2. : culled interrupt (b) tq0cms bit = 1, tq0rde bit = 0 or 1 (without transfer control) 00010 l reflected immediately 00011 00010 00011 timing of rewriting transfer culling count from 2 to 3 16-bit counter tq0id4 to tq0id0 bits tq0id4 to tq0id0 bits (slave bit) intovq signal intccq0 signal remarks 1. rewriting is reflected immediately. the transfer timing is ignored. 2. : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 583 12.4.4 operation to rewrite re gister with transfer function the following seven registers are provided with a transfer f unction and used to control a motor. each of registers has a buffer register. ? tq0ccr0: register that specifies the cycle of the 16-bit counter (tmq) ? tq0ccr1: register that specifies the duty factor of toqt1 (u) and toqb1 (u) ? tq0ccr2: register that specifies the duty factor of toqt2 (v) and toqb2 (v) ? tq0ccr3: register that specifies the duty factor of toqt3 (w) and toqb3 (w) ? tq0opt1: register that specif ies the culling of interrupts ? tp2ccr0: register that specifies the a/d conversion start trigger generation timing (tmp2 during tuning operation) ? tp2ccr1: register that specifies the a/d conversion start trigger generation timing (tmp2 during tuning operation) the following three rewrite modes are provided in the registers with a transfer function. ? anytime rewrite mode this mode is set by setting the tq0opt0.tq0cms bit to 1. the setting of the tq0o pt2.tq0rde bit is ignored. in this mode, each compare register is updated independe ntly, and the value of the compare register is updated as soon as a new value is written to it. ? batch rewrite mode (transfer mode) this mode is set by clearing the tq0opt0.tq0cms bit to 0, the tq0opt1.tq0id4 to tq0opt1.tq0id0 bits to 00000, and the tq0opt2.tq0rde bit to 0. when data is written to the tq 0ccr1 register, data in the seven registers are transferred to the buffer register all at once at the next transfer timing. unless the tq0ccr1 register is rewritten, the transfer operation is not performed even if the other si x registers are rewritten. the transfer timing is the timing of each crest (match between the 16-bit counter value and tq0ccr0 register value) and valley (match between the 16-bit count er value and 0001h) regardless of the interrupt. ? intermittent batch rewrite mode (transfer culling mode) this mode is set by clearing the tq0opt0.tq0cms bi t to 0 and setting the tq0opt2.tq0rde bit to 1. when data is written to the tq0ccr1 register, the seven r egisters are transferred to the buffer register all at once at the next transfer timing. unless the tq0ccr1 register is rewritten, t he transfer operation is not performed even if the other six registers are rewritten. if interrupt culling is specified by the tq0opt1 register, the transfer timing is also culled as the interrupts are culled, and the seven registers are transferred all at once at the culled timing of crest interrupt (match between the 16-bit counter value and tq0ccr0 register value) or valley interrupt (match between the 16-bit counter value and 0001h). for details of the interrupt culling function, see 12.4.3 interrupt culling function .
chapter 12 motor control function user?s manual u16397ej3v0ud 584 (1) anytime rewrite mode this mode is set by setting the tq0opt0.tq0cms bit to 1. the setting of the tq0opt2.tq0rde bit is ignored. in this mode, the value written to each register with a transfer function is immediately transferred to an internal buffer register and compared with the val ue of the counter. if a register with transfer function is rewritten in this mode after the count value of the 16-bit counter matc hes the value of the tq0ccrm register, the rewritten value is not reflected because the next match is ignored after the first match has occurred. if the register is rewritten during up counting, the new register valu e becomes valid after the counter has started counting down. figure 12-21. timing of reflecting rewritten value operating clock (f xx ) tq0ccr0 register ba ccr0 buffer register ba note note after the register (tq0ccr0, tq0ccr2, tq0ccr3 , tq0opt1, tp2ccr0, or tp2ccr1) has been written, the written value is transferred to an intern al buffer register after four clocks of the operating clock. however, the value of only the tq0ccr1 register is transferred after 5 more clocks. (a) rewriting tq0ccr0 register even if the tq0ccr0 register is rewritten in the anyt ime rewrite mode, the new value may not be reflected in some cases. figure 12-22. example of rewriting tq0ccr0 register 16-bit counter <1> <2> <1> <2> rewriting during period <1> (rewriting during up counting) if the newly rewritten value is greater than the value of the 16-bit counter, there is no problem because it will match the value of the 16-bit counter. if the new value is less than the value of the 16-bit counter, it will not match the value of the counter. as a result, the 16- bit counter overflows and continues counting up from 0000h until it matches the register value again , and the correct pwm waveform is not output. rewriting during period <2> (r ewriting during down counting) a match with the value of the 16-bit counter is ignored during counting down. theref ore, the rewritten period value is reflected starting from counting up in the next cycle as a match point.
chapter 12 motor control function user?s manual u16397ej3v0ud 585 (b) rewriting tq0ccrm register figure 12-24 shows the timing of rewriting before the value of the 16-bit counter matches the value of the tq0ccrm register (<1> in figure 12-23 ), and figure 12-25 shows the timing of rewriting after the value of the 16-bit counter matches the value of the tq0ccrm register (<2> in figure 12-23). figure 12-23. basic operation of 16- bit counter and tq0ccrm register (a) basic figure 16-bit counter tq0ccrm register <1> <2> <1> <2> <1> <2> <1> <2> i ii ii remarks 1. i = set value of tq0ccrm register 2. m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 586 figure 12-24. example of rewriting tq0ccr1 to tq 0ccr3 registers (rewriting before match occurs) (a) if the tq0ccrm register is rewritten before its value matc hes the value of the 16-bit counter, the register value will match the value of the 16-b it counter after the register has been rewritten. consequently, the new register value is immediately reflected. 16-bit counter ccrm buffer register tq0ccrm register toqtm pin output i k k i k k ik (b) if a value less than the value of the 16-bit counter (great er if the counter is counting down) is written to the tq0ccrm register, the output waveform is as follows because the register value does not match the counter value. i i r r r r ir 16-bit counter ccrm buffer register tq0ccrm register toqtm pin output if the register value does not matc h the counter value, the toqtm pin output does not change. even if the value of the 16-bit counter does not match the value of the tq0ccrm register, the toqtm pin output always changes to the high level if the crest interrupt occurs and to the low level if the valley interrupt occurs. this is a function provided for 0% output and 100% output. for details, see 12.4.2 (2) pwm output of 0%/100% . remarks 1. i, r, k = set values of tq0ccrm register 2. m = 1 to 3
chapter 12 motor control function user?s manual u16397ej3v0ud 587 figure 12-25. example of rewriting tq0ccr1 to tq0ccr3 registers (rewriting after match occurs) ccrm buffer register 16-bit counter tq0ccrm register intccqm signal toqtm pin output i k k i i k k ik <1> <3> <2> <1> matching of the count value of the 16-bit counter and the value of the tq0ccrm register as a result of rewriting the register is ignored after a match signal has been generated, and the pwm output does not change. <2> even if the pwm output does not change, the interrupt generat ed upon a match between the 16-bit counter value and the tq0ccrm r egister value (intccqm) is output. <3> the next match between the 16-bit counter and tq0ccr m register is valid after the counter has changed its counting direction to up or down, and the pwm output changes. if the tq0ccrm register is rewritten after its value matc hes the value of the 16-bit counter, the next match is ignored after the first match occurs and the rewritten val ue is not reflected to the toqtm pin output. if the register is rewritten while the counter is counting down, the match that occurs after the counter starts counting down is valid (the match that occurs after the counter has started counting up is valid if the register is rewritten while the counter is counting up). remarks 1. i, k = set value of tq0ccrm register 2. m = 1 to 3 (c) rewriting tq0opt1 register the interrupt culling counter is cleared when the tq0opt1 register is wri tten. when the interrupt culling counter has been cleared, the measur ed number of times the interrupt has occurred is discarded. consequently, the interrupt generation interval is temporarily extended. to avoid this operation, rewrite the tq0opt1 register in the intermittent batch rewrite mode (transfer culling mode). for details of rewriting the tq0opt1 register, see 12.4.3 interrupt culling function .
chapter 12 motor control function user?s manual u16397ej3v0ud 588 (2) batch rewrite mode (transfer mode) this mode is set by clearing the tq0opt0.tq0cms bit to 0, the tq0opt1.tq0id4 to tq0opt1.tq0id0 bits to 00000, and the tq0opt2.tq0rde bit to 0. in this mode, the values written to each compare register are transferred to the internal buffer register all at once at the transfer timing and compared with the counter value. (a) rewriting procedure if data is written to the tq0ccr1 register, the va lues set to the tq0ccr0 to tq0ccr3, tq0opt1, tp2ccr0, and tp2ccr1 registers are transferred all at once to the internal buffer register at the next transfer timing. therefore, write to the tq0ccr1 register last. writing to the register is prohibited after the tq0ccr1 register has been written and before the transfer timing is generated (until the crest (match between the 16-bit counter value and tq0ccr0 register value) or the valley (match between the 16-bit counter value and 0001h)). the op eration procedure is as follows. <1> rewriting the tq0ccr0, tq0ccr2, tq0ccr3, tq0opt1, tp2ccr0, and tp2ccr1 registers do not rewrite registers that do not have to be rewritten. <2> rewriting the tq0ccr1 register rewrite the same value to the register even when it is not necessary to rewrite the tq0ccr1 register. <3> holding the next rewriting pending until the transfer timing is generated rewrite the register next time after the intovq or intccq0 interrupt has occurred. <4> return to <1>.
chapter 12 motor control function user?s manual u16397ej3v0ud 589 figure 12-26. basic operation in batch mode intovq signal intccq0 signal ccr2 buffer register ccr3 buffer register opt1 buffer register tq0ccr2 register tq0ccr3 register tq0opt1 register 16-bit counter (tmq0) transfer timing tq0ccr0 register tq0ccr1 register ccr0 buffer register ccr1 buffer register & 16-bit counter (tmp2) transfer timing tp2ccr0 register tp2ccr1 register ccr0 buffer register ccr1 buffer register [operation of tmq0] write the tq0ccr1 register the target timing is the first transfer timing after a write to the tq0ccr1 register. the values are transferred all at once at the transfer timing. [operation of tmp2] write the tq2ccr1 register the target timing is the first transfer timing after a write to the tq2ccr1 register. the values are transferred all at once at the transfer timing.
chapter 12 motor control function user?s manual u16397ej3v0ud 590 (b) rewriting tq0ccr0 register when rewriting the tq0ccr0 register in the batch re write mode, the output waveform differs depending on whether transfer occurs at the crest (match between the 16-bit counter value and tq0ccr0 register value) or at the valley (match between the 16-bit counter value and 0001h). usually, it is recommended to rewrite the tq0ccr0 register while the 16-bit counter is counting down, and transfer the register value at the transfer timing of the crest timing. figure 12-28 shows an example of rewriting the tq0c cr0 register while the 16-bit counter is counting up (during period <1> in figure 12-27). figure 12-29 sh ows an example of rewriting the tq0ccr0 register while the counter is counting down (during period <2> in figure 12-27). figure 12-27. basic operation of 16-bit counter <1> <2> <1> <2> 16-bit counter the transfer timing in figure 12-28 is at the point wher e the crest timing occurs. while the 16-bit counter is counting down, the cycle changes and an asymmetrical triangular wave is output. because the cycle changes, rewrite the duty factor (voltage data value).
chapter 12 motor control function user?s manual u16397ej3v0ud 591 figure 12-28. example of rewriting tq 0ccr0 register (during up counting) (a) m > n 16-bit counter transfer timing ccr0 buffer register tq0ccr0 register tq0ccr1 register ccr1 buffer register toqt1 pin output intccq0 signal intovq signal kk k k i k k n + 1 n + 1 n n m m 0000h 0000h m i i k k (b) m < n 16-bit counter transfer timing ccr0 buffer register tq0ccr0 register tq0ccr1 register ccr1 buffer register toqt1 pin output intccq0 signal intovq signal kk i n + 1 n + 1 n n m m 0000h 0000h m i i k k remarks 1. if transfer (match between the value of the 16- bit counter and the value of the ccr0 buffer register) occurs in the 6-phase pwm output mode, the value of the tq0ccr0 register plus 1 is loaded to the 16-bit counter. in this way, t he expected wave can be output even if the cycle value is changed at the transfer timing of the cres t (match between the 16-bit counter value and the tq0ccr0 register value) timing. 2. m: value of ccr0 buffer register before rewriting n: value of ccr0 buffer register after rewriting
chapter 12 motor control function user?s manual u16397ej3v0ud 592 figure 12-29. example of rewriting tq0 ccr0 register (during down counting) 16-bit counter transfer timing tq0ccr0 register tq0ccr1 register ccr1 buffer register ccr0 buffer register toqt1 pin output intccq0 signal intovq signal k kk k ii n n m m + 1 n + 1 0000h 0000h m i i k k because the next transfer timing is at the point of the valley (match between the 16-bit counter value and 0001h), the cycle value changes from the next cycle and output of a symmetrical triangular wave is maintained. because the cycle changes, rewrite the duty value (voltage data value) as required.
chapter 12 motor control function user?s manual u16397ej3v0ud 593 (c) rewriting tq0ccrm register figure 12-30. example of rewriting tq0ccrm register transfer timing tq0ccrm register 16-bit counter ccrm buffer register toqtm register intccqm signal k k k i i rr r r i 0000h <1> <2> <1> <2> rewriting during period <1> (rewriting during counting up) because the tq0ccrm register value is transferred at the transfer timing of the cr est (match between the 16- bit counter value and tq0ccrm register value), an asymmetrical triangular wave is output. rewriting during period <2> (rewriting during counting down) because the tq0ccrm register value is transferred at the transfer timing of the valley (match between the 16-bit counter value and 0001h), a symmetrical triangular wave is output. remark m = 1 to 3 (d) transferring tq0o pt1 register value do not set the tq0opt1.tq0id4 to tq0opt1.tq0id0 bits to other than 00000. when using the interrupt culling function, rewrite the tq0opt1 register in t he intermittent batch rewrite mode (transfer culling mode). for details of rewriting the tq0opt1 register, see 12.4.3 interrupt culling function .
chapter 12 motor control function user?s manual u16397ej3v0ud 594 (3) intermittent batch rewrit e mode (transfer culling mode) this mode is set by clearing the tq0opt0.tq0cms bi t to 0 and setting the tq0opt2.tq0rde bit to 1. in this mode, the values written to each compare register are transferred to the internal buffer register all at once after the culled transfer timing and compared with the counter value. the transfer timing is the timing at which an interrupt is generated (intccq 0, intovq) by interrupt culling. for details of the interrupt culling function, see 12.4.3 interrupt culling function . (a) rewriting procedure if data is written to the tq0ccr1 register, t he tq0ccr0 to tq0ccr3, tq0opt1, tp2ccr0, and tp2ccr1 registers are transferred all at once to the inte rnal buffer register at the next transfer timing. therefore, write to the tq0ccr1 register last. writ ing to the register is prohibited after the tq0ccr1 register has been written until the transfer timing is generated (until the intovq or intccq0 interrupt occurs). the operation procedure is as follows. <1> rewrite the tq0ccr0, tq0ccr2, tq0ccr3, tq0opt1, tp2ccr0, and tp2ccr1 registers. do not rewrite registers that do not have to be rewritten. <2> rewrite the tq0ccr1 register. rewrite the same value to the register even when it is not necessary to rewrite the tq0ccr1 register. <3> hold the next rewriting pending until the transfer timing is generated. perform the next rewrite after the into vq or intccq0 interrupt has occurred. <4> return to <1>.
chapter 12 motor control function user?s manual u16397ej3v0ud 595 figure 12-31. basic operation in intermittent batch rewrite mode intovq signal intccq0 signal ccr2 buffer register ccr3 buffer register opt1 buffer register tq0ccr2 register tq0ccr3 register tq0opt1 register 16-bit counter (tmq0) transfer timing tq0ccr0 register tq0ccr1 register ccr0 buffer register ccr1 buffer register & 16-bit counter (tmp2) transfer timing tp2ccr0 register tp2ccr1 register ccr0 buffer register ccr1 buffer register [tmq0 operation] write the tq0ccr1 register. rewrite the register at the tr ansfer timing that is generated after the tq0ccr1 register has been rewritten. the registers are transferred all at once at the transfer timing. the transfer timing is also culled as the interrupts are culled. [tmp2 operation] write the tq2ccr1 register. rewrite the register at the tr ansfer timing that is generated after the tq2ccr1 register has been rewritten. the registers are transferred all at once at the transfer timing. the transfer timing is also culled as the interrupts are culled. remark this is an example of the operation when the tq 0opt1.tq0ice bit = 1, tq 0opt1.tq0ioe bit = 1, tq0opt1.tq0id4 to tq0o pt1.tq0id0 bits = 00001.
chapter 12 motor control function user?s manual u16397ej3v0ud 596 (b) rewriting tq0ccr0 register when rewriting the tq0ccr0 register in the interm ittent batch mode, the output waveform differs depending on where the occurrence of the crest or valle y interrupt is specified by the interrupt culling setting. the following figure illustrates the change of the output waveform when interrupts are culled. figure 12-32. rewriting tq0ccr0 regi ster (when crest interrupt is set) 16-bit counter transfer timing tq0ccr0 register tq0ccr1 register ccr0 buffer register ccr1 buffer register intccq0 signal toqt1 pin output intovq signal i l i m m 0000h 0000h m n n k k k k kk n + 1 i i i the transfer timing is generated when the crest interr upt occurs, the cycle of up counting and down counting changes, and an asymmetrical triangular wave is output. remarks 1. this is an example of the operation when the tq0opt1.tq0ice bit = 1, tq0opt1.tq0ioe bit = 0, tq0opt1.tq0id4 to tq 0opt1.tq0id0 bits = 00001. 2. : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 597 figure 12-33. rewriting tq0ccr0 regi ster (when valley interrupt is set) i l i i m 0000h 0000h m n n k k kk m + 1 m + 1 n + 1 i i i 16-bit counter transfer timing tq0ccr0 register tq0ccr1 register ccr0 buffer register ccr1 buffer register intccq0 signal toqt1 pin output intovq signal the transfer timing is generated when the valley interrupt occurs, the cycle of up counting becomes same as cycle of down counting, and a symmetrical triangular wave is output. remarks 1. this is an example of the operation when the tq0opt1.tq0ice bit = 0, tq0opt1.tq0ioe bit = 1, tq0opt1.tq0id4 to tq 0opt1.tq0id0 bits = 00001. 2. : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 598 (c) rewriting tq0ccr1 to tq0ccr3 registers ? transfer at crest when crest interrupt is set because the register is transferred at the transfer ti ming of the crest interrupt, an asymmetrical triangular wave is output. figure 12-34. rewriting tq0ccr1 register (tq0opt1.tq0ice bit = 1, tq0opt1.tq0ioe bit = 0, tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00001) 16-bit counter transfer timing tq0ccr1 register ccr1 buffer register toqt1 pin output i i i r ik transfer at crest interrupt k k i intccq0 signal intovq signal remark : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 599 ? transfer at valley when valley interrupt is set because the register is transferred at the transfer timi ng of the valley interrupt, a symmetrical triangular wave is output. figure 12-35. rewriting tq0ccr1 register (tq0opt1.tq0ice bit = 1, tq0opt1.tq0ioe bit = 1, tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00001) 16-bit counter transfer timing tq0ccr1 register ccr1 buffer register toqt1 pin output i i r ik transfer at valley interrupt transfer at valley interrupt r k k k i intccq0 signal intovq signal remark : culled interrupt (d) rewriting tq0opt1 register because a new interrupt culling value is transferred when the value of the interrupt culling counter matches the value of the 16-bit counter, the next interrupt and those that follow occur at the set interval. for details of rewriting the tq0opt1 register, see 12.4.3 interrupt culling function .
chapter 12 motor control function user?s manual u16397ej3v0ud 600 (4) rewriting tq0opt0.tq0cms bit the tq0cms bit can select the anytime rewrite mode and batch rewrite mode. this bit can be rewritten during timer operation (when tq0ctl0.tq0ce bit = 1). howeve r, the operation and caution illustrated in figure 12- 31 are necessary. if the tq0ccr1 register is written when the tq0cms bit is cleared to 0, a transfer request signal (internal signal) is set. when the transfer request signal is set, the register is tr ansferred at the next transfer timing, and the transfer request signal is cleared. this transfer request signal is also cleared when the tq0cms bit is set to 1. figure 12-36. rewriting tq0cms bit 16-bit counter transfer request signal transfer timing <1> <2> <3> <4> <5> <6> tq0ccr1 register 0000h ccr1 buffer register write signal of tq0ccr1 clear clear tq0cms bit ir rs s k i <1> if the tq0ccr1 register is rewritten when the tq 0cms bit is 0, the transfer request signal is set. if the tq0cms bit is set to 1 in this status, the transfer request signal is cleared. <2> the register is not transferred because the tq0cms bit is set to 1 and the transfer request signal is cleared. <3> the transfer request signal is not set even if the tq 0ccr1 register is written when the tq0cms bit is 1. <4> the transfer request signal is not set even if the tq 0ccr1 register is written when the tq0cms bit is 1, so even if the tq0cms bit is cleared to 0, transfer does not occur at the subsequent transfer timing. <5> the transfer request signal is set if the tq0ccr1 register is written when the tq0cms bit is 0. transfer is performed at the subsequent transfer timing and the transfer request signal is cleared. <6> once transfer has been performed, the transfer re quest signal is cleared. therefore, transfer is not performed at the next transfer timing.
chapter 12 motor control function user?s manual u16397ej3v0ud 601 12.4.5 tmp2 tuning operation for a/d conversion start trigger signal output this section explains the tuning operation of tmp2 and tmq0 in the 6-phase pwm output mode. in the 6-phase pwm output mode, the tuning operation is performed with tmq0 serving as the master and tmp2 as a slave. the conversion start trigger signal of the a/ d converter can be set as the a/d conversion start trigger source by the intccp20 and intccp21 signals of tmp2 and the intovq and intccq0 signals of tmq0. (1) tuning operation starting procedure the tmp2 and tmq0 registers should be set using the fo llowing procedure to perform the tuning operation. (a) setting of tmp2 register (s top the operations of tmq0 and tm p2 (by clearing the tq0ctl0.tq0ce bit and tp2ctl0.tp2ce bit to 0)). ? set the tp2ctl1 register to 85h (set the tuning operation slave mode and free-running timer mode). ? clear the tp2opt0 register to 00h (select the compare register). ? set an appropriate value to the tp2ccr0 and tp2ccr1 registers (set the default value for comparison for starting the operation). (b) setting of tmq0 register ? set the tq0ctl1 register to 07h (ma ster mode and 6-phase pwm output mode). ? set an appropriate value to the tq0ioc0 regist er (set the output mode of toqt1 to toqt3). however, clear the tq0ol0 bit to 0 and set the tq0oe0 bit to 1 (enable positive phase output). unless this setting is made, the crest interrupt (intccq0) and valley inte rrupt (intovq) do not occur. consequently, the conversion start trigger signal of the a/d converter is not correctly generated. ? clear the tq0opt0 register to 00h (select the compare register). ? set an appropriate value to the tq0ccr0 to tq0ccr3 registers (set the default value for comparison for starting the operation). ? set the tq0ctl0 register to 0xh (clear the tq 0ce bit to 0 and set the operating clock of tmq0). the operating clock of tmq0 set by the tq0ctl0 register is also supplied to tmp2, and the count operation is performed at the same ti ming. the operating clock of tmp2 set by the tp2ctl0 register is ignored. (c) setting of tmqop0 (tmq0 option) register ? set an appropriate value to the tq0opt1 and tq0o pt2 registers. ? set an appropriate value to the tq0ioc3 regist er (set toqb1 to toqb3 in the output mode). ? set an appropriate value to the tq0dtc register (s et the default value for comparison for starting the operation). (d) setting of alternate function ? set the alternate function to the port by setting the port control mode. (e) set the tp2ce bit to 1 and set the tq0ce bit to 1 immediately after that to start the 6-phase pwm output operation rewriting the tq0ctl0, tq 0ctl1, tp0ctl0, and tp0ctl1 registers is prohibited during operation. the operation and the pwm output waveform are not guarant eed if any of these registers is rewritten during operation. however, rewriting the tq0ctl0.tq0ce bit to clear it is permitted. manipulating (reading/writing) the other tmq0, tmp2, and tmq0 option registers is prohibited until the tp2ctl0.tp2ce bit is set to 1 and then the tq0ce bit is set to 1. caution when tuning tmp2 in the 6-phase pwm mode, output of the top20 and top21 pins is disabled. clear the tp2ioc0.tp2oe0 and tp2ioc0.tp2oe1 bits to 0.
chapter 12 motor control function user?s manual u16397ej3v0ud 602 (2) tuning operation clearing procedure to clear the tuning operation and exit the 6-phase pwm output mode, set the tmp2 and tmq0 registers using the following procedure. <1> clear the tq0ctl0.tq0ce bit to 0 and stop the timer operation. <2> clear the tp2ctl0.tp2ce bit to 0 so that tmp2 can be separated. <3> stop the timer output by using the tq0ioc0 and tp2ioc0 registers. <4> clear the tp2ctl1.tp2sye bit to 0 to clear the tuning operation. caution manipulating (reading/writing) the other tm q0, tmp2, and tmq0 option registers is prohibited until the tq0ce bit is set to 1 and then the tp1ce bit is set to 1. (3) when not tuning tmp2 when the match interrupt signal of tmp2 is not necessary as the conversion trigger s ource that starts the a/d converter, tmp2 can be used independently as a separate timer without being tuned. in this case, the match interrupt signal of tmp2 cannot be used as a trigger so urce to start a/d conversion in the 6-phase pwm output mode. therefore, fix the tq0opt2.tq 0at2 and tq0opt2.tq0at3 bits to 00. the other control bits can be used in t he same manner as when tmp2 is tuned. if tmp2 is not tuned, the compare registers (tp2ccr0 and tp2ccr1) of tmp2 are not affected by the setting of the tq0opt0.tq0cms and tq0opt2.tq0rde bit. for the initia lization procedure when tmp2 is not tuned, see (b) to (e) in 12.4.5 (1) tuning operation starting procedure . (a) is not necessary because it is a step used to set tmp2 for the tuning operation. (4) basic operation of tmp2 during tuning operation the 16-bit counter of tmp2 only counts up. the 16-bi t counter is cleared by the set cycle value of the tq0ccr0 register and starts counting fr om 0000h again. the count value of this counter is the same as the value of the 16-bit counter of tmq0 when it counts up. however, it is not the same when the 16-bit counter of tmp2 counts down. ? when tmq0 counts up (same value) 16-bit counter of tmq0: 0000h m (up counting) 16-bit counter of tmp2: 0000h m (up counting) ? when tmq0 counts down (not same value) 16-bit counter of tmq0: m + 1 0001h (down counting) 16-bit counter of tmp2: 0000h m (up counting)
chapter 12 motor control function user?s manual u16397ej3v0ud 603 figure 12-37. tmp2 during tuning operation r s r s r s r s 16-bit counter of tmq0 16-bit counter of tmp2 m (carrier data) tq0ccr0 register toqt1 pin output (u) toqb1 pin output (u) tq0ccr1 register tp2ccr0 register tp2ccr1 register intccp20 signal intccp21 signal tq0ccr2 register tq0ccr3 register i (phase u data) s (a/d conversion start trigger timing 2) r (a/d conversion start trigger timing 3) j (phase v data) k (phase w data) i ii i j j j j k k k k m + 1 m + 1 toqt2 pin output (v) toqb2 pin output (v) toqt3 pin output (w) tqtadt signal toqb3 pin output (w) note note m m m note the tqtadt signal is masked by the tq 0opt2.tq0atm2 and tq0opt 2.tq0atm3 bits.
chapter 12 motor control function user?s manual u16397ej3v0ud 604 12.4.6 a/d conversion start trigger output function the v850e/ma3 has a function to select four trigger sources (intovq, intccq0, intccp20, intccp21) to generate the a/d conversion start trigger signal (tqtadt). the trigger sources are specified by the tq0opt2.tq0at0 to tq0opt2.tq0at3 bits. ? tq0at0 bit = 1: a/d conversion start trigger signal generated when intovq (counter underflow) occurs. ? tq0at1 bit = 1: a/d conversion start trigger signal generated when intccq0 (cycle match) occurs. ? tq0at2 bit = 1: a/d conversion start trigger signal generated when in tccp20 (match of tp2ccr0 register of tmp2 during tuning operation) occurs. ? tq0at3 bit = 1: a/d conversion start trigger signal generated when in tccp21 (match of tp2ccr1 register of tmp2 during tuning operation) occurs. the a/d conversion start trigger signals selected by the tq 0at0 to tq0at3 bits are ored and output. therefore, two or more trigger sources can be specified at the same time. the intovq and intccq0 signals selected by the tq0at0 and tq0at1 bits are culled interrupt signals. therefore, these signals are output after the interrupts have been culled and, unless interrupt output is enabled (tq0opt1.tq0ice, tq0opt1.tq0ioe bits), the a/ d conversion start trigger signal is not output. the trigger sources (intccp20 and intccp21) from tmp2 have a function to mask the a/d conversion start trigger signal depending on the status of the count-up/count -down of the 16-bit counter, if so set by the tq0at2 and tq0at3 bits. ? tq0atm2 bit: correspond to the tq0at2 bit and c ontrol intccp20 (match interrupt signal) of tmp2. ? tq0atm2 bit = 0: the a/d conversion start trigger signal is output when the 16-bit counter counts up (tq0opt0.tq0cuf bit = 0), and the a/d conversi on start trigger signal is not output when the 16-bit counter counts down (tq0opt0.tq0cuf bit = 1). ? tq0atm2 bit = 1: the a/d conversion start trigger signal is output when the 16-bit counter counts up (tq0opt0.tq0cuf bit = 1), and the a/d conversi on start trigger signal is not output when the 16-bit counter counts down (tq0opt0.tq0cuf bit = 0). ? tq0atm3 bit: correspond to the tq0at3 bit and c ontrol intccp21 (match interrupt signal) of tmp2. ? tq0atm3 bit = 0: the a/d conversion start trigger signal is output when the 16-bit counter counts up (tq0opt0.tq0cuf bit = 0), and the a/d conversi on start trigger signal is not output when the 16-bit counter counts down (tq0opt0.tq0cuf bit = 1). ? tq0atm3 bit = 1: the a/d conversion start trigger signal is output when the 16-bit counter counts up (tq0opt0.tq0cuf bit = 1), and the a/d conversi on start trigger signal is not output when the 16-bit counter counts down (tq0opt0.tq0cuf bit = 0). the tq0atm3, tq0atm2, and tq0at3 to tq 0at0 bits can be rewritten while the timer is operating. if the bit that sets the a/d conversion start trigger signal is rewritten wh ile the timer is operating, the new setting is immediately reflected on the output status of the a/d conversion start trigger signal. these control bits do not have a transfer function and can be used only in the anytime rewrite mode.
chapter 12 motor control function user?s manual u16397ej3v0ud 605 cautions 1. the a/d conversion start trigger signal out put that is set by the tq0at2 and tq0at3 bits can be used only when tmp2 is performing a tuning operation as the slave timer of tmq0. if tmq0 and tmp2 are not performing a tuning operation, or if a mode other than the 6-phase pwm output mode is used, the output cannot be guaranteed. 2. the tmq0 signal output is inte rnally used to identify whethe r the 16-bit counter is counting up or down. therefore, enable toq0 pin output by clearing the tq0ioc0.tq0ol0 bit to 0 and setting the tq0ioc0.tq0oe0 bit to 1.
chapter 12 motor control function user?s manual u16397ej3v0ud 606 figure 12-38. example of a/d conversion start trigge r (tqtadt) signal output (tq0opt1.tq0ice bit = 1, tq0opt1.tq0ioe bit = 1, tq0opt1. tq0id4 to tq0opt1.tq0id0 bits = 00000: without interrupt culling) 16 -bit counter intovq signal intccp20 signal intccp21 signal tq0cuf bit tqtadt signal tqtadt signal tqtadt signal tqtadt signal tqtadt signal tqtadt signal tqtadt signal tqtadt signal tq0at3 to tq0at0 bits = 0001 (intovq signal output) tq0at3 to tq0at0 bits = 0010 (intccq0 signal output) tq0at3 to tq0at0 bits = 0100, tq0atm2 bit = 0 (intccp20 signal output during counting up) tq0at3 to tq0at0 bits = 0100, tq0atm2 bit = 1 (intccp20 signal output during counting down) tq0at3 to tq0at0 bits = 1000, tq0atm3 bit = 1 (intccp21 signal output during counting down) tq0at3 to tq0at0 bits = 0011 (setting to output a/d conversion start trigger signal when both crest and valley interrupts occur) tq0at3 to tq0at0 bits = 1100, tq0atm3 bit = 1, tq0atm2 bit = 0 (intccp20 and intccp21 signals ored for output. setting to output a/d conversion start trigger signal when match interrupt of tmp2 occurs when counter is counting up or down) tq0at3 to tq0at0 bits = 1000, tq0atm3 bit = 0 (intccp21 signal output during counting up) intccq0 signal
chapter 12 motor control function user?s manual u16397ej3v0ud 607 figure 12-39. example of a/d conversion start trigge r (tqtadt) signal output (tq0opt1.tq0ice bit = 0, tq0opt1.tq0ioe bit = 1, tq0opt1.tq 0id4 to tq0opt1.tq0id0 bits = 00010: with interrupt culling) (1) 16 -bit counter intovq signal tqtadt signal tq0at3 to tq0at0 bits = 0011 (both intccq0 and intovq signals are selected but crest interrupt (intccq0) is not output because interrupt culling is specified.) intccq0 signal l remark : culled interrupt figure 12-40. example of a/d conversion start trigge r (tqtadt) signal output (tq0opt1.tq0ice bit = 0, tq0opt1.tq0ioe bit = 1, tq0opt1.tq 0id4 to tq0opt1.tq0id0 bits = 00010: with interrupt culling) (2) 16 -bit counter intovq signal tqtadt signal tq0at3 to tq0at0 bits = 0101, tq0atm2 bit = 1 tq0cuf bit intccp21 signal intccp20 signal intccq0 signal l caution the intccq0 signal is cull ed but the intccp20 signal is not. remark : culled interrupt
chapter 12 motor control function user?s manual u16397ej3v0ud 608 (1) operation under boundary condition (operation when 16-bit counter matches intccp20 signal) table 12-3. operation when tq0ccr0 register = m, tq0at2 bit = 1, tq0atm2 bit = 0 (up counting period selected) value of tp2ccr0 register value of 16-bit counter of tmq0 value of 16-bit counter of tmp2 status of 16-bit counter of tmq0 tqtadt signal output by intccp20 signal 0000h 0000h 0000h ? output 0000h m + 1 0000h ? not output 0001h 0001h 0001h count-up output 0001h m 0001h count-down not output m m m count-up output m 0001h m count-down not output table 12-4. operation when tq0ccr0 register = m, tq0at2 bit = 1, tq0atm2 bit = 1 (down counting period selected) value of tp2ccr0 register value of 16-bit counter of tmq0 value of 16-bit counter of tmp2 status of 16-bit counter of tmq0 tqtadt signal output by intccp20 signal 0000h 0000h 0000h ? not output 0000h m + 1 0000h ? output 0001h 0001h 0001h count-up not output 0001h m 0001h count-down output m m m count-up not output m 0001h m count-down output caution the tp2ccrm register enables setting of ?0? to ?m? when the tq0ccr0 register = m. setting of a value of ?m + 1? or higher is prohibited. if a value higher than ?m + 1? is set, the 16-bit c ounter of tmp2 is cleared by ?m?. therefore, the tqtadt signal is not output.
user?s manual u16397ej3v0ud 609 chapter 13 watchdog timer functions 13.1 functions the watchdog timer has the following operation modes. ? watchdog timer ? interval timer the following functions are realized fr om the above-listed operation modes. ? generation of non-maskable interrupt request si gnal (intwdt) upon overflow of watchdog timer ? generation of system reset signal (wdt res) upon overflow of watchdog timer ? generation of maskable interrupt request signal (intwdtm) upon overflow of interval timer remark select whether to use the watchdog timer in the wa tchdog timer mode or the interval timer mode using the wdtm register. figure 13-1. block diagram of watchdog timer 13-bit divider run wdcs0 to wdcs2 bits wdtm3, wdtm4 bits clear clear 8-bit counter output controller f xw f xw /2 13 f xw /2 11 f xw /2 10 f xw /2 9 f xw /2 8 f xw /2 7 f xw /2 6 f xw /2 5 selector ovf intwdtm intwdt wdtres remark intwdtm: request signal for maskable interrupt by watchdog timer overflow intwdt: request signal for non-maskable interrupt by watchdog timer overflow wdtres: reset signal by watchdog timer overflow f xw = f xx /2: watchdog timer clock frequency
chapter 13 watchdog timer functions user?s manual u16397ej3v0ud 610 13.2 configuration the watchdog timer consists of the following hardware. table 13-1. configuration of watchdog timer item configuration control registers watchdog timer cl ock select register (wdcs) watchdog timer mode register (wdtm) watchdog timer reset status register (wdres) 13.3 control registers the registers that control the watchdog timer are as follows. ? watchdog timer clock select register (wdcs) ? watchdog timer mode register (wdtm) ? watchdog timer reset status register (wdres) (1) watchdog timer clock select register (wdcs) the wdcs register sets the overflow time of the watchdog timer and the interval timer. this register can be read or written in 8-bit units. reset input clears this register to 00h. 0 wdcs 0 0 0 0 wdcs2 wdcs1 wdcs0 wdcs2 0 0 0 0 1 1 1 1 overflow time of watchdog timer/interval timer wdcs1 0 0 1 1 0 0 1 1 wdcs0 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff6c1h 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx 2 18 /f xx 2 19 /f xx 2 20 /f xx 2 22 /f xx 60 mhz 80 mhz 204.8 s 409.6 s 819.2 s 1.638 ms 3.277 ms 6.554 ms 13.11 ms 52.43 ms 273.1 s 546.1 s 1.092 ms 2.185 ms 4.369 ms 8.738 ms 17.48 ms 69.91 ms f xx remark f xw = f xx /2: watchdog timer clock frequency
chapter 13 watchdog timer functions user?s manual u16397ej3v0ud 611 (2) watchdog timer mode register (wdtm) the wdtm register sets the watchdog timer operat ion mode and enables/disables count operations. this register is a special register that c an be written only in a specific sequence (see 3.4.9 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. run stop counting clear counter and start counting run 0 1 selection of operation mode of watchdog timer note 1 wdtm 0 0 wdtm4 wdtm3 0 0 0 after reset: 00h r/w address: fffff6c2h interval timer mode (upon overflow, maskable interrupt intwdtm is generated.) watchdog timer mode 1 (upon overflow, non-maskable interrupt intwdt is generated.) watchdog timer mode 2 (upon overflow, reset operation wdtres is started.) wdtm4 0 0 1 1 wdtm3 0 1 0 1 selection of operation mode of watchdog timer note 2 <7> notes 1. once the run bit is set (to 1), it cannot be cleared (to 0) by software. therefore, when counting is started, it cannot be stopped except by reset input. 2. once the run bit is set to 1, the wdtm3 and wd tm4 bits cannot be cleared (to 0) by software and can be cleared only by reset.
chapter 13 watchdog timer functions user?s manual u16397ej3v0ud 612 (3) watchdog timer reset status register (wdres) when the v850e/ma3 has been reset, the wdres register is used to check whether it has been reset by the watchdog timer (wdtres) or not. the wdres register is a special register . the status of wdtres is shown below. this register is set only in 8-bit units when it is written, and in 8-bit or 1-bit units when it is read. to write the wdres register, a specific sequence usin g the prcmd register as the command register is required. if the register is written in an illegal sequenc e, the written data is invalid and the protect error bit (sys.prerr bit) is set to 1, and the write operation is not performed. reset input clears this register to 00h. 0 wdtres not generated wdtres generated wresf 0 1 wdtres detection flag wdres 0 0 0 0 0 0 wresf after reset: 00h r/w address: fffff82ah setting (1) condition: reset signal generation due to watchdog timer (wdt) overflows clearing (0) condition: writing 0 by instruction or reset pin input only 0 can be written to the wresf bit. <0> caution before writing 0 to the wresf bit, check if the wresf bit is 1 (read) to avoid a conflict with the flag setting. remark the wresf bit can be read/written but it can on ly cleared by writing 0 and cannot be operated by writing 1.
chapter 13 watchdog timer functions user?s manual u16397ej3v0ud 613 13.4 operation 13.4.1 operation as watchdog timer the watchdog timer operation to detect a program loop is selected by the wdtm.wdtm4 bit to 1. the count clock (program loop detection time interv al) of the watchdog timer can be selected using the wdcs.wdcs0 to wdcs.wdcs2 bits. the count operation is started by setting the wdtm.run bit to 1. when, after the count operation is started, the run bit is again se t to 1 within the set program loop detection time interval, the watchdog timer is cleared and t he count operation starts again. if the program loop detection time is exceeded without the run bit being set to 1, a reset (wdtres) or a non- maskable interrupt request signal (intwdt) is generat ed, depending on the value of the wdtm.wdtm3 bit. the count operation of the watchdog ti mer stops in the software stop mode a nd idle mode. therefore, set the run bit to 1 before the software stop mode or idle mode is entered in order to clear the watchdog timer. table 13-2. program loop detection time of watchdog timer program loop detection time clock 80 mhz 60 mhz 2 14 /f xx 204.8 s 273.1 s 2 15 /f xx 409.6 s 546.1 s 2 16 /f xx 819.2 s 1.092 ms 2 17 /f xx 1.638 ms 2.185 ms 2 18 /f xx 3.277 ms 4.369 ms 2 19 /f xx 6.554 ms 8.738 ms 2 20 /f xx 13.11 ms 17.48 ms 2 22 /f xx 52.43 ms 69.91 ms remark f xw = f xx /2: watchdog timer clock frequency
chapter 13 watchdog timer functions user?s manual u16397ej3v0ud 614 13.4.2 operation as interval timer the watchdog timer can be made to operate as an interval timer that repeatedly generates interrupts using the count value set in advance as the interval, by setting the wdtm.wdtm4 bit to 0. when the watchdog timer operates as an interval timer, th e interrupt mask flag (wdtmk) and priority specification flags (wdtpr0 to wdtpr2) of the wdtic register are va lid and maskable interrupt request signals (intwdtm) can be generated. the default priority of the intwdtm signal is set to the highest level among the maskable interrupt request signals. the interval timer continues to operate in the halt m ode, but it stops operating in the software stop mode and the idle mode. caution once the wdtm4 bit is set to 1 (thereby selecting the watchdog timer mode) and the run bit is set (1), the interval timer mode is no t changed unless a reset is performed. table 13-3. interval time of interval timer interval time clock 80 mhz 60 mhz 2 14 /f xx 204.8 s 273.1 s 2 15 /f xx 409.6 s 546.1 s 2 16 /f xx 819.2 s 1.092 ms 2 17 /f xx 1.638 ms 2.185 ms 2 18 /f xx 3.277 ms 4.369 ms 2 19 /f xx 6.554 ms 8.738 ms 2 20 /f xx 13.11 ms 17.48 ms 2 22 /f xx 52.43 ms 69.91 ms remark f xw = f xx /2: watchdog timer clock frequency
user?s manual u16397ej3v0ud 615 chapter 14 a/d converter 14.1 features ? analog input: 8 channels ? 10-bit a/d converter ? on-chip a/d conversion result registers (adcr0 to adcr7) 10 bits 8 ? a/d conversion trigger mode software trigger mode timer trigger mode external trigger mode ? a/d conversion operation mode select mode scan mode ? buffer mode 1-buffer mode 4-buffer mode ? successive approximation method ? operable when the in ternal system clock (f xx ) is 10 mhz or higher
chapter 14 a/d converter user?s manual u16397ej3v0ud 616 14.2 configuration the block diagram is shown below. figure 14-1. block diag ram of a/d converter ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 intcmd0 intccq0 tqtadt intad adm0 (8) 8 voltage comparator sar (10) adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 10 10 10 90 internal bus av dd0 r/2 r r/2 series resistor string 70 av ss0 adm1 (8) 70 8 edge detection noise elimination adtrg sample & hold circuit f xx selector tap selector adm2 (8) 70 8 idle/software stop mode controller adts (8) 70 8 remark f xx : peripheral clock cautions 1. if there is noise at the analog input pins (ani0 to ani7) or at the a/d converter power supply voltage pin (av dd0 ), that noise may generate an illegal conversion result. software processing will be needed to avoid a negative effect on the system from this illegal conversion result. an example of this softwar e processing is shown below. ? take the average result of a number of a/d conversions and use that as the a/d conversion result. ? execute a number of a/d conversions con secutively and use tho se results, omitting any exceptional results that may have been obtained. ? if an a/d conversion result that is judge d to have generated a system malfunction is obtained, be sure to recheck the system malfunction before performing malfunction processing. 2. do not apply a voltage outside the av ss0 to av dd0 range to the pins that are used as a/d converter input pins. 3. the a/d converter is opera ble when the peripheral clock (f xx ) is 10 mhz or higher.
chapter 14 a/d converter user?s manual u16397ej3v0ud 617 the a/d converter consists of the following hardware. table 14-1. configuration of a/d converter item configuration analog input ani0 to ani7 (total of eight channels) registers successive appro ximation register (sar) a/d conversion result registers 0 to 7 (adcr0 to adcr7) a/d conversion result registers 0h to 7h (adcr0h to adcr7h) control registers a/d converter mode register 0 (adm0) a/d converter mode register 1 (adm1) a/d converter mode register 2 (adm2) a/d trigger select register (adts) (1) selector the input circuit selects the analog input pins (ani0 to ani7) accordi ng to the mode set by the adm0 and adm1 registers and sends the input to the sample & hold circuit. (2) sample & hold circuit the sample & hold circuit samples each of the analog in put voltages sequentially sent from the input circuit, and sends them to the voltage comparator. this circui t also holds the sampled analog input voltage during a/d conversion. (3) voltage comparator the voltage comparator compar es the analog input voltage with the output voltage of th e series resistor string voltage tap. (4) series resistor string the series resistor string is used to generate voltages to match the analog input voltage. the series resistor string is co nnected between the power supply volta ge pin for the a/d converter (av dd0 ) and the ground pin for the a/d converter (av ss0 ). to make 1,024 equivalent vo ltage steps between these 2 pins, it is configured from 1,023 equivalent resistors and 2 resistors with 1/2 of the resistance value. the voltage tap of the series resist or string is selected by a tap sele ctor controlled by the successive approximation register (sar). (5) successive approximation register (sar) the sar is a 10-bit register that sets series resistor string voltage tap data, w hose values match the voltage values of the analog input pins, 1 bit at a ti me starting from the most significant bit (msb). if data is set in the sar all the way to the least signifi cant bit (lsb) (a/d conversion completed), the contents of the sar (conversion results) are held in a/d conversi on result register n (adcrn) (n = 0 to 7). when all the specified a/d conversion oper ations have been completed, an a/d conversion end interrupt request signal (intad) is generated. (6) a/d conversion result register n (adcrn) the adcrn register is a 10-bit register that holds the a/d conversion results (n = 0 to 7). each time a/d conversion is completed, the conversion results are lo aded from the successive approximation register (sar) and stored in the lower 10 bits of the adcrn register. the higher 6 bits of this register is always 0.
chapter 14 a/d converter user?s manual u16397ej3v0ud 618 (7) a/d converter mode register 0 (adm0) this register is used to select the analog input pin, specify the operation mode, and control the conversion operation. (8) a/d converter mode register 1 (adm1) this register is used to set the c onversion operation time of the analog input to be a/d converted and specify the trigger mode. (9) a/d converter mode register 2 (adm2) this register is used to reset the a/d converter and control the clocks. (10) a/d trigger select register (adts) this register is used to specify the timer trigger input. (11) controller the controller selects the analog input pin, generates the sample & hold ci rcuit operation timing, and controls the conversion trigger according to the mode set by the adm0 to adm2 and adts registers. (12) ani0 to ani7 pins these are 8-channel analog input pins for the a/d conv erter. they input the analog signals to be a/d converted. caution make sure that the volt ages input to ani0 to ani7 do no t exceed the rated values. if a voltage higher than or equal to av dd0 or lower than or equal to av ss0 (even within the range of the absolute maximum ratings ) is input to a channel, the c onversion value of the channel is undefined, and the conversion values of th e other channels may also be affected. (13) av dd0 pin this alternates with the pin for inputting the positive powe r supply and reference voltage of the a/d converter. it converts signals input to the anin pin to digital signals based on the voltage applied between av dd0 and av ss0 . always make the potential at this pin the same as that at the ev dd pin even when the a/d converter is not used. do not stop supplying power to the av dd0 pin even in the standby status. (14) av ss0 pin this is the ground pin of the a/d conv erter. always make the potential at this pin the same as that at the ev ss pin.
chapter 14 a/d converter user?s manual u16397ej3v0ud 619 14.3 control registers the a/d converter is controlle d by the following registers. ? a/d converter mode registers 0 to 2 (adm0 to adm2) ? a/d trigger select register (adts) the following registers are also used. ? a/d conversion result registers 0 to 7 (adcr0 to adcr7) ? a/d conversion result registers 0h to 7h (adcr0h to adcr7h) (1) a/d converter mode register 0 (adm0) the adm0 register is an 8-bit regist er that selects the analog input pi n, specifies the operation mode, and executes conversion operations. this register can be read or written in 8-bit or 1-bit unit s. however, when data is written to the adm0 register during an a/d conversion operation, the conversion operation is initialized and conversion is executed from the beginning. bit 6 is read-only and writing executed is ignored. reset input clears this register to 00h. cautions 1. when the adce bit is 1 in the timer/external trigge r mode, the trigger signal standby state is set. to clear the adce bit, write 0, clear (0) the adm2.adcae bit, or reset the v850e/ma3. in the software trigger mode, the conversion tr igger is set by writing 1 to the adce bit. after the operation, when the mode is changed to the timer/external trigger mode without clearing the adce bit, the tri gger input standby state is set immediately after the register value is changed. 2. it takes 7 to 9 clocks until the adcs bit is set to 1 from when the adce bit was set to 1 in the software trigger mode.
chapter 14 a/d converter user?s manual u16397ej3v0ud 620 adce adm0 adcs 5 bs 4 ms 3 0 2 anis2 1 anis1 0 anis0 <6> <7> after reset: 00h r/w address: fffff200h adce a/d conversion control 0 conversion disabled 1 conversion enabled adcs a/d converter status 0 a/d conversion stopped 1 a/d conversion operating bs buffer mode specification 0 1-buffer mode 1 4-buffer mode ms operation mode specification 0 scan mode 1 select mode caution for anis2 to anis0 bits, see table 14-2 specification of analog input pin. table 14-2. specification of analog input pin select mode scan mode anis2 anis1 anis0 software trigger mode timer/external trigger mode note software trigger mode timer/external trigger mode 0 0 0 ani0 ani0 ani0 1 0 0 1 ani1 ani1 ani0, ani1 2 0 1 0 ani2 ani2 ani0 to ani2 3 0 1 1 ani3 ani3 ani0 to ani3 4 1 0 0 ani4 setting prohibited ani0 to ani4 4 + ani4 1 0 1 ani5 setting prohibited ani0 to ani5 4 + ani4, ani5 1 1 0 ani6 setting prohibited ani0 to ani6 4 + ani4 to ani6 1 1 1 ani7 setting prohibited ani0 to ani7 4 + ani4 to ani7 note the analog input pins that can be specified in th e timer/external trigger mode of the select mode are the ani0 to ani3 pins. if the anis2 bit is set to 1, therefore, the a/d conversion operation is not performed.
chapter 14 a/d converter user?s manual u16397ej3v0ud 621 (2) a/d converter mode register 1 (adm1) the adm1 register is an 8-bit register that spec ifies the conversion operation time and trigger mode. this register can be read or written in 8-bit units. however, when data is written to the adm1 register during an a/d conversion operation, the conv ersion operation is initialized a nd conversion is executed from the beginning. reset input sets this register to 07h. cautions 1. it takes the following number of clocks fr om trigger input to the start of a/d conversion. in software trigger mode: 9 to 11 clocks in timer/external trigger mode: 5 to 7 clocks 2. input the trigger at an inte rval longer than the minimum trigge r interval indicated in 14.8.5 a/d conversion time. 7 0 adm1 6 trg2 5 trg1 4 0 3 0 2 fr2 1 fr1 0 fr0 after reset: 07h r/w address: fffff201h trg2 trg1 trigger mode 0 0 software trigger mode 0 1 timer trigger mode note 1 1 0 setting prohibited 1 1 external trigger mode note 2 notes 1. the trigger is specified by the adts register in the timer trigger mode. 2. the valid edge of the trigger (adtrg pin) is specified by the intr3.intr37 and intf3.intf37 bits in the external trigger mode (see 20.4.2 (5) external interr upt rising edge specification register 3 (intr3), external interrupt fa lling edge specification register 3 (intf3) ). do not set the intr37 and intf37 bits to detect a level (low level detection). cautions 1. for fr2 to fr0 bits, see table 14-3 conversion operation time. 2. be sure to set bits 3, 4, and 7 to ?0?.
chapter 14 a/d converter user?s manual u16397ej3v0ud 622 table 14-3. conversion operation time conversion operation time note fr2 fr1 fr0 number of conversion clocks f xx = 80 mhz f xx = 66.7 mhz f xx = 50 mhz f xx = 10 mhz 0 0 0 52 setting prohibited setting prohibited setting prohibited 5.20 s 0 0 1 104 setting prohibited setting prohibi ted setting prohibited setting prohibited 0 1 0 156 setting prohibited 2.34 s 3.12 s setting prohibited 0 1 1 208 2.60 s 3.12 s 4.16 s setting prohibited 1 0 0 260 3.25 s 3.90 s 5.20 s setting prohibited 1 0 1 312 3.90 s 4.68 s setting prohibited setting prohibited 1 1 0 364 4.55 s setting prohibited setting pr ohibited setting prohibited 1 1 1 416 5.20 s setting prohibited setting pr ohibited setting prohibited note figures under the conversion operation time parameter are target values. set the conversion operation time in the range of 2.34 to 5.20 s. the a/d converter cannot be used if f xx < 10 mhz. remark f xx : internal system clock
chapter 14 a/d converter user?s manual u16397ej3v0ud 623 (3) a/d converter mode register 2 (adm2) the adm2 register is an 8-bit register that cont rols the reset and clock of the a/d converter. this register can be read or written in 8-bit or 1-bit units. however, bit 1 is read-only. reset input sets this register to 02h. cautions 1. when the adcae bit is cleared to 0, the adm0.adce and adm0.adcs bits are automatically cleared to 0 (the adce bi t cannot be set if the adcae bit is 0). the other registers are not initialized. 2. the a/d converter enters the reset state after reset release. when operating the a/d converter, be sure to set the adcae bit to 1 after setting the adm0 and adm1 registers. 7 0 adm2 6 0 5 0 4 0 3 0 2 0 <1> adncs adcae <0> after reset: 02h r/w address: fffff202h adncs a/d conversion invalid status 0 a/d conversion enabled 1 a/d conversion disabled ? this bit is set when the a/d converter is not used, in the idle/software stop mode, after the idle/software stop mode has been released, and within the oscillation stabilization time note after the adcae bit has been set to 1. ? in the software trigger mode, starting the conversion is postponed even if the adm0.adce bit is set to 1. ? in the timer/external trigger mode, the tri gger is ignored even if it is input within the stabilization time. adcae a/d converter operation control 0 clock supply to the a/d converter is stopped; the a/d converter is in the reset state 1 the clock is supplied to the a/d conv erter; a/d converter operation is enabled note time is required to stabilize the analog circuit after supplying the clock to the a/d converter is started. the v850e/ma3 uses hardware to ensur e the lapse of the stabilization time. for the stabilization time, see 14.8.6 stabilization time .
chapter 14 a/d converter user?s manual u16397ej3v0ud 624 (4) a/d conversion result registers 0 to 7, 0h to 7h (adcr0 to adcr7, adcr0h to adcr7h) the adcrn register is a 10-bit regist er holding the a/d conversion results. there are eight 10-bit registers. these registers are read-only, in 16-bit or 8-bit units. to read the a/d conversion result in 16-bit units, specify the adcrn register, and to read the higher 8 bits of t he result, specify the adcrnh register (n = 0 to 7). when reading the 10-bit data of the a/d conversion result s from the adcrn register during 16-bit access, only the lower 10 bits are valid and the higher 6 bits are always 0. reset input clears the adcrn register to 0000h, and the adcrnh register to 00h. address: adcr0 fffff210h, adcr1 fffff212h, after reset: 0000h r after reset: 00h r adcrn ad n9 ad n8 ad n7 ad n6 ad n5 ad n4 ad n3 ad n2 ad n1 ad n0 0 0 0 0 0 0 adn9 adcrnh adn8 adn7 adn6 adn5 adn4 adn3 adn2 76 54 32 1 0 adcr2 fffff214h, adcr3 fffff216h, adcr4 fffff218h, adcr5 fffff21ah, adcr6 fffff21ch, adcr7 fffff21eh address: adcr0h fffff220h, adcr1h fffff221h, adcr2h fffff222h, adcr3h fffff223h, adcr4h fffff224h, adcr5h fffff225h, adcr6h fffff226h, adcr7h fffff227h (n = 0 to 7) (n = 0 to 7) the correspondence between each analog input pin and t he adcrn register (except in the 4-buffer mode) is shown below. analog input pin adcrn register ani0 adcr0, adcr0h ani1 adcr1, adcr1h ani2 adcr2, adcr2h ani3 adcr3, adcr3h ani4 adcr4, adcr4h ani5 adcr5, adcr5h ani6 adcr6, adcr6h ani7 adcr7, adcr7h
chapter 14 a/d converter user?s manual u16397ej3v0ud 625 the relationship between the analog voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (of a/d conversion result register n (adcrn)) is as follows: 0.5) 1,024 av v ( int adcr dd0 in + = or, 1,024 av 0.5) (adcr v 1,024 av 0.5) (adcr dd0 in dd0 + < ? int( ): function that returns the integer of the value in ( ) v in : analog input voltage av dd0 : av dd0 pin voltage adcr: value of a/d conversion result register n (adcrn) the relationship between the analog input voltage a nd the a/d conversion results is shown below. figure 14-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av dd0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results (adcrn) remark n = 0 to 7
chapter 14 a/d converter user?s manual u16397ej3v0ud 626 (5) a/d trigger select register (adts) the adts register selects the timer trigger input. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. 7 0 adts 6 0 5 0 4 0 3 0 <2> tms2 <1> tms1 tms0 <0> after reset: 01h r/w address: fffff288h tms2 timer trigger si gnal (intcmd0) enable 0 do not select intcmd0 signal as timer trigger input. 1 select intcmd0 signal as timer trigger input. tms1 timer trigger si gnal (intccq0) enable 0 do not select intccq0 signal as timer trigger input. 1 select intccq0 signal as timer trigger input. tms0 timer trigger signal (tqtadt note ) enable 0 do not select tqtadt signal note as timer trigger input. 1 select tqtadt signal note as timer trigger input. note the tqtadt signal is set by the tq0opt 2.tq0at0 to tq0opt2.tq0at3 bits. cautions 1. do not write to the adts regi ster during an a/d c onversion operation. 2. set the tms0 bit to 1 wh en selecting the interrupt request signal (tqtadt) of the motor control function as the timer trigger input. the following interrupt request signals of the motor control function can be selected as the ti mer trigger input (two or more interrupt signals can be selected). ? timer q0 (in 6-phase pwm output mode (inclu ding when the tuning operation with timer p2 is not performed)) tq0at0 bit = 1: intovq signal (match in terrupt of the 16-bit counter value and 0001h during down-counting) tq0at1 bit = 1: intccq0 signal (match interrupt of the 16-bit counter value and the tq0ccr0 register value during up-counting) ? timer p2 (only when the tuning operation with timer q0 is performed in the 6-phase pwm output mode) tq0at2 bit = 1: intccp20 signal (when th e value of timer p2 during the tuning operation matches the set value of tp2ccr0 register value) tq0at3 bit = 1: intccp21 signal (when th e value of timer p2 during the tuning operation matches the set value of tp2ccr1 register value)
chapter 14 a/d converter user?s manual u16397ej3v0ud 627 14.4 operation 14.4.1 basic operation a/d conversion is executed by the following procedure. (1) select an analog input pin, operation mode, and tr igger mode, by using the adm0 and adm1 registers note 1 . the setting of the stabilization time is determined by the specification of the adm1.fr0 to adm1.fr2 bits. (2) set the adm2.adcae bit to 1 note 2 . when the adcae bit is set from 0 to 1, c ounting the stabilization time is started. (3) in the software trigger mode, setting the adm0.adce bi t to 1 starts a/d conversion after the lapse of the stabilization wait time. if the adce bit is set to 1 in the timer/external trigger mode, the a/d converter ignores the trigger during the stabilization wait time and waits for the trigger after the lapse of the stabilization wait time note 3 . (4) the voltage generated from the voltag e tap of the series resistor string is compared with the analog input voltage by the comparator. (5) when comparison of 10 bits has been completed, the va lid digital value result remains in the successive approximation register (sar). this value is transferr ed to the adcrn register and the conversion result is stored in this register. when a/d conversion has been completed the specified number of times, an a/d conversion end interrupt request signal (intad) is generated (n = 0 to 7). notes 1. if the adm0 to adm2 registers are written durin g a/d conversion, the conversion result is not stored in the adcrn register and the conversion operation is performed from the beginning again. if the adcae bit is cleared to 0, clock supply to the a/d converter is stopped, the current a/d conversion operation is initializ ed, and the adce bit is cleared to 0. the adm0.adcs bit register is 0 when it is read. 2. if the adm1 register is set during the stabilization wait time after the adcae bit has been set to 1, the stabilization wait time is re set, and stabilization wait time is generated according to the values of the fr0 to fr2 bits. 3. in the timer/external trigger mode, if the adce bit is set to 1, the mode changes to the trigger standby state. the a/d conversion operation is started by the trigger signal, and the trigger standby state is returned to when t he a/d conversion operation ends.
chapter 14 a/d converter user?s manual u16397ej3v0ud 628 14.4.2 operation mode and trigger mode various conversion operations can be specified for the a/ d converter by specifying the operation mode and trigger mode. the operation mode and trigger mode are set by adm0 and adm1 registers. the following shows the relationship betwe en the operation mode and trigger mode. setting value trigger mode operation mode adm0 adm1 analog input pin 1 buffer xx010xxxb 000x0xxxb select 4 buffers xx110xxxb 000x0xxxb software trigger scan xxx00xxxb 000x0xxxb ani0 to ani7 1 buffer xx010xxxb 00100xxxb select 4 buffers xx110xxxb 00100xxxb ani0 to ani3 timer trigger scan xxx00xxxb 00100xxxb ani0 to ani7 1 buffer xx010xxxb 01100xxxb select 4 buffers xx110xxxb 01100xxxb ani0 to ani3 external trigger scan xxx00xxxb 01100xxxb ani0 to ani7 (1) trigger mode there are three types of trigger modes that serve as the start timing of a/d conv ersion operation: software trigger mode, timer trigger mode, and external trigger mode. (a) software trigger mode in this mode, the analog input pin selected by the adm0.anis0 to adm0.anis2 bits from the ani0 to ani7 pins is used for a/d conversion. the conversi on is started when the adm0.adce bit is set to 1. (b) timer trigger mode in this mode, the analog input pin selected by the anis0 to anis2 bits from the ani0 to ani7 pins is used for a/d conversion. the conversion is started by one of the timers (timer q0, timer d0, or the motor control function). the timer interrupt request signa l selected by the adts register can be selected as a trigger of the a/d conversion operation. the ani0 to ani3 pins can be specified in the sele ct mode and scan mode, but the ani4 to ani7 pins cannot be specified in the select mode. in the scan mode, input from the ani3 pin is converted and conversion of the ani4 to ani7 pins is immediat ely started when the fourth trigger is generated. when a timer trigger is generated, the analog input conversion timing is generated. (c) external trigger mode in this mode, the analog input pin selected by the anis0 to anis2 bits from the ani0 to ani7 pins is used for a/d conversion. the adtrg pin is used to start the a/d conversion. the ani0 to ani3 pins can be specified in the sele ct mode and scan mode, but the ani4 to ani7 pins cannot be specified in the select mode. in the scan mode, input from the ani3 pin is converted and conversion of the ani4 to ani7 pins is immediat ely started when the fourth trigger is generated. (2) operation mode there are two operation modes that set the ani0 to ani7 pins: select mode and scan mode. the select mode has sub-modes that consist of 1-buffer mode and 4-buffe r mode. these modes are set by the adm0 register.
chapter 14 a/d converter user?s manual u16397ej3v0ud 629 (a) select mode in this mode, one analog input pin voltage specified by the adm0 register is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input pin (anin). for this mode, the 1-buffer mode and 4-buffer mode are provid ed for storing the a/d conversion results (software trigger mode: n = 0 to 7, timer/external trigger mode: n = 0 to 3). ? 1-buffer mode in this mode, one analog input pin voltage specified by the adm0 re gister is a/d converted. the conversion results are stored in the adcrn register corresponding to the analog input pin (anin). the anin pin and adcrn register correspond one to one, and an a/d conversion end interrupt request signal (intad) is generated each time one a/d conversion ends. figure 14-3. select mode operat ion timing: 1-buffer mode (ani1) data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 (ani1) data 6 (ani1) conversion start adce bit set conversion start adce bit set conversion start adce bit set conversion start adce bit set conversion start adce bit set conversion start adce bit set intad interrupt adcr1 register a/d conversion ani1 (input) data 1 data 2 data 3 data 4 data 5 data 6 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input pin
chapter 14 a/d converter user?s manual u16397ej3v0ud 630 ? 4-buffer mode in this mode, one analog input pin voltage is a/d c onverted four times and the results are stored in the adcr0 to adcr3 registers. the a/d conversion end interrupt request signal (intad) is generated when the four a/d conversions end. figure 14-4. select mode operat ion timing: 4-buffer mode (ani6) data 1 (ani6) data 2 (ani6) data 3 (ani6) data 4 (ani6) data 5 (ani6) data 1 (ani6) data 5 (ani6) data 6 (ani6) conversion start adce bit set conversion start adce bit set intad interrupt adcr0 register a/d conversion ani6 (input) data 2 (ani6) adcr1 register data 3 (ani6) adcr2 register data 4 (ani6) adcr3 register data 1 data 2 data 3 data 4 data 5 data 6 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input pin
chapter 14 a/d converter user?s manual u16397ej3v0ud 631 (b) scan mode in this mode, the analog input pins (anin) specified by the adm0 regi ster are selected sequentially from the ani0 pin, and a/d conversion is executed. th e a/d conversion results are stored in the adcrn register corresponding to the analog input pin (anin) (n = 0 to 7). when the c onversion of the specified analog input pin ends, the a/d conversion end inte rrupt request signal (intad) is generated. figure 14-5. scan mode operation ti ming: 4-channel scan (ani0 to ani3) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 1 (ani0) data 5 (ani0) data 6 (ani1) conversion start adce bit set conversion start adce bit set intad interrupt adcr0 register a/d conversion ani0 (input) ani1 (input) ani2 (input) ani3 (input) data 2 (ani1) adcr1 register data 3 (ani2) adcr2 register data 4 (ani3) adcr3 register data 1 data 2 data 3 data 4 data 5 data 6 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adcrn register analog input pin
chapter 14 a/d converter user?s manual u16397ej3v0ud 632 14.5 operation in software trigger mode when the adm0.adce bit is set (1), a/d conversion is started. 14.5.1 select mode operation in this mode, the analog input pin voltage specified by the adm0 register is a/d conver ted. the conversion results are stored in a/d conversion result register n (adcrn) co rresponding to the analog input. in the select mode, the 1- buffer mode and 4-buffer mode are supported according to t he method of storing the a/d conversion results (n = 0 to 7). (1) 1-buffer mode (software trigger select: 1 buffer) in this mode, one analog input pin voltage is a/d conver ted once. the conversion results are stored in one adcrn register. the analog input pin (anin) and adcrn register correspond one to one. each time an a/d conversion is executed, an a/d co nversion end interrupt request signal (intad) is generated and a/d conversion ends. analog input pin a/d conversion result register anin adcrn if the adm0.adce bit is set (1), a/d conversion can be restarted. this mode is most appropriate for applications in which the results of each first-time a/d conversion are read. figure 14-6. example of 1-buffer mode oper ation (software trigger select: 1 buffer) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm0 (1) the adm0.adce bit is set to 1 (enable) (2) the ani2 pin is a/d converted (3) the conversion result is stored in the adcr2 register (4) the intad interrupt request signal is generated
chapter 14 a/d converter user?s manual u16397ej3v0ud 633 (2) 4-buffer mode (softwar e trigger select: 4 buffers) in this mode, one analog input pin voltage is a/d conver ted four times and the results are stored in the adcr0 to adcr3 registers. when the 4t h a/d conversion ends, an a/d conv ersion end interrupt request signal (intad) is generated and the a/d conversion is stopped. analog input pin a/d conversion result register anin adcr0 anin adcr1 anin adcr2 anin adcr3 if the adm0.adce bit is set (1), a/d conversion can be restarted. this mode is suitable for applications in which the av erage of the a/d conversi on results is calculated. figure 14-7. example of 4-buffer mode oper ation (software trigger select: 4 buffers) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm0 ( 4) ( 4) (1) the adm0.adce bit is set to 1 (enable) (6) the ani4 pin is a/d converted (2) the ani4 pin is a/d converted (7) the conv ersion result is stored in the adcr2 register (3) the conversion result is stored in the a dcr0 register (8) the ani4 pin is a/d converted (4) the ani4 pin is a/d converted (9) the conv ersion result is stored in the adcr3 register (5) the conversion result is stored in the adcr1 register (10) the intad signal is generated
chapter 14 a/d converter user?s manual u16397ej3v0ud 634 14.5.2 scan mode operations in this mode, the analog input pins (anin) specified by the adm0 register are selected sequentially from the ani0 pin, and a/d conversion is ex ecuted. the a/d conversion results are stored in the adcr n register corresponding to the analog input pin (n = 0 to 7). when conversion of all the specified analog input pin ends, the a/d conver sion end interrupt request signal (intad) is generated, and a/d conversion is stopped. analog input pin a/d conversion result register ani0 adcr0 anin note adcrn note set by the adm0.ani s0 to adm0.anis2 bits. if the adm0.adce bit is set (1), a/d conversion can be restarted. this mode is most appropriate for applications in whic h multiple analog inputs are constantly monitored. figure 14-8. example of scan mode operation (software trigger scan) ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adm0 (1) the adm0.adce bit is set to 1 (enable) (8) the ani3 pin is a/d converted (2) the ani0 pin is a/d converted (9) the conv ersion result is stored in the adcr3 register (3) the conversion result is stored in the a dcr0 register (10) the ani4 pin is a/d converted (4) the ani1 pin is a/d converted (11) the conv ersion result is stored in the adcr4 register (5) the conversion result is stored in the a dcr1 register (12) the ani5 pin is a/d converted (6) the ani2 pin is a/d converted (13) the conv ersion result is stored in the adcr5 register (7) the conversion result is stored in the adcr2 register (14) the intad signal is generated . . . . . .
chapter 14 a/d converter user?s manual u16397ej3v0ud 635 14.6 operation in timer trigger mode conversion timing for up to four-channel analog inputs (a ni0 to ani3) can be set for the a/d converter using the interrupt request signal of the time r selected by the adts register. timer q0, timer d0, or the motor control function can be used for the timer to specify the a/d conversion trigger. the following two modes are provided according to the value set in the timer. (1) one-shot mode to use the one-shot mode, set the adts.tms1 bit to 1, and set timer q0 in the one-shot pulse mode. when the 16-bit counter value matches the set value of the tq0ccr0 register, an interrupt request signal (intccq0) is generated and the 16-bit counter is cleared to 0000h and stopped. after that, because timer q0 does not generate the intccq0 signal, the a/d trigger signal is not ge nerated and the a/d converter enters the conversion standby status. when timer q0 is restarted, the a/d trigger signal is generated. the one-shot mode is used if t he a/d conversion cycle is longer than the timer q0 cycle. (2) loop mode the loop mode is used as follows. ? when timer q0 is used in the interval timer mode (when the adts.tms1 bit is set to 1) ? crest interrupt/valley interrupt of motor control function ? when timer p2 that operates in tune with the motor control function is used in the free-running mode ? timer d0 in this mode, the timer repeatedly outputs an interrupt request signal and a/d conversion is also performed repeatedly. depending on the setting of the tq 0opt2.tq0at0 to tq0opt 2.tq0at3 bits of the motor control function, two or more timer interrupt request signals can be used as a trigger of a/d conversion. at this time, the generation interval of the timer interrupt request signal must not be shorter than the minimum trigger interval shown in table 14-5 conversion time in timer tr igger mode and external trigger mode . the interrupt request signal is ignored even if it is generated at interval shorter than the minimum trigger interval.
chapter 14 a/d converter user?s manual u16397ej3v0ud 636 14.6.1 select mode operation in this mode, the analog input pin voltage specified by the adm0 register is a/d conver ted. the conversion results are stored in adcrn register. in the select mode, the 1-buffer mode and 4-buffer mode are provided according to the method of storing the a/d conv ersion results (n = 0 to 3). (1) 1-buffer mode operation (tim er trigger select: 1 buffer) in this mode, one analog input pin voltage is a/d conver ted once using the signal from the timer as a trigger, and the results are stored in one adcrn register. an a/ d conversion end interrupt request signal (intad) is generated for each a/d conversion and a/ d conversion is stopped (n = 0 to 3). trigger analog input pin a/d conversion result register timer trigger signal anin adcrn in one-shot mode, a/d conversion stops after one conv ersion. to restart a/d conversion, set (1) the tq0ctl0.tq0ce bit to restart timer q0. when set to the loop mode, unless the adm0.adce bit is cleared (0) or the adm2.adcae bit is cleared (0), a/d conversion is repeated each time a timer interrupt request signal is generated. figure 14-9. example of 1-trigger mode op eration (timer trigger select: 1 buffer) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter timer interrupt request signal (1) the adm0.adce bit is set to 1 (enable) (2) the timer interrupt request signal is generated (3) the ani1 pin is a/d converted (4) the conversion result is stored in the adcr1 register (5) the intad signal is generated
chapter 14 a/d converter user?s manual u16397ej3v0ud 637 (2) 4-buffer mode operation (tim er trigger select: 4 buffers) in this mode, one analog input pin voltage is a/d conv erted four times using the timer interrupt request signal as a trigger, and the results are stored in the adcr0 to adcr3 registers. the a/d conversion end interrupt request signal (intad) is generated when the four a/d conversions end and a/d conversion is stopped. this mode is suitable for applications in which the av erage of the a/d conversi on results is calculated. trigger analog input pin a/d conversion result register timer interrupt request signal anin adcr0 timer interrupt request signal anin adcr1 timer interrupt request signal anin adcr2 timer interrupt request signal anin adcr3 if the one-shot mode is set and the timer interrupt requ est signal (intccq0) is generat ed less than four times, the intad signal is not generat ed and the standby state is set. figure 14-10. example of 1-trigger mode op eration (timer trigger select: 4 buffers) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 ( 4) ( 4) (1) the adm0.adce bit is set to 1 (enable) (8 ) the timer interrupt request signal is generated (2) the timer interrupt request signal is generated (9) the ani2 pin is a/d converted (3) the ani2 pin is a/d converted (10) the conv ersion result is stored in the adcr2 register (4) the conversion result is stored in the adcr0 r egister (11) the timer interrupt request signal is generated (5) the timer interrupt request signal is generated (12) the ani2 pin is a/d converted (6) the ani2 pin is a/d converted (13) the conv ersion result is stored in the adcr3 register (7) the conversion result is stored in the adcr1 register (14) the intad signal is generated
chapter 14 a/d converter user?s manual u16397ej3v0ud 638 14.6.2 scan mode operation in this mode, the analog input pins (anin) specified by the adm0 register are selected sequentially from the ani0 pin using the timer interrupt request signal as a trigger an d a/d conversion is performed. the a/d conversion results are stored in the adcrn register corresponding to the analog input pin (n = 0 to 7). in the conversion operation, first t he lower 4 analog input pin channels (ani0 to ani3) are a/d converted the specified number of times. if the lower 4 analog input pin channels (ani0 to ani3) are set by the adm0 register so that they are scanned, and when the se t number of a/d conversions ends, the a/d conversion end interrupt request signal (intad) is generated and a/d conversion is stopped. when the higher 4 channels (ani4 to ani7) of the analog input pins are set by the adm0 register so that they are scanned, after the conversion of the lower 4 channels has ended, the mode is shifted to the software trigger mode, and the remaining a/d conversions are executed. the conversion results are stored in the adcrn re gister corresponding to the analog input pin. when conversion of all the specified analog input pins has ended, the intad signal is generated and a/d conversion is stopped (n = 0 to 7). trigger analog input pin a/d conversion result register timer interrupt request signal ani0 adcr0 timer interrupt request signal ani1 adcr1 timer interrupt request signal ani2 adcr2 timer interrupt request signal ani3 adcr3 ani4 adcr4 ani5 adcr5 ani6 adcr6 (software trigger mode) ani7 adcr7 when the timer interrupt request signal is generated while the adm0.adce bit is 1, a/d conversion is restarted. in one-shot mode, and when less than the specified number of timer interrupt request signals are generated, if the adce bit is set to 1, the intad signal is not generated and the standby state is set. the timer interrupt request signal is ig nored even if it is generated when t he software trigger mode is set. this mode is suitable for applications in which two or mo re analog input pins are constantly monitored.
chapter 14 a/d converter user?s manual u16397ej3v0ud 639 figure 14-11. example of timer trigger scan operation (a) setting when scanning ani0 to ani3 pins ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 (1) the adm0.adce bit is set to 1 (enable) (8 ) the timer interrupt request signal is generated (2) the timer interrupt request signal is generated (9) the ani2 pin is a/d converted (3) the ani0 pin is a/d converted (10) the conv ersion result is stored in the adcr2 register (4) the conversion result is stored in the adcr0 r egister (11) the timer interrupt request signal is generated (5) the timer interrupt request signal is generated (12) the ani3 pin is a/d converted (6) the ani1 pin is a/d converted (13) the conv ersion result is stored in the adcr3 register (7) the conversion result is stored in the adcr1 register (14) the intad signal is generated caution the timer interrupt request signal cannot be used as a trigger for the analog input pins enclosed in the broken lines. when a setting is made to scan the ani0 to ani7 pins, the ani4 to ani7 pins are converted in softw are trigger mode (see (b) below). (b) setting when scanning ani0 to ani7 pins ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter intm000 (1) to (13) same as (a) (18) the ani6 pin is a/d converted (14) the ani4 pin is a/d converted (19) the conv ersion result is stored in the adcr6 register (15) the conversion result is stored in the a dcr4 register (20) the ani7 pin is a/d converted (16) the ani5 pin is a/d converted (21) the conv ersion result is stored in the adcr7 register (17) the conversion result is stored in t he adcr5 register (22) the intad signal is generated
chapter 14 a/d converter user?s manual u16397ej3v0ud 640 figure 14-12. timer trigger scan operati on timing: 8-channel scan (ani0 to ani7) data 1 (ani0) data 9 (ani0) intad interrupt adcr0 register ani0 (input) ani1 (input) ani2 (input) ani3 (input) ani4 (input) ani5 (input) ani6 (input) ani7 (input) data 2 (ani1) adcr1 register adcr2 register adcr3 register a/d conversion timer interrupt request signal data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani4) data 6 (ani5) data 7 (ani6) data 8 (ani7) data 9 (ani0) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 8 data 9 data 5 (ani4) adcr4 register data 6 (ani5) data 7 (ani6) data 8 (ani7) adcr5 register adcr6 register adcr7 register data 3 (ani2) data 4 (ani3) conversion start adce bit set conversion start adce bit set
chapter 14 a/d converter user?s manual u16397ej3v0ud 641 14.7 operation in external trigger mode in the external trigger mode, the analog input pins (a ni0 to ani7) are a/d converted at the adtrg pin input timing. the adtrg pin has an alternate function as the p37/intp 137 pin. to set the external trigger mode, set the pmc3.pmc37 bit to 1 and the adm1.trg2 and adm1.trg1 bits of to 11. for the valid edge of the external input signal in the ex ternal trigger mode, the rising edge, falling edge, or both rising and falling edges can be specified using the intr3.intr37 bit and intf3.intf37 bit (see 20.4.2 (5) external interrupt rising edge specification re gister 3 (intr3), external interrupt falling edge specification register 3 (intf3) ). do not specify level detection when using the adtrg pin. 14.7.1 select mode operations in this mode, one analog input pin (ani0 to ani3) voltage specified by the adm0 regist er is a/d converted. the conversion results are stored in the adcr n register corresponding to the analog input. there are two select modes: 1-buffer mode and 4-buffer mode, according to the method of storing the a/d conversion results (n = 0 to 3). (1) 1-buffer mode (externa l trigger select: 1-buffer) in this mode, one analog input pin vo ltage is a/d converted using the adtrg signal as a trigger. the conversion results are stored in one adcrn register. the analog input pin (anin) and the adcrn register correspond one to one. the a/d conversion end interr upt request signal (intad) is generated for each a/d conversion, and a/d c onversion is stopped. trigger analog input pin a/d conversion result register adtrg signal anin adcrn while the adm0.adce bit is 1, a/d conversion is repeat ed every time a trigger is input from the adtrg pin. this mode is most appropriate for applications in wh ich the results are read after each a/d conversion. figure 14-13. example of 1-buffer mode oper ation (external trigger select: 1 buffer) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adtrg (1) the adm0.adce bit is set to 1 (enable) (2) the external trigger si gnal (adtrg) is generated (3) the ani2 pin is a/d converted (4) the conversion result is stored in the adcr2 register (5) the intad signal is generated
chapter 14 a/d converter user?s manual u16397ej3v0ud 642 (2) 4-buffer mode (externa l trigger select: 4 buffers) in this mode, one analog in put pin voltage is a/d conv erted four times using the adtrg signal as a trigger and the results are stored in the adcr0 to adcr3 register s. the a/d conversion end interrupt request signal (intad) is generated and a/d conversion is stopped after the 4th a/d conversion. trigger analog input pin a/d conversion result register adtrg signal anin adcr0 adtrg signal anin adcr1 adtrg signal anin adcr2 adtrg signal anin adcr3 while the adm0.adce bit is 1, a/d conversion is repeat ed every time a trigger is input from the adtrg pin. this mode is suitable for applications in which the av erage of the a/d conversi on results is calculated. figure 14-14. example of 4-buffer mode oper ation (external trigger select: 4 buffers) ani0 ani1 ani2 ani3 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter ( 4) ( 4) adtrg (1) the adm0.adce bit is set to 1 ( enable) (8) the adtrg signal is generated (2) the external trigger signal (adtrg) is generated (9) the ani2 pin is a/d converted (3) the ani2 pin is a/d converted (10) the conv ersion result is stored in the adcr2 register (4) the conversion result is stored in the adcr0 register (11) the adtrg signal is generated (5) the adtrg signal is generated (12) the ani2 pin is a/d converted (6) the ani2 pin is a/d converted (13) the conv ersion result is stored in the adcr3 register (7) the conversion result is stored in the adcr1 register (14) the intad signal is generated
chapter 14 a/d converter user?s manual u16397ej3v0ud 643 14.7.2 scan mode operation in this mode, the analog input pins specified by a/d co nverter mode register 0 (adm 0) are selected sequentially from the ani0 pin using the adtrg signal as a trigger, and a/d converted. the a/d conv ersion results are stored in a/d conversion result register n (adcrn) corres ponding to the analog input pin (n = 0 to 7). when the lower 4 analog input pin channels (ani0 to ani3) are set by the adm0 register so that they are scanned, the a/d conversion end interrupt request signal (intad) is generated when the specifi ed number of a/d conversions have ended, and a/d conversion is stopped. when the higher 4 analog input pin channels (ani4 to ani7 ) are set by the adm0 register so that they are scanned, after the conver sion of the lower 4 channels is ended, the mode is shifted to the software tr igger mode, and the remaining a/d conversions are exec uted. the conversion results are stor ed in the adcrn register corresponding to the analog input pin (n = 0 to 7). trigger analog input pin a/d conversion result register adtrg signal ani0 adcr0 adtrg signal ani1 adcr1 adtrg signal ani2 adcr2 adtrg signal ani3 adcr3 ani4 adcr4 ani5 adcr5 ani6 adcr6 (software trigger mode) ani7 adcr7 when conversion of all the specified analog input pins has ended, the intad signal is generated and a/d conversion is stopped. when a trigger is input to the adtrg pin while the ad m0.adce bit is 1, a/d conversion is started again. the next trigger is ignored even if it is input when the software trigger mode is set. this is most suitable for applications in which multiple analog inputs are constantly monitored.
chapter 14 a/d converter user?s manual u16397ej3v0ud 644 figure 14-15. example of scan mode operation (external trigger scan) (a) setting when scanning ani0 to ani3 pins ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adtrg (1) the adm0.adce bit is set to 1 ( enable) (8) the adtrg signal is generated (2) the external trigger signal (adtrg) is generated (9) the ani2 pin is a/d converted (3) the ani0 pin is a/d converted (10) the conv ersion result is stored in the adcr2 register (4) the conversion result is stored in the adcr0 register (11) the adtrg signal is generated (5) the adtrg signal is generated (12) the ani3 pin is a/d converted (6) the ani1 pin is a/d converted (13) the conv ersion result is stored in the adcr3 register (7) the conversion result is stored in the adcr1 register (14) the intad signal is generated caution the adtrg pin cannot be used as a trigger fo r the analog input pins enclosed in the broken lines. when a setting is made to scan the ani0 to ani7 pins, the ani4 to ani7 pins are converted in software tri gger mode (see (b) below). (b) setting when scanning ani0 to ani7 pins ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d converter adtrg (1) to (13) same as (a) (18) the ani6 pin is a/d converted (14) the ani4 pin is a/d converted (19) the conv ersion result is stored in the adcr6 register (15) the conversion result is stored in the a dcr4 register (20) the ani7 pin is a/d converted (16) the ani5 pin is a/d converted (21) the conv ersion result is stored in the adcr7 register (17) the conversion result is stored in t he adcr5 register (22) the intad signal is generated
chapter 14 a/d converter user?s manual u16397ej3v0ud 645 14.8 notes on operation 14.8.1 stopping conversion operation when the adm0.adce bit is set to 0 during a conver sion operation, the conver sion operation stops and the conversion results are not stored in the adcrn register (n = 0 to 7). 14.8.2 timer/external trigger interval for the interval (input time interval) of the tr igger in the timer/external trigger mode, see table 14-5 conversion time in timer trigger mode and external trigger mode . (1) when interval = 0 when several triggers are input simultaneously, the analo g input pin with the smaller anin pin number (n) is converted. the other trigger signals input simultaneous ly are ignored, and the number of trigger inputs is not counted. note, therefore, that the generation of an inte rrupt request signal (intad) and saving of the result to the adcrn register are abnormalities (n = 0 to 7). (2) when 0 < interval < a/ d conversion operation time when the timer/external trigger is input during a conver sion operation, the conversi on operation is aborted and the conversion starts according to t he last timer/external trigger input. when conversion operations are abort ed, the conversion results are not stored in the adcrn register, and the number of trigger inputs is not counted. note, therefore, that the generation of the intad signal and saving of the result to the adcrn register are abnormalities (n = 0 to 7). (3) when interval a/d conversion operation time the number of trigger inputs is count ed, the intad signal is generated, and the value at the end of conversion is correctly saved in the adcrn register. design so that the interval is equal or greater than the a/d conversion operation time. 14.8.3 operation in standby mode (1) halt mode in this mode, a/d conversion continues. (2) idle mode, software stop mode as clock supply to the a/d converter is stop ped, no conversion operations are performed. when these modes are released by nmi input or t he maskable interrupt request signal input pin note , the adm0 to adm2 and adcrn registers hold the value. however, when the idle or software stop mode is set during a conversion operation, the conversi on operation is suspended. at this time, if the mode released by nmi input or the maskable interrupt request signal input pin note , the conversion operation resumes. at this time, the interrupt request signal (intad) may be generated, but th e conversion result written to the adcrn register will become undefined (x = 0 to 3, n = 0 to 7). note intp000, intp001, intp004, intp005, intp010 to intp013, intp021, intp022, intp050, intp051, intp106, intp107, intp114, intp115, intp124 to intp126, intp130 to intp134, intp137 pins
chapter 14 a/d converter user?s manual u16397ej3v0ud 646 14.8.4 timer interrupt request si gnal in timer trigger mode the timer interrupt request signal becomes an a/d conversion start trigger and starts the conversion operation. when this happens, the timer interrupt request signal also func tions as an interrupt for the cpu. in order to prevent match interrupts for the cpu, disable interrupts usi ng the mask bits of the in terrupt control register. 14.8.5 a/d conversion time (1) conversion time in software trigger mode the table below shows the conversion time in the software trigger mode. table 14-4. conversion time in software trigger mode fr2 fr1 fr0 number of conversion clocks number of initialization clocks minimum trigger interval note 0 0 0 52 11 63 0 0 1 104 22 126 0 1 0 156 33 189 0 1 1 208 44 252 1 0 0 260 55 315 1 0 1 312 66 378 1 1 0 364 77 441 1 1 1 416 88 504 note target (2) conversion time in timer trigge r mode and external trigger mode the table below shows the conversion time in t he timer trigger mode and external trigger mode. in the external trigger mode, analog delay time (80 ns (typ.)) required to eliminate noise must be also taken into consideration in addition to the a/d conversion time shown below. table 14-5. conversion time in timer tr igger mode and external trigger mode fr2 fr1 fr0 number of conversion clocks number of initialization clocks minimum trigger interval note 0 0 0 52 9 61 0 0 1 104 18 122 0 1 0 156 27 183 0 1 1 208 36 244 1 0 0 260 45 305 1 0 1 312 54 366 1 1 0 364 63 427 1 1 1 416 72 488 note target
chapter 14 a/d converter user?s manual u16397ej3v0ud 647 figure 14-16. outline of a/ d conversion operation time system clock conversion operation time sampling 2: 11 14.8.6 stabilization time immediately after clock supply to the a/d converter was started by setting the adm2.adcae bit to 1 and when the idle/software stop mode has been released, time during which the analog circuit stabilizes must be secured. in order that a/d conversion is correctly executed when it is start ed, the stabilization time of the analog circuit as well as a/d conversion time are necessary. the v850e/ma3 uses hardware to ensure the lapse of the stabilization time. the stabilization time is as shown in table 14-6 stabilization time . in the software trigger mode, the trigger is kept waiting until the stabilization time elapses. in the timer trigger mode and external trigger mode, the trigger is ignored even if it is input within the stabilization time , and the converter waits for input of a new trigger. table 14-6. stabilization time fr2 fr1 fr0 number of stabilization time clocks 0 0 0 31 0 0 1 60 0 1 0 89 0 1 1 118 1 0 0 147 1 0 1 176 1 1 0 205 1 1 1 234 14.8.7 variation of a/d conversion results the results of the a/d conversion may vary depending on the fluctuation of t he supply voltage, or may be affected by noise. to reduce the variation, take counteractive measures with the program such as averaging the a/d conversion results.
chapter 14 a/d converter user?s manual u16397ej3v0ud 648 14.9 how to read a/d converter characteristics table here, special terms unique to the a/d converter are explained. (1) resolution this is the minimum analog input voltage that can be identified. that is, the percentage of the analog input voltage per bit of digital output is called 1lsb (leas t significant bit). the percentage of 1lsb with respect to the full scale is expressed by %fsr (full scale range). %fsr indicates the ratio of analog input voltage that can be converted as a percentage, and is always r epresented by the following formula regardless of the resolution. 1%fsr = (max. value of analog input voltage that can be converted ? min. value of analog input voltage that can be converted)/100 = (av dd0 ? 0)/100 = av dd0 /100 1lsb is as follows when the resolution is 10 bits. 1lsb = 1/2 10 = 1/1024 = 0.098%fsr accuracy has no relation to resolution, but is determined by overall error. (2) overall error this shows the maximum error value between the actual measured value and the theoretical value. zero-scale error, full-scale error, lin earity error and errors that are combi nations of these express the overall error. note that the quantization error is not included in the overall erro r in the characteristics table. figure 14-17. overall error ideal line 0 ...... 0 1 ...... 1 digital output overall error analog input av dd0 0
chapter 14 a/d converter user?s manual u16397ej3v0ud 649 (3) quantization error when analog values are converted to digital values, a 1/2lsb error naturally occurs. in an a/d converter, an analog input voltage in a range of 1/2lsb is converted to the same di gital code, so a quantization error cannot be avoided. note that the quantization error is not included in the over all error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. figure 14-18. quan tization error 0 ...... 0 1 ...... 1 digital output quantization error 1/2lsb 1/2lsb analog input 0 av dd0 (4) zero-scale error this shows the difference between the actual meas urement value of the a nalog input voltage and the theoretical value (1/2 lsb) when the digital output changes from 0??000 to 0??001. figure 14-19. zero-scale error 111 011 010 001 zero-scale error ideal line 000 01 2 3 av dd0 digital output (lower 3 bits) analog input (lsb) ? 1 100
chapter 14 a/d converter user?s manual u16397ej3v0ud 650 (5) full-scale error this shows the difference between the actual meas urement value of the a nalog input voltage and the theoretical value (3/2lsb) when the digital output changes from 1??110 to 1??111. figure 14-20. full-scale error 100 011 010 000 0 av dd0 av dd0 ? 1 av dd0 ? 2 av dd0 ? 3 digital output (lower 3 bits) analog input (lsb) full-scale error 111 (6) differential linearity error while the ideal width of code output is 1lsb, this indicates the differ ence between the actual measurement value and the ideal value. this indicates the basic characteristics of the a/d conv ersion when the voltage applied to the analog input pins of the same channel is consistent ly increased bit by bit from av ss0 to av dd0 . when the input voltage is increased or decreased, or when two or more channels are used, see 14.9 (2) overall error . figure 14-21. differential linearity error 0 av dd0 digital output analog input differential linearity error 1 ...... 1 0 ...... 0 ideal 1lsb width
chapter 14 a/d converter user?s manual u16397ej3v0ud 651 (7) integral linearity error this shows the degree to which the conversion characteri stics deviate from the ideal linear relationship. it expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. figure 14-22. integral linearity error 0 av dd0 digital output analog input integral linearity error ideal line 1 ...... 1 0 ...... 0 (8) conversion time this expresses the time from when a trigger is gener ated to the time when the digital output was obtained. the sampling time is included in the conv ersion time in the characteristics table. (9) sampling time this is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. figure 14-23. sampling time sampling time conversion time
user?s manual u16397ej3v0ud 652 chapter 15 d/a converter 15.1 functions the d/a converter has the following functions. { 8-bit resolution 2 channels (dac0, dac1) { r-2r ladder method { settling time: 3 s (max.) { analog output voltage: av dd1 m/256 (m = 0 to 255; value set to da0csn register) { operation modes: normal mo de, real-time output mode remark n = 0, 1 15.2 configuration the d/a converter configur ation is shown below. figure 15-1. block diagram of d/a converter da0cs0 r-2r ladder resistor r-2r ladder resistor da0cs1 ano0 ano1 da0ce0 da0ce1 da0cs0 write da0md0 intcmd2 da0cs1 write da0md1 intcmd3 av dd1 av ss1 caution do not turn off power to the av dd1 pin even in the standby mode.
chapter 15 d/a converter user?s manual u16397ej3v0ud 653 the d/a converter consists of the following hardware. table 15-1. configuration of d/a converter item configuration control registers d/a converter mode register (da0m) d/a conversion value setting regi sters 0 and 1 (da0cs0 and da0cs1) 15.3 control registers the registers that control the d/ a converter are as follows. ? d/a converter mode register (da0m) ? d/a conversion value setting registers 0 and 1 (da0cs0 and da0cs1) (1) d/a converter mode register (da0m) the da0m register controls the operation of the d/a converter. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 normal mode real-time output mode note da0mdn 0 1 selection of d/a converter operation mode (n = 0, 1) da0m 0 da0ce1 da0ce0 0 0 da0md1 da0md0 after reset: 00h r/w address: fffff2c2h operation disabled operation enabled da0cen 0 1 d/a converter operation enable/disable control (n = 0, 1) note the output trigger in the real-time outpu t mode (da0mdn bit = 1) is as follows. ? when n = 0: intcmd2 signal (see chapter 10 16-bit interval timer d (tmd) ) ? when n = 1: intcmd3 signal (see chapter 10 16-bit interval timer d (tmd) ) caution the output goes into a high-impedance state when d/a conversion is stopped (da0cen bit = 0).
chapter 15 d/a converter user?s manual u16397ej3v0ud 654 (2) d/a conversion value setting registers 0, 1 (da0cs0, da0cs1) the da0csn register sets the analog volt age value output to the anon pin. these registers can be read or written in 8-bit units. reset input clears these registers to 00h. da7 da0csn (n = 0, 1) da6 da5 da4 da3 da2 da1 da0 after reset: 00h r/w address: da0cs0 fffff2c0h, da0cs1 fffff2c1h cautions 1. in the real-time output mode (da0m.da0m dn bit = 1), set the da0c sn register before the intcmd2/intcmd3 signal is ge nerated. d/a conversion starts when the intcmd2/ intcmd3 signal is generated. 2. set the da0m.dance1 bit to 1 after setting the da0csn register.
chapter 15 d/a converter user?s manual u16397ej3v0ud 655 15.4 operation 15.4.1 operation in normal mode d/a conversion is performed using a write operation to the da0csn register as the trigger. the setting method is described below. <1> set the da0m.da0mdn bit to 0 (normal mode). <2> set the analog voltage value to be output to the anon pin to the da0csn register. steps <1> and <2> above constitute the initial settings. <3> set the da0m.da0cen bit to 1 (d/a conversion enable). d/a conversion starts when this setting is performed. <4> to perform subsequent d/a conversions, write to the da0csn register. the previous d/a conversion result is held until the next d/a conversion is performed. remark n = 0, 1 15.4.2 operation in real-time output mode d/a conversion is performed using the interrupt request signals (intcmd2 and intcmd3) of timer d2 and timer d3 (tmd2 and tmd3) as triggers. the setting method is described below. <1> set the da0m.da0mdn bit to 1 (real-time output mode). <2> set the analog voltage value to be output to the anon pin to the da0csn register. <3> set the da0m.da0cen bit to 1 (d/a conversion enable). steps <1> to <3> above consti tute the initial settings. <4> operate timer d2 and timer d3 (tmd2 and tmd3). <5> d/a conversion starts when the intcmd2 and intcmd3 signals are generated. <6> the intcmd2 and intcmd3 signals are generated when subsequent d/a conversions are performed. before performing the next d/a conversion (generation of intcmd2 and intcmd3 signals), set the analog voltage value to be output to the anon pin to the da0csn register.
chapter 15 d/a converter user?s manual u16397ej3v0ud 656 15.4.3 cautions observe the following cautions when using the d/a converter of the v850e/ma3. (1) do not change the set value of the da0csn register while the trigger signal is being issued in the real-time output mode. (2) before changing the operation mode, be sure to clear da0m.da0cen bit to 0. (3) when using the p80/ano0 and p81/ano1 pins as port pi ns, make sure that their input level changes as little as possible. (4) apply power to av dd1 at the same timing as ev dd . (5) no current can be output from the anon pin (n = 0, 1) because the output impedance of the d/a converter is high. when connecting a resistor of 2 m ? or less, insert a jfet input operational amplifier between the resistor and the anon pin. figure 15-2. external pin connection example ev dd output 10 f 0.1 f av dd1 anon av ss1 ? + jfet input operational amplifier (6) the d/a converter holds the pin status in the idle mode or software stop mode. to reduce the power consumption, clear the da0m.da0cen bit to 0. the anon pin goes into a high-impedance state when the da0cen bit = 0.
user?s manual u16397ej3v0ud 657 chapter 16 asynchronous ser ial interface a (uarta) 16.1 mode switching between uarta and other serial interface 16.1.1 mode switching between uarta0 and csib 0, uarta1 and csib1, and uarta2 and csib2 in the v850e/ma3, uarta0 and csib0, uarta1 and cs ib1, and uarta2 and csib2 function alternately, and these pins cannot be used at the same time. to use uarta0/csib0, and uarta1/csib1, the pmc4 and pfc4 registers must be set in advance. to use uarta2/csi b2, the pmc3, pfc3, and pfce3 registers must be set in advance. caution the operations related to transmission and reception of uarta0/csib0, uarta1/csib1, and uarta2/csib2 are not guaranteed if the mode is sw itched during transmission or reception. be sure to disable the unit that is not used.
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 658 figure 16-1. mode switch settings of uarta0/csib0, uarta1/csib1 pmc4 after reset: 00h r/w address: fffff448h 0 0 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0 1 2 3 4 5 6 7 pfc4 after reset: 00h r/w address: fffff468h 0 0 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 0 1 2 3 4 5 6 7 i/o port sck1 i/o asck1 input pmc45 0 1 1 specification of alternate function of p45 pin pfc45 0 1 i/o port si1 input rxd1 input pmc44 0 1 1 specification of alternate function of p44 pin pfc44 0 1 i/o port so1 output txd1 output pmc43 0 1 1 specification of alternate function of p43 pin pfc43 0 1 i/o port sck0 i/o asck0 input pmc42 0 1 1 specification of alternate function of p42 pin pfc42 0 1 i/o port si0 input rxd0 input pmc41 0 1 1 specification of alternate function of p41 pin pfc41 0 1 i/o port so0 output txd0 output pmc40 0 1 1 specification of alternate function of p40 pin pfc40 0 1 remark x = don?t care
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 659 figure 16-2. uarta2/csib2 mode switch settings pmc3 after reset: 00h r/w address: fffff446h pmc37 0 0 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 pfc3 after reset: 00h r/w address: fffff466h 0 0 0 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h 0 0 0 pfce34 pfce33 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port rxd3 input scl note i/o pmc34 0 1 1 specification of alternate function of p34 pin pfce34 0 1 pfc34 1 0 i/o port txd3 output sda note i/o pmc33 0 1 1 specification of alternate function of p33 pin pfce33 0 1 pfc33 1 0 i/o port asck2 input sck2 i/o pmc32 0 1 1 specification of alternate function of p32 pin pfce32 0 1 pfc32 1 0 i/o port rxd2 input si2 input pmc31 0 1 1 specification of alternate function of p31 pin pfce31 0 1 pfc31 1 0 i/o port txd2 output so2 output pmc30 0 1 1 specification of alternate function of p30 pin pfce30 0 1 pfc30 1 0 note i 2 c bus versions (y products) only when using the sda and scl pins, the pins functi on as dummy open-drain output pins (p-ch side is always off). remark x = don?t care
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 660 16.1.2 uarta3/i 2 c mode switching in i 2 c bus versions (y products) of the v850e/ma3, uarta3 and i 2 c function alternately, and these pins cannot be used at the same time. to switch between uarta3 and i 2 c, the pmc3, pfc4, and pfce3 registers must be set in advance. caution the operations related to tr ansmission and reception of uarta3/i 2 c are not guaranteed if the mode is switched during transmissi on or reception. be sure to disable the unit that is not used. figure 16-3. uarta3/i 2 c mode switch settings pmc3 after reset: 00h r/w address: fffff446h pmc37 0 0 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 pfc3 after reset: 00h r/w address: fffff466h 0 0 0 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h 0 0 0 pfce34 pfce33 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port rxd3 input scl note i/o pmc34 0 1 1 specification of alternate function of p34 pin pfce34 0 1 pfc34 1 0 i/o port txd3 output sda note i/o pmc33 0 1 1 specification of alternate function of p33 pin pfce33 0 1 pfc33 1 0 note i 2 c bus versions (y products) only when using the sda and scl pins, the pins functi on as dummy open-drain output pins (p-ch side is always off). remark x = don?t care
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 661 16.2 features { transfer rate: 300 bps to 5 mbps (using peripheral clock (f xx ) of 80 mhz and dedicated baud rate generator) { full-duplex communication: internal uarta receive data register n (uanrx) internal uarta transmit data register n (uantx) { 2-pin configuration: txdn: transmit data output pin rxdn: receive data input pin { reception error output function ? parity error ? framing error ? overrun error { interrupt sources: 3 ? reception error interrupt (intsern): this inte rrupt is generated by oring the three types of reception errors ? reception end interrupt (intsrn): this interrupt occurs upon transfer of receive data from the shift register to the uanrx register after serial transfer end, in the reception enabled status. ? transmission enable interrupt (intstn): this interrupt occurs upon transfer of transmit data from the uantx register to the shift regi ster in the transmission enabled status. { character length: 7, 8 bits { parity function: odd, even, 0, none { transmission stop bit: 1, 2 bits { on-chip dedicated baud rate generator { msb-/lsb-first transfer selectable { transmit/receive data inverted input/output possible remark n = 0 to 3
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 662 16.3 configuration the block diagram of the uartan is shown below. figure 16-4. block diagram of uartan uanotp0 uanctl0 uanstr uanctl1 uanctl2 clock selector uanrx reception unit transmission unit transmit shift register transmission controller reception controller baud rate generator receive shift register filter selector baud rate generator selector parity framing overrun uantx internal bus internal bus intsrn intstn txdn rxdn f xx /2 to f xx /2048 intsern asck0 to asck2 note note uarta0 to uarta2 only remarks 1. n = 0 to 3 2. for the configuration of the baud rate generator, see figure 16-12 . uartan consists of the following hardware units. table 16-1. configuration of uartan item configuration registers uartan control register 0 (uanctl0) uartan control register 1 (uanctl1) uartan control register 2 (uanctl2) uartan option control register 0 (uanopt0) uartan status register (uanstr) uartan receive shift register uartan receive data register (uanrx) uartan transmit shift register uartan transmit data register (uantx)
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 663 (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register used to specify the uartan operation. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register used to select the base clock (f uclk ) for the uartan. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register us ed to control the baud rate for the uartan. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register used to control serial transfer for the uartan. (5) uartan status register (uanstr) the uanstr register consists of flags indicating the e rror contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrenc e of a reception error and is cleared (to 0) by reading the uanstr register. (6) uartan receive shift register this is a shift register used to convert the serial data input to the rxdn pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the uanrx register. this register cannot be manipulated directly. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit register that holds receiv e data. when 7 characters are received, 0 is stored in the highest bit (when data is received lsb first). in the reception enabled status, receive data is transfe rred from the uartan receive shift register to the uanrx register in synchronization with the comple tion of shift-in processing of 1 frame. transfer to the uanrx register also causes the recepti on end interrupt request signal (intsrn) to be output. (8) uartan transmit shift register the uartan transmit shift register is a shift register used to convert the parallel data transferred from the uantx register into serial data. when 1 byte of data is transferred from the uantx register , the uartan transmit shift register data is output from the txdn pin. this register cannot be manipulated directly. (9) uartan transmit data register (uantx) the uantx register is an 8-bit transmit data buffer. transmission starts when transmit data is written to the uantx register. when data can be wri tten to the uantx register (when dat a of one frame is transferred from the uantx register to the uartan transmit shift regi ster), the transmission enable interrupt request signal (intstn) is generated.
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 664 16.4 control registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that c ontrols the uartan serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 10h. (1/2) uanpwr disable uartan operation (uartan reset asynchronously) enable uartan operation uanpwr 0 1 uartan operation control uanctl0 (n = 0 to 3) uantxe uanrxe uandir uanps1 uanps0 uancl uansl <6> <5> <4> 3 2 1 after reset: 10h r/w address: ua0ctl0 fffffa00h, ua1ctl0 fffffa10h ua2ctl0 fffffa20h, ua3ctl0 fffffa30h the uartan operation is controlled by the uanpwr bit. the txdan pin output is fixed to high level by clearing the uanpwr bit to 0 (fixed to low level if uanopt0.uantdl bit = 1). disable transmission operation enable transmission operation uantxe 0 1 transmission operation enable ? to start transmission, set the uanpwr bit to 1 and then set the uantxe bit to 1. ? to initialize the transmission unit, clear the uantxe bit to 0, wait for two cycles of the base clock (f uclk ), and then set the uantxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 16.7 (1) (a) base clock ).  when the operation is enabled (uanpwr bit = 1), the transmission operation is enabled after two or more cycles of the base clock (f uclk ) have elapsed since uantxe = 1.  when the uanpwr bit is cleared to 0, the status of the internal circuit becomes the same status as uantxe bit = 0 by the uanpwr bit even if the uantxe bit is 1. the transmission operation is enabled when the uanpwr bit is set to 1 again. <7> 0
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 665 (2/2) 7 bits 8 bits uancl note 0 1 specification of data character length of 1 frame of transmit/receive data 1 bit 2 bits uansl note 0 1 specification of length of stop bit for transmit data only the first bit of the receive data stop bits is checked, regardless of the value of the uansl bit. if ?reception with 0 parity? is selected during reception, a parity check is not performed. therefore, since the uanstr.uanpe bit is not set, no error interrupt due to a parity error is output. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check uanps1 note 0 0 1 1 parity selection during transmission parity selection during reception uanps0 note 0 1 0 1 msb-first transfer lsb-first transfer uandir note 0 1 transfer direction selection disable reception operation enable reception operation uanrxe 0 1 reception operation enable  to start reception, set the uanpwr bit to 1 and then set the uanrxe bit to 1.  to initialize the reception unit, clear the uanrxe bit to 0, wait for two cycles of the base clock, and then set the uanrxe bit to 1 again. otherwise, initialization may not be executed (for the base clock, see 16.7 (1) (a) base clock ).  when the operation is enabled (uanpwr bit = 1), the reception operation is enabled after two or more cycles of the base clock (f uclk ) have elapsed since uanrxe = 1.  when the uanpwr bit is cleared to 0, the status of the internal circuit becomes the same status as uanrxe bit = 0 by the uanpwr bit even if the uanrxe bit is 1. the reception operation is enabled when the uanpwr bit is set to 1 again. note this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = uanrxe bit = 0. however, setting any or all of the uanpwr, uantxe, and uanrxe bits to 1 at the same time is possible. remark for details of parity, see 16.6.6 parity types and operations . (2) uartan control register 1 (uanctl1) for details, see 16.7 (2) uartan control register 1 (uanctl1) . (3) uartan control register 2 (uanctl2) for details, see 16.7 (3) uartan control register 2 (uanctl2) .
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 666 (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit regist er that controls the serial transfer operation of the uartan register. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 14h. 0 uanopt0 (n = 0 to 3) 0 0 1 0 1 uantdl uanrdl 654321 after reset: 14h r/w address: ua0opt0 fffffa03h, ua1opt0 fffffa13h ua2opt0 fffffa23h, ua3opt0 fffffa33h 7 0  the output level of the txdn pin can be inverted using the uantdl bit.  this register can be set when the uanctl0.uanpwr bit = 0 or when the uanctl0.uantxe bit = 0. normal output of transfer data inverted output of transfer data uantdl 0 1 transmit data level bit  the input level of the rxdn pin can be inverted using the uanrdl bit.  this register can be set when the uanpwr bit = 0 or the uanctl0.uanrxe bit = 0.  when the uanrdl bit is set to 1 (inverted input of receive data), reception must be enabled (uanctl0.uanrxe bit = 1) after setting the data reception pin to the uart reception pin (rxdn) when reception is started. when the pin mode is changed after reception is enabled, the start bit will be mistakenly detected if the pin level is high. normal input of transfer data inverted input of transfer data uanrdl 0 1 receive data level bit caution be sure to clear bits 3 and 5 to 7 to ?0?, and set bits 4 and 2 to ?1?. operation with other settings is not guaranteed. (5) uartan status register (uanstr) the uanstr register is an 8-bit register that displays t he uartan transfer status and reception error contents. this register can be read or written in 8-bit or 1-bi t units, but the uantsf bit is a read-only bit, while the uanpe, uanfe, and uanove bits can both be read and written. however, these bits can only be cleared by writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained). the initialization conditions are shown below. register/bit initialization conditions uanstr register ? after reset ? uanctl0.uanpwr = 0 uantsf bit ? uanctl0.uantxe = 0 uanpe, uanfe, uanove bits ? 0 write ? uanctl0.uanrxe = 0
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 667 uantsf  when the uanpwr bit = 0 or the uantxe bit = 0 has been set.  when, following transfer end, there was no next data transfer from uantx register write to uantx register uantsf 0 1 transfer status flag uanstr (n = 0 to 3) 0 0 0 0 uanpe uanfe uanove 6 5 4 3 <2> <1> after reset: 00h r/w address: ua0str fffffa04h, ua1str fffffa14h, ua2str fffffa24h, ua3str fffffa34h the uantsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uantsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uantsf bit = 1.  when the uanpwr bit = 0 or the uanrxe bit = 0 has been set.  when 0 has been written when parity of data and parity bit do not match during reception. uanpe 0 1 parity error flag  the operation of the uanpe bit is controlled by the settings of the uanctl0.uanps1 and uanctl0.uanps0 bits.  the uanpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained.  when the uanpwr bit = 0 or the uanrxe bit = 0 has been set  when 0 has been written when no stop bit is detected during reception uanfe 0 1 framing error flag  only the first bit of the receive data stop bits is checked, regardless of the value of the uanctl0.uansl bit.  the uanfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the value is retained .  when the uanpwr bit = 0 or the uanrxe bit = 0 has been set.  when 0 has been written when receive data has been set to the uanrx register and the next receive operation is ended before that receive data has been read. uanove 0 1 overrun error flag  when an overrun error occurs, the data is discarded without the next receive data being written to the uanrx register.  the uanove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the value is retained . <7> <0>
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 668 (6) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer register that st ores parallel data converted by the uartan receive shift register. the data stored in the uartan receive shift register is transferred to the uanrx regi ster upon end of reception of 1 byte of data. a reception end interrupt reques t signal (intsrn) is generated at this timing. during lsb-first reception when the data length has been s pecified as 7 bits, the receive data is transferred to bits 6 to 0 of the uanrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the uanrx register and the lsb always becomes 0. when an overrun error occurs (the uanstr.uanove bit = 1), the receive data at this time is not transferred to the uanrx register and is discarded. this register is read-only, in 8-bit units. in addition to reset input, the uanrx register can be set to ffh by clearing the uanctl0.uanpwr bit to 0. uanrx (n = 0 to 3) 654321 after reset: ffh r address: ua0rx fffffa06h, ua1rx fffffa16h, ua2rx fffffa26h, ua3rx fffffa36h 7 0 (7) uartan transmit data register (uantx) the uantx register is an 8-bit register used to set transmit data. transmission starts when transmit data is written to t he uantx register in the transmission enabled status (uanctl0.uantxe bit = 1). when t he data of the uantx register has been transferred to the uartan transmit shift register, the transmission enable interrupt request signal (intstn) is generated. this register can be read or written in 8-bit units. reset input sets this register to ffh. uantx (n = 0 to 3) 654321 after reset: ffh r/w address: ua0tx fffffa07h, ua1tx fffffa17h, ua2tx fffffa27h, ua3tx fffffa37h 7 0
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 669 16.5 interrupt request signals the following three interrupt request signals are generated from uartan. ? reception error interrupt request signal (intsern) ? reception end interrupt request signal (intsrn) ? transmission enable interrupt request signal (intstn) among these three interrupt signals, the reception error in terrupt signal has the highest default priority, and the reception end interrupt request signal and transmission enable interrupt request signal follow in this order. table 16-2. interrupts and their default priorities interrupt priority reception error high reception end ? transmission enable low (1) reception error interrupt request signal (intsern) a reception error interrupt request signal is generated while reception is enabled by oring the three types of reception errors (parity error, framing error, and over run error) explained in the uanstr register section. (2) reception end interrupt request signal (intsrn) a reception end interrupt request signal is output when da ta is shifted into the uartan receive shift register and transferred to the uanrx register in the reception enabled status. no reception end interrupt request signal is generated in the reception disabled status. (3) transmission enable interr upt request signal (intstn) if transmit data is transferred from the uantx register to the uartan transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated.
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 670 16.6 operation 16.6.1 data format full-duplex serial data reception and transmission is performed. as shown in figure 16-5, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data frame, parity selection, s pecification of the stop bit length, and specification of msb/lsb-first transfer ar e performed using the uanctl0 register. moreover, control of uartan output/inverted output for the txdn bit is performed using the uanopt0.uantdl bit. ? start bit ..................1 bit ? character bits ........7 bits/8 bits ? parity bit ................even parity/odd parity/0 parity/no parity ? stop bit ..................1 bit/2 bits
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 671 figure 16-5. uarta transmit/receive data format (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txdn inversion 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (d) 7-bit data length, lsb first, odd pa rity, 2 stop bits, transfer data: 36h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 parity bit stop bit stop bit (e) 8-bit data length, lsb first, no pa rity, 1 stop bit, transfer data: 87h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 672 16.6.2 uart transmission first set the base clock of uartan with the uanctl1 regi ster and the baud rate clock wi th the uanctl2 register. set the output level of transmit data with the uanopt0 register. also set a trans fer direction, parity, data character length, and stop bit length with the uanctl0 register. a high level is output to the txdn pin by setting the uanctl0.uanpwr bit to 1. next, the transmission enabled status is set by setting t he uanctl0.uantxe bit to 1, and transmission is started by writing transmit data to the uantx register. the st art bit, parity bit, and stop bit are automatically added. since the cts (transmit enable signal) input pin is not pr ovided in uartan, use a port to check that reception is enabled at the transmit destination. the data in the uantx register is tr ansferred to the uartan transmit shift register upon the start of the transmit operation. a transmission enable interrupt request signal (intstn) is generated upon end of tr ansmission of the data of the uantx register to the uartan transmit shift register, and th ereafter the contents of the ua rtan transmit shift register are output to the txdn pin. write of the next transmit data to the uantx register is enabled by generating the intstn signal. remark n = 0 to 3 figure 16-6. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intstn remark lsb first
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 673 16.6.3 continuous transmission procedure uartan can write the next transmit data to the uantx regist er when the uartan transmit shift register starts the shift operation. the transmit timing of the uartan transmi t shift register can be judged from the transmission enable interrupt request signal (intstn). an efficient communication rate is realized by writing t he data to be transmitted next to the uantx register during transfer. caution during continuous transmission execution, perform initialization after checking that the uanstr.uantsf bit is 0. the transmit data cannot be guaranteed when initialization is performed while the uantsf bit is 1. remark n = 0 to 3 figure 16-7. continuous transmission processing flow start register settings uantx write yes yes no no occurrence of transmission interrupt? required number of writes performed? end
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 674 figure 16-8. continuous transmission operation timing (a) transmission start start data (1) data (1) txdn pin uantx register transmission shift register intstn signal uantsf bit data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) transmission end start data (n ? 1) data (n ? 1) data (n ? 1) data (n) ff data (n) txdn pin uantx register transmission shift register intstn pin uantsf bit uanpwr or uantxe bit parity stop stop start data (n) parity parity stop remark n = 0 to 3
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 675 16.6.4 uart reception first set the base clock of uartan with the uanctl1 regi ster and the baud rate clock wi th the uanctl2 register. set the input level of receive data with the uanopt0 register. also set a trans fer direction, parity, data character length, and stop bit length with the uanctl0 register. the reception wait status is set by setting the uanctl0.uanpwr bit to 1 and then setting the uanctl0.uanrxe bit to 1. in the reception wait status, the rxdn pi n is monitored and start bit detection is performed. start bit detection is performed using a two-step detection routine. first the rising edge of the rxdn pin is detected and samp ling is started at the falling edge. the start bit is recognized if the rxdn pin is low level at the start bit sampling point. after a start bit has been recognized, the receive operation starts, and serial data is saved to the uart an receive shift register according to the set baud rate. when the reception end interrupt request signal (intsrn) is output upon reception of the stop bit, the data of the uartan receive shift register is written to the uanrx regist er. however, if an overrun error occurs (uanstr.uanove bit = 1), the receive data at this time is not wr itten to the uanrx register and is discarded. even if a parity error (uanstr.uanpe bit= 1) or a frami ng error (uanstr.uanfe bit = 1) occurs during reception, reception continues until the reception position of the first stop bit, and intser n is output following reception end. remark n = 0 to 3 figure 16-9. uart reception start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intsrn signal uanrx register remark : start bit sampling point
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 676 cautions 1. be sure to read the uanrx register even when a reception error occurs. if the uanrx register is not read, an overrun error occurs during r eception of the next data, and reception errors continue occurring indefinitely. 2. the operation during recepti on is performed assuming that th ere is only one stop bit. a second stop bit is ignored. 3. when reception is completed, read the ua nrx register after the reception end interrupt request signal (intsrn) has been generated, and clear the uanpwr or uanrxe bit to 0. if the uanpwr or uanrxe bit is cleared to 0 befo re the intsrn signal is generated, the read value of the uanrx register cannot be guaranteed. 4. if receive end processing (intsrn signal gene ration) of uartan and the uanpwr bit = 0 or uanrxe bit = 0 conflict, the intsrn signal may be generated in spite of these being no data stored in the uanrx register. to end reception without waiti ng intsrn signal genera tion, be sure to set (1) the interrupt mask flag (sricn.srmkn), clear (0) the interrupt request flag (sricn.srifn) in that order, and then clear the uanpwr bit or uanrxe bit to 0. 16.6.5 reception errors errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. data reception result error flags are set in the uanstr register and a reception error interrupt request signal (intsern) is output when an error occurs. it is possible to ascertain which error occurred during reception by reading the contents of the uanstr register. clear the reception error flag by writing 0 to it after reading it. caution the reception end interrupt request signal (intsrn) and reception error interrupt request signal (intsern) are not generated simultaneously. the intsrn signal is gene rated when a reception ends normally. the intsern signa l is generated and the intsrn signal is not generated when a reception error occurs. remark n = 0 to 3 ? reception error causes error flag reception error cause uanpe parity error received parity bit does not match the setting uanfe framing error stop bit not detected uanove overrun error reception of next data ended before data was read from uanrx register
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 677 16.6.6 parity types and operations the parity bit is used to detect bit errors in the comm unication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect odd-count bit errors. in the case of 0 parity and no parity, errors cannot be detected. (a) even parity (i) during transmission the number of bits whose value is ?1? among the transmi t data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 1 ? even number of bits whose value is ?1? among transmit data: 0 (ii) during reception the number of bits whose value is ?1? among the rec eption data, including the parit y bit, is counted, and if it is an odd number, a parity error is output. (b) odd parity (i) during transmission opposite to even parity, the number of bits whose value is ?1? among t he transmit data, including the parity bit, is controlled so that it is an odd number . the parity bit values are as follows. ? odd number of bits whose value is ?1? among transmit data: 0 ? even number of bits whose value is ?1? among transmit data: 1 (ii) during reception the number of bits whose value is ?1? among the receiv e data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity e rror occurs, regardless of whether the parity bit is 0 or 1. (d) no parity no parity bit is added to the transmit data. reception is performed assuming that ther e is no parity bit. no parity error occurs since there is no parity bit.
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 678 16.6.7 receive data noise filter this filter samples the rxdn pin using the base clock (f uclk ) of the prescaler output. when the same sampling value is read twice, the match det ector output changes and the rxdan signal is sampled as the input data. therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal circuit (see figure 16-11 ). see 16.7 (1) (a) base clock regarding the base clock. moreover, since the circuit is as shown in figure 16-10, the processing that goes on wit hin the receive operation is delayed by 3 clocks in relation to the external signal status. remark n = 0 to 3 figure 16-10. noise filter circuit match detector in base clock (f uclk ) rxdn qin ld_en q internal signal c internal signal b in q internal signal a figure 16-11. timing of rxdn signal judged as noise internal signal b base clock (f uclk ) rxdn (input) internal signal c mismatch (judged as noise) internal signal a mismatch (judged as noise) match match
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 679 16.7 dedicated baud rate generator the dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartan. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. (1) baud rate generator configuration figure 16-12. configuration of baud rate generator f uclk selector uanpwr bit 8-bit counter match detector baud rate uanctl2: uanbrs7 to uanbrs0 1/2 uanpwr, uantxe bits (or uanrxe bit) uanctl1: uancks3 to uancks0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 f xx /2048 asck0 to asck2 note note valid only for the uarta0 to uarta2 only. setting uarta3 is prohibited. caution if the cpu clock (f cpu ) is slower than f uclk , uartan cannot be used. remarks 1. n = 0 to 3 2. f xx : peripheral clock frequency (a) base clock when the uanctl0.uanpwr bit is 1, the cl ock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits is supplied to the 8-bit counter. this clock is called the base clock. when the uanpwr bit = 0, f uclk is fixed to the low level. (b) serial clock generation a serial clock can be generated by setting the uanctl1 register and the uanctl2 register. the base clock (f uclk ) is selected by uanctl1.uancks3 to uanctl1.uancks0 bits. the frequency division value for the 8-bit count er can be set using the uanctl2.uanbrs7 to uanctl2.uanbrs0 bits.
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 680 (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register that selects the uartan base clock. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution clear the uanctl0.uanpwr bit to 0 before rewriting the uanctl1 register. 0 uanctl1 (n = 0 to 3) 0 0 0 uancks3 uancks2 uancks1 uancks0 654321 after reset: 00h r/w address: ua0ctl1 fffffa01h, ua1ctl1 fffffa11h ua2ctl1 fffffa21h, ua3ctl1 fffffa31h 7 0 f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xx /2,048 external clock note (asck0 to asck2 pins) setting prohibited uancks2 0 0 0 0 1 1 1 1 0 0 0 0 uancks3 0 0 0 0 0 0 0 0 1 1 1 1 base clock (f uclk ) selection uancks1 0 0 1 1 0 0 1 1 0 0 1 1 uancks0 0 1 0 1 0 1 0 1 0 1 0 1 other than above note valid only for the uarta0 to uarta2 only. setting uarta3 is prohibited. remark f xx : peripheral clock frequency
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 681 (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartan. this register can be read or written in 8-bit units. reset input sets this register to ffh. caution clear the uanctl0.uanpwr bit to 0 or clear the uantxe and uanrxe bits to 00 before rewriting the uanctl2 register. uanbrs7 uanctl2 (n = 0 to 3) uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 654321 after reset: ffh r/w address: ua0ctl2 fffffa02h, ua1ctl2 fffffa12h ua2ctl2 fffffa22h, ua3ctl2 fffffa32h 7 0 uan brs7 0 0 0 0 : 1 1 1 1 uan brs6 0 0 0 0 : 1 1 1 1 uan brs5 0 0 0 0 : 1 1 1 1 uan brs4 0 0 0 0 : 1 1 1 1 uan brs3 0 0 0 0 : 1 1 1 1 uan brs2 0 1 1 1 : 1 1 1 1 uan brs1 0 0 1 : 0 0 1 1 uan brs0 0 1 0 : 0 1 0 1 default (k) 4 5 6 : 252 253 254 255 serial clock f uclk /4 f uclk /5 f uclk /6 : f uclk /252 f uclk /253 f uclk /254 f uclk /255 setting prohibited remark f uclk : frequency of base clock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 682 (4) baud rate the baud rate is obtained by the following equation. baud rate = [bps] f uclk : frequency of base clock selected by the uanctl1.uancks3 to uanctl1.uancks0 bits k: value set using the uanctl2.uanbrs7 to uanc tl2.uanbrs0 bits (k = 4, 5, 6, ..., 255) (5) baud rate error the baud rate error is obtained by the following equation. error (%) = ? 1 100 [%] cautions 1. the baud rate erro r during transmission must be wit hin the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in section (7) allowable baud rate range during reception. example peripheral clock frequency = 80 mhz = 80,000,000 hz setting value of uanctl1.uancks3 to uanctl1.uancks0 bits = 0001b (f uclk = 20,000,000 hz) setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits = 01000001b (k = 65) target baud rate = 153,600 baud rate = 20,000,000/ (2 65) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] f uclk 2 k actual baud rate (baud rate with error) target baud rate (correct baud rate)
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 683 (6) baud rate setting example table 16-3. baud rate generator setting data baud rate f xx = 80 mhz f xx = 66 mhz f xx = 50 mhz (bps) f uclk k err (%) f uclk k err (%) f uclk k err (%) 300 f xx /1,024 130 0.16 f xx /512 215 ? 0.07 f xx /512 163 ? 0.15 600 f xx /512 130 0.16 f xx /256 215 ? 0.07 f xx /256 163 ? 0.15 1,200 f xx /256 130 0.16 f xx /128 215 ? 0.07 f xx /128 163 ? 0.15 2,400 f xx /128 130 0.16 f xx /64 215 ? 0.07 f xx /64 163 ? 0.15 4,800 f xx /64 130 0.16 f xx /32 215 ? 0.07 f xx /32 163 ? 0.15 9,600 f xx /32 130 0.16 f xx /16 215 ? 0.07 f xx /16 163 ? 0.15 19,200 f xx /16 130 0.16 f xx /8 215 ? 0.07 f xx /8 163 ? 0.15 31,250 f xx /8 160 0.00 f xx /8 132 0.00 f xx /4 200 0.00 38,400 f xx /8 130 0.16 f xx /4 215 ? 0.07 f xx /4 163 ? 0.15 76,800 f xx /4 130 0.16 f xx /2 215 ? 0.07 f xx /2 163 ? 0.15 153,600 f xx /2 130 0.16 f xx /2 107 0.39 f xx /2 81 0.47 250,000 f xx /2 80 0.00 f xx /2 66 0.00 f xx /2 50 0.00 312,500 f xx /2 64 0.00 f xx /2 53 ? 0.377 f xx /2 40 0.00 2,000,000 f xx /2 10 0.00 ? ? ? ? ? ? 5,000,000 f xx /2 4 0.00 ? ? ? ? ? ? remark f xx : peripheral clock frequency f uclk : frequency of base clock selected by uanctl1.uancks3 to uanctl1.uancks0 bits k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 3) err: baud rate error (%)
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 684 (7) allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error during reception must be set within the allowable error range using the following equation. figure 16-13. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartan transfer rate start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0 to 3 as shown in figure 16-13, the receive data latch timing is determined by the counter set using the uanctl2 register following start bit detection. the transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, t he following is the theoretical result. fl = (brate) ? 1 brate: uartan baud rate (n = 0 to 3) k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 3) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 685 therefore, the maximum baud rate that can be re ceived by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the following maximum allowable transfer rate yields the following. flmax = 11 fl ? fl = fl flmax = fl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartan and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 16-4. maximum/minimum allowable baud rate error division ratio (k) maximum allowable baud rate error minimum allowable baud rate error 4 +2.32% ? 2.43% 8 +3.52% ? 3.61% 20 +4.26% ? 4.30% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.72% remarks 1. the reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy. 2. k: setting value of uanctl2.uanbrs7 to uanctl2.uanbrs0 bits (n = 0 to 3) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2
chapter 16 asynchronous serial interface a (uarta) user?s manual u16397ej3v0ud 686 (8) baud rate during cont inuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. however, timing initialization is performed via st art bit detection by the receiving side, so this has no influence on the transfer result. figure 16-14. transfer rate during continuous transfer start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of 2nd byte start bit bit 0 assuming 1 bit data length: fl; stop bit length: flstp; and base clock frequency: f uclk , we obtain the following equation. flstp = fl + 2/f uclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + (2/f uclk ) 16.8 cautions when the clock supply to uartan is stopped (for example, in idle1 or stop mode), the operation stops with each register retaining the value it had imm ediately before the clock supply was stoppe d. the txdn pin output also holds and outputs the value it had immediat ely before the clock supply was stopped. however, the operation is not guaranteed after the clock supply is resumed. therefore, after the clock supply is resumed, the circuits should be initialized by setting the uanctl0.uanpwr, uanc tl0.uanrxe, and uanctl0.uantxe bits to 000. remark n = 0 to 3
user?s manual u16397ej3v0ud 687 chapter 17 clocked serial interface b (csib) 17.1 mode switching between csib and other serial interface 17.1.1 mode switching between uarta0 and csib 0, uarta1 and csib1, and uarta2 and csib2 in the v850e/ma3, uarta0 and csib0, uarta1 and cs ib1, and uarta2 and csib2 function alternately, and these pins cannot be used at the same time. to swit ch between uarta0 and csib0, and uarta1 and csib1, the pmc4 and pfc4 registers must be set in advance. to switch between uarta2 and csib2, the pmc3, pfc3, and pfce3 registers must be set in advance. caution the operations related to transmission and reception of uarta0/csibn, uarta1/csib1, and uarta2/csib2 are not guaranteed if the mode is sw itched during transmission or reception. be sure to disable the unit that is not used. 17.2 features { transfer rate: 10 mbps (using internal clock) { master mode and slave mode selectable { 8-bit to 16-bit transfer, 3-wire serial interface { interrupt request signals (int csiern, intcsirn, intcsitn) { serial clock and data phase switchable { transfer data length selectable in 1-bit units between 8 and 16 bits { transfer data msb-first/lsb-first switchable { 3-wire transfer son: serial data output sin: serial data input sckn: serial clock output transmission mode, reception mode, an d transmission/reception mode specifiable remark n = 0 to 2
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 688 figure 17-1. mode switch settings of uarta0/csib0, uarta1/csib1 pmc4 after reset: 00h r/w address: fffff448h 0 0 pmc45 pmc44 pmc43 pmc42 pmc41 pmc40 0 1 2 3 4 5 6 7 pfc4 after reset: 00h r/w address: fffff468h 0 0 pfc45 pfc44 pfc43 pfc42 pfc41 pfc40 0 1 2 3 4 5 6 7 i/o port sck1 i/o asck1 input pmc45 0 1 1 specification of alternate function of p45 pin pfc45 0 1 i/o port si1 input rxd1 input pmc44 0 1 1 specification of alternate function of p44 pin pfc44 0 1 i/o port so1 output txd1 output pmc43 0 1 1 specification of alternate function of p43 pin pfc43 0 1 i/o port sck0 i/o asck0 input pmc42 0 1 1 specification of alternate function of p42 pin pfc42 0 1 i/o port si0 input rxd0 input pmc41 0 1 1 specification of alternate function of p41 pin pfc41 0 1 i/o port so0 output txd0 output pmc40 0 1 1 specification of alternate function of p40 pin pfc40 0 1 remark x = don?t care
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 689 figure 17-2. uarta2/csib2 mode switch settings pmc3 after reset: 00h r/w address: fffff446h pmc37 0 0 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 pfc3 after reset: 00h r/w address: fffff466h 0 0 0 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h 0 0 0 pfce34 pfce33 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port rxd3 input scl note i/o pmc34 0 1 1 specification of alternate function of p34 pin pfce34 0 1 pfc34 1 0 i/o port txd3 output sda note i/o pmc33 0 1 1 specification of alternate function of p33 pin pfce33 0 1 pfc33 1 0 i/o port asck2 input sck2 i/o pmc32 0 1 1 specification of alternate function of p32 pin pfce32 0 1 pfc32 1 0 i/o port rxd2 input si2 input pmc31 0 1 1 specification of alternate function of p31 pin pfce31 0 1 pfc31 1 0 i/o port txd2 output so2 output pmc30 0 1 1 specification of alternate function of p30 pin pfce30 0 1 pfc30 1 0 note i 2 c bus versions (y products) only when using the sda and scl pins, the pins functi on as dummy open-drain output pins (p-ch side is always off). remark x = don?t care
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 690 17.3 configuration the following shows the block diagram of csibn. figure 17-3. block diagram of csibn cbnctl2 cbnctl0 cbnstr intcsirn son intcsitn cbntx so latch cbnrx f cclk cbnctl1 intcsiern sin f xx /8 f xx /16 f xx /32 f xx /128 f xx /512 f xx /2048 f xx /8192 sckn internal bus controller phase control shift register phase control selector caution csibn cannot be used if the cpu clock (f cpu ) is slower than f cclk . remark f cclk : communication clock (10 mhz (max.)) csibn includes the following hardware. table 17-1. configuration of csibn item configuration csibn receive data register (cbnrx) registers csibn transmit data register (cbntx) csibn control register 0 (cbnctl0) csibn control register 1 (cbnctl1) csibn control register 2 (cbnctl2) control registers csibn status register (cbnstr)
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 691 (1) csibn receive data register (cbnrx) the cbnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. the receive operation is started by reading the cbnrx register in the reception enabled status. if the transfer data length is 8 bits, the lower 8 bits of th is register are read-only in 8-bit units as the cbnrxl register. reset input clears this register to 0000h. in addition to reset input, the cbnrx register can be init ialized by clearing (to 0) the cbnctl0.cbnpwr bit. after reset: 0000h r address: cbnrx cb0rx fffffd04h, cb0rxl fffffd04h, cb1rx fffffd14h, cb1rxl fffffd14h, cb2rx fffffd24h, cb2rxl fffffd24h (2) csibn transmit data register (cbntx) the cbntx register is a 16-bit buffer regist er used to write the csibn transfer data. this register can be read or written in 16-bit units. the transmit operation is started by writing data to t he cbntx register in the transmission enabled status. if the transfer data length is 8 bits, the lower 8 bits of th is register are read-only in 8-bit units as the cbntxl register. reset input clears this register to 0000h. after reset: 0000h r/w address: cbntx cb0tx fffffd06h, cb0txl fffffd06h, cb1tx fffffd16h, cb1txl fffffd16h, cb2tx fffffd26h, cb2txl fffffd26h remark the communication start conditions are shown below. transmission mode (cbntxe bit = 1, cbnr xe bit = 0): write to cbntx register transmission/reception mode (cbntxe bit = 1, cb nrxe bit = 1): write to cbntx register reception mode (cbntxe bit = 0, cbnrxe bit = 1): read from cbnrx register
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 692 17.4 control registers the following registers are used to control csibn. ? csibn control register 0 (cbnctl0) ? csibn control register 1 (cbnctl1) ? csibn control register 2 (cbnctl2) ? csibn status register (cbnstr) (1) csibn control register 0 (cbnctl0) cbnctl0 is a register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. (1/2) cbnpwr disable csibn operation and reset the cbnstr register enable csibn operation cbnpwr 0 1 specification of csibn operation disable/enable cbnctl0 (n = 0 to 2) cbntxe note cbnrxe note cbndir note 00 cbntms note cbnsce after reset: 01h r/w address:  the cbnpwr bit controls the csibn operation and resets the internal circuit. disable transmit operation enable transmit operation cbntxe note 0 1 specification of transmit operation disable/enable  the son output is low level when the cbntxe bit is 0.  when the cbnrxe bit is cleared to 0, no reception end interrupt is output even when the prescribed data is transferred in order to disable the receive operation, and the receive data (cbnrx register) is not updated. disable receive operation enable receive operation cbnrxe note 0 1 specification of receive operation disable/enable < > < > < > < > < > cb0ctl0 fffffd00h, cb1ctl0 fffffd10h, cb2ctl0 fffffd20h note these bits can only be rewritten when the cbnpwr bit = 0. however, cbnpwr bit = 1 can also be set at the same time as rewriting these bits. caution be sure to clear bits 3 and 2 to 0.
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 693 (2/2) single transfer mode continuous transfer mode cbntms note 1 0 1 transfer mode specification communication start trigger invalid communication start trigger valid cbnsce 0 1 specification of start transfer disable/enable  in master mode this bit enables or disables the communication start trigger. (a) in single reception mode clear the cbnsce bit to 0 before reading the receive data (cbnrx register) note 2 . (b) in continuous reception mode clear the cbnsce bit to 0 one communication clock before reception of the last data is ended note 3 .  in slave mode this bit enables or disables the communication start trigger. (a) in single reception mode, or continuous reception mode set the cbnsce bit to 1 note 4 .  in single transmission or transmission/reception mode, or continuous transmission mode, or transmission/reception mode the function of the cbnsce bit is invalid. it is recommended to set this bit to 1. msb first lsb first cbndir note 1 0 1 specification of transfer direction mode (msb/lsb)  when using single transmission or transmission/reception mode with communication type 2 or 4 (cbnctl1.cbndap bit = 1), write the transfer data to the cbntx register after checking that the cbnstr.cbntsf bit is 0.  when using dma, use the continuous transfer mode. notes 1. these bits can only be rewritten when the cbnpwr bit = 0. however, the cbnpwr can be set to 1 at the same time as these bits are rewritten. 2. if the cbnsce bit is read while it is 1, the next communication operation is started. 3. the cbnsce bit is not cleared to 0 one communication clock before the end of the last data re ception, the next communication operation is automatically started. to start communication operation again after reading the last data, set the cbnsce bit to 1 and perform a dummy read of the cbnrx register. 4. to start the reception, a dummy read is necessary.
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 694 (a) how to use cbnsce bit (i) in single reception mode <1> when the reception of the la st data is completed with intcsirn interrupt servicing, clear the cbnsce bit to 0, and then read the cbnrx register. <2> when the reception is disabled after the rec eption of the last data has been completed, check that the cbnstr.cbntsf bit is 0, and then cl ear the cbnpwr and cbnrxe bits to 0. to continue reception, set the cbnsce bit to 1 and start the next receive operation by performing a dummy read of the cbnrx register. (ii) in continu ous reception mode <1> clear the cbnsce bit to 0 during reception of the last data with intcsirn interrupt servicing by the reception before the last recept ion, and then read the cbnrx register. <2> after receiving the intcsirn signal of the last reception, read the last data from the cbnrx register. <3> when the reception is disabled after the rec eption of the last data has been completed, check that the cbnstr.cbntsf bit is 0, and then cl ear the cbnpwr and cbnrxe bits to 0. to continue reception, set the cbnsce bit to 1 and start the next receive operation by performing a dummy read of the cbnrx register. caution in continuous recep tion mode, the serial clock is not stopped until the reception executed when the cbnsce bit is cleared to 0 is completed after the reception is started by a dummy read.
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 695 (2) csibn control register 1 (cbnctl1) cbnctl1 is an 8-bit register that controls the csibn serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution the cbnctl1 register can be rewr itten only when the cbntl0.cbnpwr bit. 0 cbnckp 0 0 1 1 specification of data transmission/ reception timing in relation to sckn cbnctl1 (n = 0 to 2) 0 cbndap 0 1 0 1 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 after reset: 00h r/w address: cbncks2 0 0 0 0 1 1 1 1 cbncks1 0 0 1 1 0 0 1 1 cbncks0 0 1 0 1 0 1 0 1 communication clock (f cclk ) f xx /8 f xx /16 f xx /32 f xx /128 f xx /512 f xx /2048 f xx /8192 external clock (sckn) master mode master mode master mode master mode master mode master mode master mode slave mode mode d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) d7 d6 d5 d4 d3 d2 d1 d0 sckn (i/o) sin capture son (output) communication type 1 communication type 2 communication type 3 communication type 4 cb0ctl1 fffffd01h, cb1ctl1 fffffd11h, cb2ctl1 fffffd21h caution set f cclk to 10 mhz or lower.
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 696 (3) csibn control register 2 (cbnctl2) cbnctl2 is an 8-bit register that controls the number of csibn serial transfer bits. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution the cbnctl2 register can be rewritten only when the cbnctl0.cbnpwr bit = 0 or when both the cbntxe and cbnrxe bits = 0. after reset: 00h r/w address: 0 cbnctl2 (n = 0 to 2) 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits cbncl3 0 0 0 0 0 0 0 0 1 cbncl2 0 0 0 0 1 1 1 1 cbncl1 0 0 1 1 0 0 1 1 cbncl0 0 1 0 1 0 1 0 1 serial register bit length cb0ctl2 fffffd02h, cb1ctl2 fffffd12h, cb2ctl2 fffffd22h remark if the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the lsb of t he cbntx and cbnrx registers.
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 697 (a) transfer data length change function the csibn transfer data length can be set in 1-bit units between 8 and 16 bits using the cbnctl2.cbncl3 to cbnctl2.cbncl0 bits. when the transfer bit length is set to a value othe r than 16 bits, set the data to the cbntx or cbnrx register starting from the lsb, regardless of whether t he transfer start bit is the msb or lsb. any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. (i) transfer bit length = 10 bits, msb first 15 10 9 0 son sin insertion of 0 (ii) transfer bit length = 12 bits, lsb first 0 son 11 12 15 sin insertion of 0
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 698 (4) csibn status register (cbnstr) cbnstr is an 8-bit register t hat displays the csibn status. this register can be read or written in 8-bit or 1-bit units, but the cbntsf flag is read-only. reset input clears this register to 00h. in addition to reset input, the cbnstr register can be initialized by clearing (0) the cbnctl0.cbnpwr bit. cbntsf communication stopped communicating cbntsf 0 1 communication status flag cbnstr (n = 0 to 2) 00 0 00 0 cbnove after reset: 00h r/w address:  during transmission, this register is set when data is prepared in the cbntx register, and during reception, it is set when a dummy read of the cbnrx register is performed. when transfer ends, this flag is cleared to 0 at the last edge of the clock. no overrun overrun cbnove 0 1 overrun error flag  an overrun error occurs when the next reception starts without performing a cpu read of the value of the cbnrx register, upon end of the receive operation. the cbnove flag displays the overrun error occurrence status in this case.  the cbnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it. < > < > cb0str fffffd03h, cb1str fffffd13h, cb2str fffffd23h caution in single transfer mode, writing to the cbntx register with the cbntsf bit set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcsirn signal, the written data is not transf erred because the cbntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications.
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 699 17.5 operation 17.5.1 single transfer mode (mast er mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /8 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no (1), (2), (3) (4) (5) (6) (8) no (7) intcsirn interrupt generated? transmission completed? end yes yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register c1h write cbntx register start transmission cbnctl0 00h remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 700 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) son pin intcsirn signal (1) write 00h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /8, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cbnctl0 register, and select t he transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writ ing the transmit data to the cbntx register, and transmission is started. (5) when transmission is started, out put the serial clock to the sckn pin, and output the transmit data from the son pin in synchronization with the serial clock. (6) when transmission of the transfer data length se t with the cbnctl2 register is completed, stop the serial clock output and transmit data output, generate the reception completion interrupt request signal (intcsirn) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue transmission, start the next transmission by writing the transmit dat a to the cbntx register again after the intcsirn signal is generated. (8) to end transmission, write the cbnctl0.cb npwr bit = 0 and the cbnctl0.cbntxe bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 701 17.5.2 single transfer mode (master mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /8 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no intcsirn interrupt generated? reception completed? end yes yes no (7) cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnctl0 register 00h read cbnrx register read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register a1h start reception (1), (2), (3) (4) (5) (6) (8) (9) (10) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 702 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sin pin sin pin capture timing intcsirn signal (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /8, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cbnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by per forming a dummy read of the cbnrx register, and reception is started. (5) when reception is started, out put the serial clock to the sckn pi n, and capture the receive data of the sin pin in synchronization with the serial clock. (6) when reception of the transfer data length set with the cbnctl2 regist er is completed, stop the serial clock output and data capturing, generate the re ception completion interrupt request signal (intcsirn) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue reception, read the cbnrx register with the cbnctl0.cbnsce bit = 1 remained after the intcsirn signal is generated. (8) to read the cbnrx register without starting the next reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) to end reception, write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 703 17.5.3 single transfer mode (master mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /8 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (7), (9) (5) (5) (6) (10) no (8) transmission/reception completed? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e1h write cbntx register read cbnrx register start transmission/reception cbnctl0 00h no intcsirn interrupt generated? yes no yes sckn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 704 (2) operation timing sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sin pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 son pin sin pin capture timing intcsirn signal (1) write 00h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = f xx /8, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cbnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writ ing the transmit data to the cbntx register, and transmission/reception is started. (5) when transmission/reception is st arted, output the serial clock to the sckn pin, output the transmit data to the son pin in synchronization with the serial clock, and capture the rece ive data of the sin pin. (6) when transmission/reception of t he transfer data length set with the cbnctl2 register is completed, stop the serial clock output, transmit data outpu t, and data capturing, generate the reception completion interrupt request signal (intcsirn) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) read the cbnrx register. (8) to continue transmission/reception, write t he transmit data to the cbntx register again. (9) read the cbnrx register. (10) to end transmission/reception, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 705 17.5.4 single transfer mode (s lave mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start no (1), (2), (3) (4) (5) (4) (6) (8) no (7) intcsirn interrupt generated? transmission completed? end yes yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register c1h write cbntx register start transmission cbnctl0 00h no yes sckn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 706 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) son pin intcsirn signal (1) write 07h to the cbnctl1 register, and sele ct communication type 1, communication clock (f cclk ) = external clock (sckn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c1h to the cbnctl0 register, and select t he transmission mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a from the son pin in synchronization with the serial clock. (6) when transmission of the transfer data length se t with the cbnctl2 register is completed, stop the serial clock output and transmit data output, generate the reception completion interrupt request signal (intcsirn) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue transmission, write the transmit dat a to the cbntx register again after the intcsirn signal is generated, and wait for a serial clock input. (8) to end transmission, write the cbnctl0.cb npwr bit = 0 and the cbnctl0.cbntxe bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 707 17.5.5 single transfer mode (slave mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start reception completed? end yes no (7) cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnctl0 register 00h read cbnrx register read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register a1h start reception no intcsirn interrupt generated? yes no yes (1), (2), (3) (4) (5) (4) (6) (6) (8) (9) (10) sckn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 708 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (10) (8) (9) sin pin sin pin capture timing intcsirn signal (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a1h to the cbnctl0 register, and select t he reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by perf orming a dummy read of the cbnrx register, and the device waits for a serial clock input. (5) when a serial clock is input, capture the receive da ta of the sin pin in sync hronization with the serial clock. (6) when reception of the transfer data length set with the cbnctl2 regist er is completed, stop the serial clock output and data capturing, generate the re ception completion interrupt request signal (intcsirn) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) to continue reception, read the cbnrx register with the cbnctl0.cbnsce bit = 1 remained after the intcsirn signal is generated, and wait for a serial clock input. (8) to end reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) to end reception, write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 709 17.5.6 single transfer mode (slave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (7), (9) (5) (4) (6) (10) no (8) transmission/reception completed? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e1h write cbntx register read cbnrx register start transmission/reception cbnctl0 00h no intcsirn interrupt generated? yes no yes sckn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 710 (2) operation timing sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (8) (7) (10) (9) sin pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 son pin sin pin capture timing intcsirn signal (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e1h to the cbnctl0 register, and select the transmission/reception mode and msb first at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a to the son pin in synchr onization with the serial clock, and capture the rece ive data of the sin pin. (6) when transmission/reception of the transfer data length set with the cbnctl2 register is completed, stop the serial clock output, transmit data outpu t, and data capturing, generate the reception completion interrupt request signal (intcsirn) at the last edge of the serial clock, and clear the cbntsf bit to 0. (7) read the cbnrx register. (8) to continue transmission/reception, write the trans mit data to the cbntx regist er again, and wait for a serial clock input. (9) read the cbnrx register. (10) to end transmission/reception, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 711 17.5.7 continuous transfer mode (master mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /8 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4), (8) (5) (11) no (7) transmission completed? end yes cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register c3h write cbntx register start transmission cbnctl0 00h no (6), (9) intcsitn interrupt generated? yes no (10) yes cbntsf bit = 0? (cbnstr register) remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 712 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) son pin intcsitn signal intcsirn signal l bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /8, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cbnctl0 register, and select the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is se t to 1 by writing the transmit data to the cbntx register, and transmission is started. (5) when transmission is started, output the serial clock to the sckn pin, and output the transmit data from the son pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cbnt x register to the shift register is completed and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcsitn) is generated. (7) to continue transmission, write the transmit dat a to the cbntx register again after the intcsitn signal is generated. (8) when a new transmit data is written to the cbntx register before communicat ion completion, the next communication is started following communication completion. (9) the transfer of the transmit data from the cbntx register to the shift register is completed and the intcsitn signal is generated. to end continuous transmission with the current transmission, do not write to the cbntx register. (10) when the next transmit data is not written to t he cbntx register before tr ansfer completion, stop the serial clock output to the sckn pin after transf er completion, and clear the cbntsf bit to 0. (11) to release the transmission enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbntxe bit = 0 after che cking that the cbntsf bit = 0. caution in continuous transm ission mode, the reception completi on interrupt request signal (intcsirn) is not generated. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 713 17.5.8 continuous transfer mode (master mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /8 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000)
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 714 (1) operation flow start yes intcsirn interrupt generated? intcsiern interrupt generated? end no no yes cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnove bit = 0 (cbnstr) read cbnrx register is data being received last data? yes cbnsce bit = 0 (cbnctl0) read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register a3h start reception (1), (2), (3) (4) (5) (6) (8) (9) (12) (13) (13) no read cbnrx register (9) (7) read cbnrx register no yes cbnctl0 register 00h no yes cbntsf bit = 0? (cbnstr) (9) (10) (11) (8) intcsirn interrupt generated? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in ( 2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 715 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckn pin cbntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (13) (10) sin pin intcsirn signal cbnsce bit son pin l sin pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /8, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cbnctl0 register, and select t he reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by per forming a dummy read of the cbnrx register, and reception is started. (5) when reception is started, output the serial clock to the sckn pin, and capture the receive data of the sin pin in synchronization with the serial clock. (6) when reception is completed, the reception co mpletion interrupt request signal (intcsirn) is generated, and reading of the cbnrx register is enabled. (7) when the cbnctl0.cbnsce bit = 1 upon communication completion, the next communication is started following communication completion. (8) to end continuous reception with the curr ent reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) when reception is completed, the intcsirn signal is generated, and reading of the cbnrx register is enabled. when the cbnsce bit = 0 is set before communication completion, stop the serial clock output to the sckn pin, and clear the cbntsf bit to 0, to end the receive operation. (11) read the cbnrx register. (12) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (13) to release the reception enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0 after che cking that the cbntsf bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 716 17.5.9 continuous transfer mode (mast er mode, transmissi on/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = f xx /8 (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 000), transfer data length = 8 bits (cbnctl2.cbncl3 to cbnctl2.cbncl0 bits = 0000)
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 717 (1) operation flow start end yes no is receive data last data? yes (12) no write cbntx register cbnove bit = 0 (cbnstr) read cbnrx register read cbnrx register cbnctl1 register 00h cbnctl2 register 00h cbnctl0 register e3h yes no (1), (2), (3) (4) (5) (7) (11) (9) (7) (6), (11) (8) (13) (13) (14) (15) (15) (10) no yes intcsitn interrupt generated? no yes cbntsf bit = 0? (cbnstr) write cbntx register yes no is data being transmitted last data? start transmission/reception cbnctl0 register 00h intcsiern interrupt generated? intcsirn interrupt generated? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 718 (2) operation timing (1/2) sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (15) (12) sin pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 son pin intcsitn signal intcsirn signal sin pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 00h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = f xx /8, and master mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cbnctl0 register, and select the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is se t to 1 by writing the transmit data to the cbntx register, and transmission/reception is started. (5) when transmission/reception is st arted, output the serial clock to the sckn pin, output the transmit data to the son pin in synchronization with the seri al clock, and capture the receive data of the sin pin. (6) when transfer of the transmit data from the cbntx register to the shift register is completed and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcsitn) is generated. (7) to continue transmission/reception, write the tr ansmit data to the cbntx register again after the intcsitn signal is generated. (8) when one transmission/reception is completed, the reception completion interrupt request signal (intcsirn) is generated, and reading of the cbnrx register is enabled. (9) when a new transmit data is written to the cbntx register before communicat ion completion, the next communication is started following communication completion. (10) read the cbnrx register. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 719 (2/2) (11) the transfer of the transmit data from the cbntx register to the shift register is completed and the intcsitn signal is generated. to end cont inuous transmission/reception with the current transmission/reception, do not wr ite to the cbntx register. (12) when the next transmit data is not written to t he cbntx register before tr ansfer completion, stop the serial clock output to the sckn pin after transf er completion, and clear the cbntsf bit to 0. (13) when the reception error interrupt request signal (intcsiern) is generated, read the cbnrx register. (14) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (15) to release the transmission/reception enable status, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bi t = 0 after checking that the cbntsf bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 720 17.5.10 continuous transfer mode (slave mode, transmission mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000) (1) operation flow start (1), (2), (3) (4) (4) (5), (8) (11) no (7) transmission completed? end yes cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register c3h write cbntx register start transmission cbnctl0 00h no (10) yes cbntsf bit = 0? (cbnstr register) no (6), (9) intcsitn interrupt generated? yes no (9) yes sckn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 721 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (11) (10) son pin intcsitn signal bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write c3h to the cbnctl0 register, and select the transmission mode, msb first, and continuous transfer mode at the same time as enablin g the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmi t data from the son pin in synchronization with the serial clock. (6) when transfer of the transmit data from the cbnt x register to the shift register is completed and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcsitn) is generated. (7) to continue transmission, write the transmit dat a to the cbntx register again after the intcsitn signal is generated. (8) when a serial clock is input following completion of the transmission of the transfer data length set with the cbnctl2 register, continu ous transmission is started. (9) when transfer of the transmit data from the cbnt x register to the shift register is completed and writing to the cbntx register is enabled, the intcsitn signal is generated. to end continuous transmission with the current transmission, do not write to the cbntx register. (10) when the clock of the transfer dat a length set with the cbnctl2 register is input without writing to the cbntx register, clear the cbntsf bit to 0 to end transmission. (11) to release the transmission enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbntxe bit = 0 after che cking that the cbntsf bit = 0. caution in continuous transmis sion mode, the reception completi on interrupt request signal (intcsirn) is not generated. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 722 17.5.11 continuous transfer m ode (slave mode, reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000)
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 723 (1) operation flow start yes intcsirn interrupt generated? intcsiern interrupt generated? end no no yes cbnrx register dummy read cbnsce bit = 0 (cbnctl0) cbnove bit = 0 (cbnstr) read cbnrx register is data being received last data? yes cbnsce bit = 0 (cbnctl0) read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register a3h reception start (1), (2), (3) (4) (5) (4) (6) (8) (9) (12) (13) (13) no read cbnrx register (9) (7) read cbnrx register no yes cbnctl0 register 00h intcsirn interrupt generated? (9) (10) (11) (8) no yes cbntsf bit = 0? (cbnstr) no yes sckn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 724 (2) operation timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sckn pin cbntsf bit (1) (2) (4) (3) (5) (6) (7) (8) (9) (11) (13) (10) sin pin intcsirn signal cbnsce bit sin pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write a3h to the cbnctl0 register, and select t he reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by perf orming a dummy read of the cbnrx register, and the device waits for a serial clock input. (5) when a serial clock is input, capture the receive da ta of the sin pin in sync hronization with the serial clock. (6) when reception is completed, the reception co mpletion interrupt request signal (intcsirn) is generated, and reading of the cbnrx register is enabled. (7) when a serial clock is input in the cbnctl0.cbns ce bit = 1 status, continuous reception is started. (8) to end continuous reception with the curr ent reception, write the cbnsce bit = 0. (9) read the cbnrx register. (10) when reception is completed, the intcsirn signal is generated, and reading of the cbnrx register is enabled. when the cbnsce bit = 0 is set before communication completion, clear the cbntsf bit to 0 to end the receive operation. (11) read the cbnrx register. (12) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (13) to release the reception enable status , write the cbnctl0.cbnpwr bit = 0 and the cbnctl0.cbnrxe bit = 0 after che cking that the cbntsf bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 725 17.5.12 continuous transfer mode (s lave mode, transmission/reception mode) msb first (cbnctl0.cbndir bit = 0), communication type 1 (cbnctl1.cbnckp and cbnctl1.cbndap bits = 00), communication clock (f cclk ) = external clock (sckn) (cbnctl1.cbncks2 to cbnctl1.cbncks0 bits = 111), transfer data length = 8 bits (cbnctl2. cbncl3 to cbnctl2.cbncl0 bits = 0000)
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 726 (1) operation flow start end yes no is receive data last data? yes no write cbntx register cbnove bit = 0 (cbnstr) read cbnrx register read cbnrx register cbnctl1 register 07h cbnctl2 register 00h cbnctl0 register e3h yes no (1), (2), (3) (4) (5) (7) (11) (9) (7) (8) (13) (12) (13) (14) (15) (15) (10) no yes cbntsf bit = 0? (cbnstr) write cbntx register yes no is data being transmitted last data? start transmission/reception cbnctl0 register 00h intcsiern interrupt generated? intcsirn interrupt generated? (6), (11) no yes intcsitn interrupt generated? (4) no yes sckn pin input started? remarks 1. the broken lines indicate the hardware processing. 2. the numbers in this figure correspond to the processing numbers in (2) operation timing . 3. n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 727 (2) operation timing (1/2) sckn pin cbntsf bit (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (13) (15) (12) sin pin bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 son pin intcsitn signal intcsirn signal sin pin capture timing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (1) write 07h to the cbnctl1 register, and select communication type 1, communication clock (f cclk ) = external clock (sckn), and slave mode. (2) write 00h to the cbnctl2 register, and set the transfer data length to 8 bits. (3) write e3h to the cbnctl0 register, and select the transmission/reception mode, msb first, and continuous transfer mode at the same time as enabling the operation of the communication clock (f cclk ). (4) the cbnstr.cbntsf bit is set to 1 by writing the transmit data to the cb ntx register, and the device waits for a serial clock input. (5) when a serial clock is input, output the transmit dat a to the son pin in synchr onization with the serial clock, and capture the rece ive data of the sin pin. (6) when transfer of the transmit data from the cbnt x register to the shift register is completed and writing to the cbntx register is enabled, the transmission enable interrupt request signal (intcsitn) is generated. (7) to continue transmission, write the transmit data to the cbntx r egister again after the intcsitn signal is generated. (8) when reception of the transfer dat a length set with the cbnctl2 regist er is completed, the reception completion interrupt request signal (intcsirn) is generated, and reading of the cbnrx register is enabled. (9) when a serial clock is input continuously, continuous transmission/re ception is started. (10) read the cbnrx register. (11) when transfer of the transmit data from the cbnt x register to the shift register is completed and writing to the cbntx register is enabled, the intcsitn signal is generated. to end continuous transmission/reception with the current transmission/re ception, do not write to the cbntx register. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 728 (2/2) (12) when the clock of the transfer data length set with the cbnc tl2 register is input without writing to the cbntx register, the intcsirn signal is gener ated. clear the cbntsf bit to 0 to end transmission/reception. (13) when the reception error interrupt request signal (intcsiern) is generated, read the cbnrx register. (14) if an overrun error occurs, write the cbns tr.cbnove bit = 0, and clear the error flag. (15) to release the transmission/reception enable status, write the cbnctl0.cbnpwr bit = 0, the cbnctl0.cbntxe bit = 0, and the cbnctl0.cbnrxe bi t = 0 after checking that the cbntsf bit = 0. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 729 17.5.13 reception error when transfer is performed with reception enabled (cbnctl0. cbnrxe bit = 1) in the continuous transfer mode, the reception error interrupt request signal (intcsiern) is generated when the next receive operation is completed before the cbnrx register is read after the reception comp letion interrupt request signal (intcsirn) is generated, and the overrun error flag (cbnstr.cbnove) is set to 1. even if an overrun error has occurred, the previous receive data is lost since the cbnrx register is updated. even if a reception error has occurred, the intcsiern signal is generated again upon the next reception completion if the cbnrx register is not read. to avoid an overrun error, complete reading the cbnrx r egister until one half clock before sampling the last bit of the next receive data from the intcsirn signal generation. (1) operation timing sckn pin cbnrx register read signal (1) (2) (4) 01h 02h 05h 0ah 15h 2ah 55h aah 00h 01h 02h 05h 0ah 15h 2ah 55h shift register aah 55h cbnrx register sin pin intcsirn signal intcsiern signal cbnove bit sin pin capture timing (3) (1) start continuous transfer. (2) completion of the first transfer (3) the cbnrx register cannot be read until one hal f clock before the completion of the second transfer. (4) an overrun error occurs, and the reception erro r interrupt request signal (intcsiern) is generated. the receive data is overwritten. remark n = 0, 1
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 730 17.5.14 clock timing (1/2) (i) communication type 1 ( cbnckp and cbndap bits = 00) d6 d5 d4 d3 d2 d1 sckn pin sin capture reg-r/w son pin intcsitn interrupt note 1 intcsirn interrupt note 2 cbntsf bit d0 d7 (ii) communication type 3 (cbnckp and cbndap bits = 10) d6 d5 d4 d3 d2 d1 d0 d7 sckn pin sin capture reg-r/w son pin intcsitn interrupt note 1 intcsirn interrupt note 2 cbntsf bit notes 1. the intcsitn interrupt is set w hen the data written to the cbntx register is transferred to the data shift register in the continuous transmission or continuous transmission/reception mode. in the single transmission or single transmission/receptio n mode, the intcsitn interrupt request signal is not generated, but the intcsirn interrupt request signal is generated upon end of communication. 2. the intcsirn interrupt occurs if reception is correctly ended and receive data is ready in the cbnrx register while reception is enabled. in the single mode, the intcsirn interrupt request signal is generated even in the transmission mode, upon end of communication. caution in single transfer mode, writing to the cbntx register with the cbntsf bit set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcsirn signal, the written data is not transf erred because the cbntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications.
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 731 (2/2) (iii) communication type 2 (cbnckp and cbndap bits = 01) d6 d5 d4 d3 d2 d1 d0 d7 sckn pin sin capture reg-r/w son pin intcsitn interrupt note 1 intcsirn interrupt note 2 cbntsf bit (iv) communication type 4 (cbnckp and cbndap bits = 11) d6 d5 d4 d3 d2 d1 d0 d7 sckn pin sin capture reg-r/w son pin intcsitn interrupt note 1 intcsirn interrupt note 2 cbntsf bit notes 1. the intcsitn interrupt is set w hen the data written to the cbntx register is transferred to the data shift register in the continuous transmission or continuous transmission/reception modes. in the single transmission or single transmission/receptio n modes, the intcsitn interrupt request signal is not generated, but the intcsirn interrupt request signal is generated upon end of communication. 2. the intcsirn interrupt occurs if reception is correctly ended and receive data is ready in the cbnrx register while reception is enabled. in the single mode, the intcsirn interrupt request signal is generated even in the transmission mode, upon end of communication. caution in single transfer mode, writing to the cbntx register with the cbntsf bi t set to 1 is ignored. this has no influence on the operation during transfer. for example, if the next data is written to the cbntx register when dma is started by generating the intcsirn signal, the written data is not transf erred because the cbntsf bit is set to 1. use the continuous transfer mode, not the si ngle transfer mode, for such applications.
chapter 17 clocked serial interface b (csib) user?s manual u16397ej3v0ud 732 17.6 output pins (1) sckn pin when csibn operation is disabled (cbnctl0.cbnpwr bit = 0), the sckn pin output status is as follows. cbnckp cbncks2 cbncks1 cbncks0 sckn pin output 1 1 1 high impedance 0 other than above fixed to high level 1 1 1 high impedance 1 other than above fixed to low level remark the output level of the sckn pin changes if any of the cb nctl1.cbnckp and cbncks2 to cbncks0 bits is rewritten. (2) son pin when csibn operation is disabled (cbnpwr bit = 0) , the son pin output status is as follows. cbntxe cbndap cbndir son pin output 0 fixed to low level 0 son latch value (low level) 0 cbntx0 value (msb) 1 1 1 cbntx0 value (lsb) remarks 1. the son pin output chan ges when any one of the cbnctl0.cbntxe, cbnctl0.cbndir bits, and cbnctl1.cbndap bit is rewritten. 2. : don?t care
user?s manual u16397ej3v0ud 733 chapter 18 i 2 c bus to use the i 2 c bus function, set the p33/sda and p34/scl pi ns to the sda and scl pins. then dummy open drain output (p-ch side is always off) is automatically set. in the v850e/ma3, one channel of i 2 c bus is provided. the products with an on-chip i 2 c bus are shown below. pd703131ay, 703132ay, 703133ay, 703134ay, 703136ay, 70f3134ay
chapter 18 i 2 c bus 734 user?s manual u16397ej3v0ud 18.1 uarta3/i 2 c mode switching in the v850e/ma3, uarta3 and i 2 c function alternately, and these pins cannot be used at the same time. to switch between uarta3 and i 2 c, the pmc3, pfc4, and pfce3 regi sters must be set in advance. caution the operations re lated to transmission and reception of uarta3/i 2 c are not guaranteed if the mode is switched during transmission or reception. be sure to disable the unit that is not used. figure 18-1. uarta3/i 2 c mode switch settings pmc3 after reset: 00h r/w address: fffff446h pmc37 0 0 pmc34 pmc33 pmc32 pmc31 pmc30 0 1 2 3 4 5 6 7 pfc3 after reset: 00h r/w address: fffff466h 0 0 0 pfc34 pfc33 pfc32 pfc31 pfc30 0 1 2 3 4 5 6 7 pfce3 after reset: 00h r/w address: fffff706h 0 0 0 pfce34 pfce33 pfce32 pfce31 pfce30 0 1 2 3 4 5 6 7 i/o port rxd3 input scl note i/o pmc34 0 1 1 specification of alternate function of p34 pin pfce34 0 1 pfc34 1 0 i/o port txd3 output sda note i/o pmc33 0 1 1 specification of alternate function of p33 pin pfce33 0 1 pfc33 1 0 note i 2 c bus versions (y products) only when using the sda and scl pins, the pins functi on as dummy open-drain output pins (p-ch side is always off). rema r k x = don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 735 18.2 features the i 2 c has the following two modes.  operation stop mode  i 2 c (inter ic) bus mode (multimaster supported) (1) operation stop mode this mode is used when serial transfers are not per formed. it can therefor e be used to reduce power consumption. (2) i 2 c bus mode (multi master supported) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock (scl) line and a serial data bus (sda) line. this mode complies with the i 2 c bus format and the master device can generate ?start condition?, ?address?, ?transfer direction specification?, ? data?, and ?stop condition? data to the sl ave device, via the serial data bus. the slave device automatica lly detects these received statuses and data by hardwar e. this function can simplify the part of application program that controls the i 2 c bus. since the scl and sda pins are used for dummy open drain outputs (p-ch side is always off), i 2 c requires pull-up resistors for the serial clock line and the serial data bus line. the scl and sd a pins withstand 3.3 v. for details, see chapter 26 electrical specifications .
chapter 18 i 2 c bus 736 user?s manual u16397ej3v0ud figure 18-2. i 2 c block diagram cld dad smc dfc cl0 internal bus iic status register (iics) iic control register (iicc) slave address register (sva) noise eliminator noise eliminator bus status detector match signal iic shift register (iic) so latch iice dq set clear iiccl. cl0 bit iics. trc bit iiccl. dfc bit iiccl.dfc bit sda note scl note pseudo open-drain output pseudo open-drain output data retention time correction circuit start condition generator stop condition generator ack generator wakeup controller ack detector output control stop condition detector serial clock counter interrupt request signal generator serial clock controller serial clock wait controller prescaler intiic iic shift register (iic) iicc.stt, iicc.spt bits iics.msts, iics.exc, iics.coi bits iics.msts, iics.exc, iics.coi bits lrel wrel spie wtim acke stt spt msts ald exc coi trc ackd std spd start condition detector internal bus clx iic clock select register (iiccl) stcf iicbsy stcen iicrsv iic flag register (iicf) iic function expansion register (iicx) prescaler compare register (prscm) prescaler mode register (prsm) prescaler f xx /2 f xx /4 to f xx /24 prscm2 prscm1 prscm0 brgce note the scl and sda pins of i 2 c are dummy open-drain output pins (p-c h side is always off). therefore, a pull-up resistor is necessary for the serial clo ck line and serial data bus line. in addition, the scl and sda pins withstand 3.3 v. for details, see chapter 26 electrical specifications .
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 737 a serial bus configuration example is shown below. figure 18-3. serial bus configuration example using i 2 c bus sda scl sda +ev dd +ev dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
chapter 18 i 2 c bus 738 user?s manual u16397ej3v0ud 18.3 configuration i 2 c includes the following hardware. table 18-1. configuration of i 2 c item configuration registers iic shift register (iic) slave address register (sva) control registers iic control register (iicc) iic status register (iics) iic flag register (iiccf) iic clock selection register (iiccl) iic function expansion register (iicx) prescaler mode register (prsm) prescaler compare register (prscm) (1) iic shift register (iic) the iic register is used to convert 8-bit serial data to 8-bit parallel data and to convert 8-bit parallel data to 8-bit serial data. the iic register can be used for both transmission and reception. write and read operations to the iic r egister are used to control the act ual transmit and receive operations. the iic register can be read or written in 8-bit units. after reset, iic is cleared to 00h. (2) slave address register (sva) the sva register sets local addresses when in slave mode. the sva register can be read or written in 8-bit units. after reset, sva0 and sva1 are cleared to 00h. (3) so latch the so latch is used to retain the sda pin?s output level. (4) wakeup controller this circuit generates an interrupt request signal (intiic ) when the address received by this register matches the address value set to the sva register or when an extension code is received. (5) prescaler this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks t hat are input during transmit/receive operations and is used to verify that 8-bit data was sent or received.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 739 (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiic). an i 2 c interrupt is generated followi ng either of two triggers. ? falling of the eighth or ninth clock of t he serial clock (set by iicc.wtim bit) ? interrupt request generated when a stop conditi on is detected (set by iicc.spie bit) (8) serial clock controller in master mode, this circuit generates the clo ck output via the scl pin from a sampling clock. (9) serial clock wait controller this circuit controls the wait timing. (10) ack generator, stop condition detector, start condition detector, and ack detector these circuits are used to gener ate and detect various statuses. (11) data hold time correction circuit this circuit generates the hold time for data corre sponding to the falling edge of the serial clock. (12) start condition generator this circuit generates a start condition when the iicc.stt bit is set. however, in the communication reservation disabled status (iicf.iicrsv bit = 1), when the bus is not released (iicf.iicbsy bit = 1), start condition requests are ignored and the iicf.stcf bit is set to 1. (13) stop condition generator a stop condition is generated w hen the iicc.spt bit is set. (14) bus status detector this circuit detects whether or not the bus is rel eased by detecting start conditions and stop conditions. however, as the bus status cannot be detected immediatel y following operation, the init ial status is set by the iicf.stcen bit.
chapter 18 i 2 c bus 740 user?s manual u16397ej3v0ud 18.4 registers i 2 c is controlled by the following registers.  iic control register (iicc)  iic status register (iics)  iic flag register (iicf)  iic clock selection register (iiccl)  iic function expansion register (iicx)  prescaler mode register (prsm)  prescaler compare register (prscm) the following registers are also used.  iic shift register (iic)  slave address register (sva) remark for the alternate-function pin settings, see table 4-19 using alternate function of port pins . (1) iic control register (iicc) the iicc register is used to enable/stop i 2 c operations, set wait timing, and set other i 2 c operations. the iicc register can be read or writt en in 8-bit or 1-bit units. however, set the spie, wtim, and acke bits when the iice bit is 0 or during the wait period. when setti ng the iice bit from ?0? to ?1?, these bits can also be set at the same time. reset input clears this register.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 741 (1/4) after reset: 00h r/w address: fffffd82h <7> <6> <5> <4> <3> <2> <1> <0> iicc iice lrel wrel spie wtim acke stt spt iice i 2 c operation enable/dis able specification 0 stop operation. reset the iics register note 1 . stop internal operation. 1 enable operation. be sure to set this register when the scl and sda lines are high level. condition for clearing (iice bit = 0) condition for setting (iice bit = 1) ? cleared by instruction ? reset ? set by instruction lrel note 2 exit from communications 0 normal operation 1 this exits from the current communications and sets standby mode. this setting is automatically cleared to 0 after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl and sda lines are set to high impedance. the stt, spt, iics.msts, iics.exc, iics.coi, iics.trc, iics.ackd, and iics.std bits are cleared to 0. the standby mode following exit from communications remains in effect until the following communications entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code rec eption occurs after the start condition. condition for clearing (lrel bit = 0) condition for setting (lrel bit = 1) ? automatically cleared after execution ? reset ? set by instruction wrel note wait cancellation control 0 do not cancel wait 1 cancel wait. this setting is automatica lly cleared to 0 after wait is canceled. condition for clearing (wrel bit = 0) condition for setting (wrel bit = 1) ? automatically cleared after execution ? reset ? set by instruction notes 1. the iics register, and the iicf.stcf, iicf.iic bsy, iiccl.cld, and iiccl.dad bits are reset. 2. this flag?s signal is invalid when the iice bit = 0. caution if the i 2 c operation is enabled (iice bit = 1) when th e scl line is high level and the sda line is low level, the start condition is detect ed immediately. after enabling i 2 c operation (iice bit = 1), set the lrel bit to 1 with a bit manipulation instruction after the wait time shown in table 18-2.
chapter 18 i 2 c bus 742 user?s manual u16397ej3v0ud (2/4) spie note enable/disable generation of interrupt request when stop condition is detected 0 disable 1 enable condition for clearing (spie bit = 0) condition for setting (spie bit = 1) ? cleared by instruction ? reset ? set by instruction wtim note control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock?s falling edge. master mode: after output of eight clocks, clock output is set to low level and wait is set. slave mode: after input of eight clocks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock?s falling edge. master mode: after output of nine clocks, clock output is set to low level and wait is set. slave mode: after input of nine clocks, the clock is set to low level and wait is set for master device. an interrupt is generated at the falling of the 9th clock during address transfer independently of the setting of this bit. the setting of this bit is valid when the address transfer is co mpleted. when in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after ack is issued. however, when t he slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtim bit = 0) condition for setting (wtim bit = 1) ? cleared by instruction ? reset ? set by instruction acke note acknowledgment control 0 disable acknowledgment. 1 enable acknowledgment. during t he ninth clock period, the sda line is set to low level. the acke bit setting is invalid for address reception by t he slave device. in this case, ack is generated when the addresses match. however, the acke bit setting is valid for reception of the extension code. set the acke bit in the system that receives the extension code. condition for clearing (acke bit = 0) condition for setting (acke bit = 1) ? cleared by instruction ? reset ? set by instruction note this flag?s signal is invalid when the iice bit = 0.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 743 (3/4) stt start condition trigger 0 do not generate a start condition. 1 when bus is released (in stop mode): generate a start condition (for starting as master). the sda line is changed from high level to low level while the scl line is high level and then the start condi tion is generated. next, after the rated amount of time has elapsed, the scl line is c hanged to low level (in wait state). when a third party is communicating ? when communication reservation functi on is enabled (iicf.iicrsv bit = 0) functions as the start condition reservation flag. when set to 1, automatically generates a start condition after the bus is released. ? when communication reservation functi on is disabled (iicrsv bit = 1) the iicf.stcf bit is set to 1 to clear the stt bit which is set to 1. in the wait state (when master device): generates a restart condition after releasing the wait. cautions concerning set timing for master reception: cannot be set to 1 during transfe r. can be set to 1 only when the acke bit has been cleared to 0 and slave has been notified of final reception. for master transmission: a start condition cannot be generat ed normally during the acknowledgment. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the spt bit. ? when the stt bit is set to 1, setting the stt bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (stt bit = 0) condition for setting (stt bit = 1) ? when the stt bit is set to 1 in the communication reservation disabled status ? cleared by loss in arbitration ? cleared because start conditi on is generated by master device ? when the lrel bit = 1 (exit from communications) ? when the iice bit = 0 (operation stop) ? reset ? set by instruction remark the stt bit is 0 if it is read after data setting.
chapter 18 i 2 c bus 744 user?s manual u16397ej3v0ud (4/4) spt stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (terminati on of master device?s transfer). after the sda line goes to low level, either set the scl line to high level or wait until the scl pin goes to high level. next, after the rated amount of time has elapsed, t he sda line is changed from low level to high level and a stop condition is generated. cautions concerning setting timing for master reception: cannot be set to 1 during transfer. can be set to 1 only when the acke bit has been cleared to 0 and during the wait period after slave has been notified of final reception. for master transmission: a stop condition cannot be generated normally during the acknowledgment period. set to 1 during the wait period that follows output of the ninth clock. ? cannot be set to 1 at the same time as the stt bit. ? the spt bit can be set to 1 only when in master mode note . ? when the wtim bit has been cleared to 0, if the spt bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated dur ing the high-level period of the ninth clock. the wtim bit should be set from 0 to 1 during the wait period following output of eight clocks, and the spt bit should be set to 1 during the wait period that follows output of the ninth clock. ? when the spt bit is set to 1, setting the spt bit to 1 again is disabled until the setting is cleared to 0. condition for clearing (spt bit = 0) condition for setting (spt bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lrel bit = 1 (exit from communications) ? when the iice bit = 0 (operation stop) ? reset ? set by instruction note set the spt bit to 1 only in master mode. howe ver, the spt bit must be set to 1 and a stop condition generated before the first stop conditi on is detected following the switch to operation enable status. for details, see 18.15 cautions . caution when the iics.trc bit is set to 1, the wrel bit is set to 1 during the ninth clock and wait is canceled, after which the trc bit is cleared to 0 and the sda lin e is set to high impedance. remark the spt bit is 0 if it is read after data setting.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 745 make sure by using software that the wait time shown in table 18-2 elapses. the wait time can be set by using the iiccl.smc and iiccl.cl0 bits, iicx.clx bit, and prscm.pr scm2 to prscm.prscm0 bits in combination. table 18-2. wait periods iicx iiccl bit 0 bit 3 bit 0 clx smc cl0 prscm register division clock wait period 0 0 0 01h f xx /4 12 clocks 0 0 0 02h f xx /8 24 clocks 0 0 0 03h f xx /12 36 clocks 0 0 0 04h f xx /16 48 clocks 0 0 0 05h f xx /20 60 clocks 0 0 0 06h f xx /24 72 clocks 0 0 1 01h f xx /4 12 clocks 0 0 1 02h f xx /8 24 clocks 0 0 1 03h f xx /12 36 clocks 0 0 1 04h f xx /16 48 clocks 0 1 x 01h f xx /4 12 clocks 0 1 x 02h f xx /8 24 clocks 0 1 x 03h f xx /12 36 clocks 0 1 x 04h f xx /16 48 clocks 0 1 x 05h f xx /20 60 clocks 1 1 x 01h f xx /4 12 clocks 1 1 x 02h f xx /8 24 clocks 1 1 x 03h f xx /12 36 clocks 1 1 x 04h f xx /16 48 clocks 1 1 x 05h f xx /20 60 clocks other than above setting prohibited remark don?t care
chapter 18 i 2 c bus 746 user?s manual u16397ej3v0ud (2) iic status register (iics) the iics register indicate s the status of the i 2 c bus. the iics register is read-only, in 8-bit or 1-bit units . however, the iics register can be read only when the iicc.stt bit is 1 or during the wait period. after reset, iics is cleared to 00h. (1/3) after reset: 00h r address: fffffd86h <7> <6> <5> <4> <3> <2> <1> <0> iics msts ald exc coi trc ackd std spd msts master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (msts bit = 0) condition for setting (msts bit = 1) ? when a stop condition is detected ? when the ald bit = 1 (arbitration loss) ? cleared by the iicc.lrel bit = 1 (exit from communications) ? when the iicc.iice bit changes from 1 to 0 (operation stop) ? reset ? when a start condition is generated ald detection of arbitration loss 0 this status means either that there was no arbitr ation or that the arbitration result was a ?win?. 1 this status indicates the arbitration result was a ?loss?. the msts bit is cleared to 0. condition for clearing (ald bit = 0) condition for setting (ald bit = 1) ? automatically cleared after the iics register is read note ? when the iice bit changes from 1 to 0 (operation stop) ? reset ? when the arbitration result is a ?loss?. exc detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (exc bit = 0) condition for setting (exc bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lrel bit = 1 (exit from communications) ? when the iice bit changes from 1 to 0 (operation stop) ? reset ? when the higher four bits of the received address data is either ?0000? or ?1111? (s et at the rising edge of the eighth clock). note this bit is also cleared when a bit manipulation instruction is executed for another bit in the iics register.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 747 (2/3) coi detection of matching addresses 0 addresses do not match. 1 addresses match. condition for clearing (coi bit = 0) condition for setting (coi bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lrel bit = 1 (exit from communications) ? when the iice bit changes from 1 to 0 ? reset ? when the received address matches the local address (sva register) (set at the rising edge of the eighth clock). trc detection of transmit/receive status 0 receive status (other than transmit status ). the sda line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sd a line (valid starting at the rising edge of the first byte?s ninth clock). condition for clearing (trc bit = 0) condition for setting (trc bit = 1) ? when a stop condition is detected ? cleared by the lrel bit = 1 (exit from communications) ? when the iice bit changes from 1 to 0 (operation stop) ? cleared by the iicc.wrel bit = 1 note (wait release) ? when the ald bit changes from 0 to 1 (arbitration loss) ? reset master ? when ?1? is output to the first byte?s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated ? when ?0? is output to the first byte?s lsb (transfer direction specification bit) slave ? when ?1? is input in the first byte?s lsb (transfer direction specification bit) ackd detection of ack 0 acknowledgment was not detected. 1 acknowledgment was detected. condition for clearing (ackd bit = 0) condition for setting (ackd bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock ? cleared by the lrel bit = 1 (exit from communications) ? when the iice bit changes from 1 to 0 (operation stop) ? reset ? after the sda pin is set to low level at the rising edge of the scl pin?s ninth clock note the iics.trc bit is cleared to 0 and the sda line become high impedance when the iicc.wrel bit is set to 1 and wait state is released at the ninth clock with the trc bit = 1.
chapter 18 i 2 c bus 748 user?s manual u16397ej3v0ud (3/3) std detection of start condition 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (std bit = 0) condition for setting (std bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte?s first clock following address transfer ? cleared by the lrel bit = 1 (exit from communications) ? when the iice bit changes from 1 to 0 (operation stop) ? reset when a start condition is detected spd detection of stop condition 0 stop condition was not detected. 1 stop condition was detected. the master device?s communication is terminated and the bus is released. condition for clearing (spd bit = 0) condition for setting (spd bit = 1) ? at the rising edge of the address transfer byte?s first clock following setting of this bit and detection of a start condition ? when the iice bit changes from 1 to 0 (operation stop) ? reset when a stop condition is detected
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 749 (3) iic flag register (iicf) iicf is register that se ts the operation mode of i 2 c and indicate the status of the i 2 c bus. these registers can be read or written in 8-bit or 1-bit units. howe ver, the stcf and iicbsy bits are read-only. the iicrsv bit can be used to enable/disable the communication reservation function (see 18.14 communication reservation ). the stcen bit can be used to set the initial value of the iicbsy bit (see 18.15 cautions ). the iicrsv and stcen bits can be wr itten only when the operation of i 2 c is disabled (iicc.iice bit = 0). when operation is enabled, the iicf register can be read. after reset, iicf is cleared to 00h.
chapter 18 i 2 c bus 750 user?s manual u16397ej3v0ud <7> stcf condition for clearing (stcf bit = 0)  clearing by setting the iicc.stt bit = 1  when the iice bit = 0  reset condition for setting (stcf bit = 1)  generating start condition unsuccessful and the stt bit cleared to 0 when communication reservation is disabled (iicrsv bit = 1). stcf 0 1 generate start condition start condition generation unsuccessful: clear stt flag iicc.stt clear flag iicf <6> iicbsy 5 0 4 0 3 0 2 0 <1> stcen <0> iicrsv after reset: 00h r/w note address: fffffd8ah condition for clearing (iicbsy bit = 0)  detection of stop condition  when the iice bit = 0  reset condition for setting (iicbsy bit = 1)  detection of start condition  setting of the iicc.iice bit when the stcen bit = 0 iicbsy 0 1 bus release status (default communication status when stcen bit = 1) bus communication status (default communication status when stcen bit = 0) i 2 c bus status flag condition for clearing (stcen bit = 0)  detection of start condition  reset condition for setting (stcen bit = 1)  setting by instruction stcen 0 1 after operation is enabled (iice bit = 1), enable generation of a start condition upon detection of a stop condition. after operation is enabled (iice bit = 1), enable generation of a start condition without detecting a stop condition. initial start enable trigger condition for clearing (iicrsv bit = 0)  clearing by instruction  reset condition for setting (iicrsv bit = 1)  setting by instruction iicrsv 0 1 enable communication reservation disable communication reservation communication reservation function disable bit note bits 6 and 7 are read-only bits. cautions 1. write to the stcen bit only wh en the operation is stopped (iice bit = 0). 2. as the bus release status (iicbsy bit = 0) is recognized regardless of the actual bus status when the stcen bit = 1, when gene rating the first start condition (stt bit = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. write to the iicrsv bit only when the operation is stopped (iice bit = 0).
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 751 (4) iic clock selection register (iiccl) the iiccl register is used to set the transfer clock for the i 2 c bus. the iiccl register can be read or writt en in 8-bit or 1-bit units. however, the cld and dad bits are read-only. the smc and cl0 bits are set using the iicx.clx bit in combination with the prscm.prscm2 to prscm.prscm0 bits (see 18.4 (8) i 2 c transfer clock setting method ). set the iiccl register when the iicc.iice bit = 0. reset input clears this register to 00h. after reset: 00h r/w note address: fffffd84h 7 6 <5> <4> 3 2 1 0 iiccl 0 0 cld dad smc dfc 0 cl0 cld detection of scl pin level (valid only when iicc.iice bit = 1) 0 the scl pin was detected at low level. 1 the scl pin was detected at high level. condition for clearing (cld bit = 0) condition for setting (cld bit = 1) ? when the scl pin is at low level ? when the iice bit = 0 (operation stop) ? reset ? when the scl pin is at high level dad detection of sda pin level (valid only when iice bit = 1) 0 the sda pin was detected at low level. 1 the sda pin was detected at high level. condition for clearing (dad bit = 0) condition for setting (dad bit = 1) ? when the sda pin is at low level ? when iice bit = 0 (operation stop) ? reset ? when the sda pin is at high level smc operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfc digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of dfc bit set/clear. the digital filter is used for noi se elimination in high-speed mode. note bits 4 and 5 are read-only bits. caution be sure to clear bits 1, 6, and 7 to ?0?.
chapter 18 i 2 c bus 752 user?s manual u16397ej3v0ud (5) iic function expansion register (iicx) these registers set the function expansion of i 2 c (valid only in high-speed mode). these registers can be read or written in 8-bit or 1-bit units. the clx bit is set by using prscm.prscm2 to prscm.prscm0 bits in combination wit h the iiccl.smc and iiccl.cl0 bits (see 18.4 (8) i 2 c transfer clock setting method ). set the iicx register when the iicc.iice bit = 0. reset input clears this register to 00h. after reset: 00h r/w address: fffffd85h 7 6 5 4 3 2 1 <0> iicx 0 0 0 0 0 0 0 clx (6) prescaler mode register (prsm) the prsm register controls the gener ation of the baud rate signal for i 2 c. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 7 0 prsm 6 0 5 0 <4> brgce 3 0 2 0 1 0 0 0 fixed to 0 operates brgce 0 1 baud rate output after reset: 00h r/w address: fffffd90h caution be sure to clear bits 0 to 3 and 5 to 7 to ?0?.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 753 (7) prescaler compare register (prscm) the prscm register controls the i 2 c division clock. this register can be read or written in 8-bit units. the prscm2 to prscm0 bits are set by using the iiccl.smc and iiccl.cl0 bits in comb ination with the iicx.clx bit (see 18.4 (8) i 2 c transfer clock setting method ). set the prscm register when the iicc.iice bit = 0. reset input clears this register to 00h. 7 0 prscm 6 0 5 0 4 0 3 0 2 prscm2 1 prscm1 0 prscm0 after reset: 00h r/w address: fffffd91h cautions 1. do not rewrite the pr scm register during transmission. 2. set the prscm register before setting the prsm.brgce bit to 1. 3. be sure to clear bits 3 to 7 to ?0?. (8) i 2 c transfer clock setting method the i 2 c transfer clock frequency (f scl ) is calculated using the following expression. f scl = 1/(m t + t r + t f ) m = 48, 96, 144, 176, 192, 240, 288, 344, 352, 384, 480, 528, 688, 704, 880, 1,032, 1,056, 1,376 (see table 18-3 selection clock setting ) t: 1/f xx t r : scl rise time t f : scl fall time for example, the i 2 c transfer clock frequency (f scl ) when f xx = 80 mhz, m = 880, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(880 12.5 ns + 200 ns + 50 ns) ? 88.9 khz m t + t r + t f m/2 t m/2 t t f t r scl scl inversion scl inversion scl inversion the selection clock is set using a combination of the iiccl.smc and iiccl.cl0 bits, the iicx.clx bit, and the prscm.prscm2 to pr scm.prscm0 bits.
chapter 18 i 2 c bus 754 user?s manual u16397ej3v0ud table 18-3. selection clock setting iicx iiccl bit 0 bit 3 bit 0 clx smc cl0 prscm register division clock transfer clock (f xx /m) settable peripheral clock frequency (f xx ) range operation mode 0 0 0 01h f xx /4 f xx /176 10.00 to 16.76 mhz 0 0 0 02h f xx /8 f xx /352 20.00 to 33.52 mhz 0 0 0 03h f xx /12 f xx /528 24.00 to 50.28 mhz 0 0 0 04h f xx /16 f xx /704 32.00 to 67.04 mhz 0 0 0 05h f xx /20 f xx /880 40.00 to 80.00 mhz 0 0 0 06h f xx /24 f xx /1,056 48.00 to 80.00 mhz 0 0 1 01h f xx /4 f xx /344 16.76 to 33.52 mhz 0 0 1 02h f xx /8 f xx /688 33.52 to 67.04 mhz 0 0 1 03h f xx /12 f xx /1,032 50.28 to 80.00 mhz 0 0 1 04h f xx /16 f xx /1,376 67.04 to 80.00 mhz normal mode (smc bit = 0) 0 1 x 01h f xx /4 f xx /96 16.00 to 33.52 mhz 0 1 x 02h f xx /8 f xx /192 32.00 to 67.04 mhz 0 1 x 03h f xx /12 f xx /288 48.00 to 80.00 mhz 0 1 x 04h f xx /16 f xx /384 64.00 to 80.00 mhz 0 1 x 05h f xx /20 f xx /480 80.00 to 80.00 mhz 1 1 x 01h f xx /4 f xx /48 16.00 to 16.76 mhz 1 1 x 02h f xx /8 f xx /96 32.00 to 33.52 mhz 1 1 x 03h f xx /12 f xx /144 48.00 to 50.28 mhz 1 1 x 04h f xx /16 f xx /192 64.00 to 67.04 mhz 1 1 x 05h f xx /20 f xx /240 80.00 to 80.00 mhz high-speed mode (smc bit = 1) other than above setting prohibited remark x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 755 (9) iic shift register (iic) the iic register is used for serial transmission/reception (shift operations) t hat is synchronized with the serial clock. the iic register can be read or writt en in 8-bit units, but data should not be written to the iic register during a data transfer. access (read/write) the iic register only during the wait period. accessi ng this register in communication states other than the wa it period is prohibited. howe ver, for the master device, t he iic register can be written once only after the transmission trigger bit (iicc.stt bit) has been set to 1. when the iic register is written during wait, the wait is cancelled and dat a transfer is started. reset input clears this register to 00h. after reset: 00h r/w address: fffffd80h 7 6 5 4 3 2 1 0 iic (10) slave address register (sva) the sva register holds the i 2 c bus?s slave addresses. however, rewrit ing this register is prohibited when the iics.std bit = 1 (start condition detection). the sva register can be read or written in 8- bit units, but bit 0 should be fixed as 0. after reset, sva is cleared to 00h. after reset: 00h r/w address: fffffd83h 7 6 5 4 3 2 1 0 sva 0
chapter 18 i 2 c bus 756 user?s manual u16397ej3v0ud 18.5 functions 18.5.1 pin configuration the serial clock pin (scl) and serial data bus pin (sda) are configured as follows. scl .................this pin is used for serial clock input and output. this pin is a dummy open-drain output (p-ch side is always off) for both master and slave devices. input is schmitt input. sda ................this pi n is used for serial data input and output. this pin is a dummy open-drain output (p-ch side is always off) for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are dummy open-drai n outputs, an external pull- up resistor is required. figure 18-4. pin configuration diagram ev dd scl sda scl sda ev dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 757 18.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus?s serial data communication fo rmat and the statuses generated by the i 2 c bus. the transfer timing for the ?start condition?, ?addre ss?, ?transfer direction spec ification?, ?data?, and ?stop condition? generated via the i 2 c bus?s serial data bus is shown below. figure 18-5. i 2 c bus?s serial data transfer timing 1 to 7 8 9 1 to 8 9 1 to 8 9 scl sda start condition address r/w ack data data stop condition ack ack the master device generates the start condition, slave address, and stop condition. the ack can be generated by ei ther the master or slave device (norma lly, it is generated by the device that receives 8-bit data). the serial clock (scl) is continuously output by the master devic e. however, in the sl ave device, the scl?s low- level period can be extended and a wait can be inserted. 18.6.1 start condition a start condition is met when the scl pin is at high level and the sda pin changes from high level to low level. the start conditions for the scl pin and sda pin are signals t hat the master device generates to the slave device when starting a serial transfer. start conditions c an be detected when the devic e is used as a slave. figure 18-6. start conditions h scl sda a start condition is generated when the ii cc.stt bit is set to 1 after a stop condition has been detected (iics.spd bit = 1). when a start condition is det ected, iics.std bit is set to 1. caution when the iicc.iice bit of the v850e/ma3 is set to 1 during communicati on between other devices, a start condition may be detected depending on the communication line state. be sure to set the iice bit to 1 when the scl and sda lines are high level.
chapter 18 i 2 c bus 758 user?s manual u16397ej3v0ud 18.6.2 addresses the 7 bits of data that follow the st art condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of t he slave devices that are connected to the master device via bus lines. t herefore, each slave devic e connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and che cks whether or not the 7-bit address data matches the data value stored in t he sva register. if the address data matches the sva register value, the slave device is selected and communicates with the master device until t he master device generates a start condition or stop condition. figure 18-7. address address scl 1 sda intiic note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (intiic ) is generated if a local address or extension code is received during slave device operation. the slave address and the eighth bit, which specif ies the transfer direction as described in 18.6.3 transfer direction specification below, are together written to the iic regi ster and are then output. received addresses are written to the iic register. the slave address is assigned to the hi gher 7 bits of the iic register.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 759 18.6.3 transfer dir ection specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfe r direction. when this transfer direction specification bit has a value of 0, it indicates that the mast er device is transmitting data to a slave device. when the transfer direction specif ication bit has a value of 1, it indica tes that the master device is receiving data from a slave device. figure 18-8. transfer direction specification scl 1 sda intiic 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the interrupt request signal (int iic) is generated if a local address or extension code is received during slave device operation.
chapter 18 i 2 c bus 760 user?s manual u16397ej3v0ud 18.6.4 ack ack is used to confirm the serial data stat us of the transmitting and receiving devices. the receiving device returns ack for every 8 bits of data it receives. the transmitting device normally receives ack after transmi tting 8 bits of data. when ack is returned from the receiving device, the reception is judged as normal and proc essing continues. the detecti on of ack is confirmed with the iics.ackd bit. when the master device is the receiving device, after re ceiving the final data, it does not return ack and generates the stop condition. when the slave device is the receiv ing device and does not return ack, the master device generates either a stop condition or a rest art condition, and then stops the current transmission. failure to return ack may be caused by the following factors. <1> reception was not performed normally. <2> the final data was received. <3> the receiving device does not exist for the specified address. when the receiving device sets the sda line to low level during the ninth clock, ack is generated (normal reception). when the iicc.acke bit is set to 1, automatic ack generat ion is enabled. transmission of the eighth bit following the 7 address data bits causes the iics.trc bit to be set. normally, set the acke bit to 1 for reception (trc bit = 0). when the slave device is receiving (when trc bit = 0), if the slave device cannot receive data, clear the acke bit to 0 to indicate to the master that no more data can be received. similarly, when the master device is receiving (when trc bit = 0) and the subsequent data is not needed, clear the acke bit to 0 to prevent ack from being generated. this not ifies the slave device (trans mitting device) of the end of the data transmission (transmission stopped). figure 18-9. ack scl 1 sda 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack when the local address is received, ack is automatically generated regardless of the value of the acke bit. no ack is generated if the received address is not a local address (nack). when receiving the extension code, set the acke bit to 1 in advance to generate ack. the ack generation method during data rec eption is based on the wait timing setti ng, as described by the following. ? when 8-clock wait is selected (iicc.wtim bit = 0): ack is generated at the falling edge of the scl pin?s eighth clock if the ac ke bit is set to 1 before the wait ? when 9-clock wait is selected (wtimn bit = 1): ack is generated if the acke bit is set to 1 in advance.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 761 18.6.5 stop condition when the scl pin is at high level, changing the sda pin from low level to high level generates a stop condition. a stop condition is generated when serial transfer from the master device to the slave device has been completed. stop conditions can be detected when the device is used as a slave. figure 18-10. stop condition h scl sda a stop condition is generated when the iicc. spt bit is set to 1. when the st op condition is detected, the iics.spd bit is set to 1 and the interrupt request signal (int iic) is generated when the iicc.spie bit is set to 1.
chapter 18 i 2 c bus 762 user?s manual u16397ej3v0ud 18.6.6 wait the wait is used to notify t he communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl pin to low level notifies the communication partner of the wait status. when wait status has been canceled for both the master and slave dev ices, the next data transfer can begin. figure 18-11. wait (1/2) (a) when master device has a nine-clock wa it and slave device has an eight-clock wait (master: transmission, slave: r eception, and iicc.acke bit = 1) scl 6 sda 78 9 123 scl iic 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iic scl acke master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iic data write (cancel wait) slave wait after output of eighth clock. ffh is written to iic register or iicc.wrel bit is set to 1. transfer lines wait from slave wait from master
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 763 figure 18-11. wait (2/2) (b) when master and slave d evices both have a nine-clock wait (master: transmission, slave: reception, and acke bit = 1) scl 6 sda 789 123 scl iic 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iic scl acke master master and slave both wait after output of ninth clock. iic data write (cancel wait) slave ffh is written to iic register or wrel bit is set to 1. generated according to previously set acke bit value transfer lines wait from master and slave wait from slave a wait state may be automatically set after a start condition is generated. al so, a wait state may be automatically set depending on the setting of the iicc.wtim bit. normally, when the wrel bit is set to 1 or when ffh is wri tten to the iic register, the wait status is canceled and the transmitting side writes data to the iic register to cancel the wait status. the master device can also c ancel the wait status via ei ther of the following methods.  by setting the iicc.stt bit to 1  by setting the iicc.spt bit to 1
chapter 18 i 2 c bus 764 user?s manual u16397ej3v0ud 18.6.7 wait state cancellation method in the case of i 2 c, wait state can be canceled normally in the following ways. ? by writing data to the iic register ? by setting the iicc.wrel bit to 1 (wait state cancellation) ? by setting the iicc.stt bit to 1 (start condition generation) note ? by setting the iicc.spt bit to 1 (stop condition generation) note note master only if any of these wait state canc ellation actions is performed, i 2 c will cancel wait state and restart communication. when canceling wait state and s ending data (including address), writ e data to the iic register. to receive data after canceling wait state, or to complete data transmission, set the wrel bit to 1. to generate a restart condition after canceli ng wait state, set the stt bit to 1. to generate a stop condition after canceling wait state, set the spt bit to 1. execute cancellation only once for each wait state. for example, if data is written to t he iic register following wait state canc ellation by setting the wrel bit to 1, conflict between the sda line change timing and iic register write timing may result in the data output to the sda line may be incorrect. even in other operations, if communication is st opped halfway, clearing the iicc.iice bit to 0 will stop communication, enabling wait state to be cancelled. if the i 2 c bus dead-locks due to noise, etc., setting the iicc.lrel bit to 1 causes the communication operation to be exited, enabling wait state to be cancelled.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 765 18.7 i 2 c interrupt request signals (intiic) the following shows the value of the iic s register at the intiic interrupt request signal generation timing and at the intiic signal timing. 18.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when iicc.wtim bit = 0 iicc.spt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 1000x110b 2: iics register = 1000x000b 3: iics register = 1000x000b (wtim bit = 1 note ) 4: iics register = 1000xx00b ? 5: iics register = 00000001b note to generate a stop condition, set the wtim bi t to 1 and change the timi ng of generation of the interrupt request signal (intiic). remark : always generated ? : generated only when iicc.spie bit = 1 x: don?t care <2> when wtim bit = 1 spt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 1000x110b 2: iics register = 1000x100b 3: iics register = 1000xx00b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus 766 user?s manual u16397ej3v0ud (2) start ~ address ~ data ~ star t ~ address ~ data ~ stop (restart) <1> when wtim bit = 0 iicc.stt bit = 1 spt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 5 6 ? 7 1: iics register = 1000x110b 2: iics register = 1000x000b (wtim bit = 1 note 1 ) 3: iics register = 1000xx00b (wtim bit = 0 note 2 ) 4: iics register = 1000x110b 5: iics register = 1000x000b (wtim bit = 1 note 3 ) 6: iics register = 1000xx00b ? 7: iics register = 00000001b notes 1 . set the wtim bit to 1 to generate a star t condition and change the timing of generation of the interrupt request signal (intiic). 2. clear the wtim bit to 0 to restore the original setting. 3. to generate a stop condition, set the wtim bit to 1 and change the timing of generation of the interrupt request signal (intiic). remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 stt bit = 1 spt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 1000x110b 2: iics register = 1000xx00b 3: iics register = 1000x110b 4: iics register = 1000xx00b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 767 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtim bit = 0 spt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 1010x110b 2: iics register = 1010x000b 3: iics register = 1010x000b (wtim bit = 1 note ) 4: iics register = 1010xx00b ? 5: iics register = 00000001b note to generate a stop condition, set the wtim bi t to 1 and change the timi ng of generation of the interrupt request signal (intiic). remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 spt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 1010x110b 2: iics register = 1010x100b 3: iics register = 1010xx00b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus 768 user?s manual u16397ej3v0ud 18.7.2 slave device operation (when recei ving slave address (match with address)) (1) start ~ address ~ data ~ data ~ stop <1> when iicc.wtim bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0001x110b 2: iics register = 0001x000b 3: iics register = 0001x000b ? 4: iics register = 00000001b remark : always generated ? : generated only when iicc.spie bit = 1 x: don?t care <2> when wtim bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0001x110b 2: iics register = 0001x100b 3: iics register = 0001xx00b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 769 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim bit = 0 (after restart, match with address) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 0001x110b 2: iics register = 0001x000b 3: iics register = 0001x110b 4: iics register = 0001x000b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 (after restart, match with address) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 0001x110b 2: iics register = 0001xx00b 3: iics register = 0001x110b 4: iics register = 0001xx00b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus 770 user?s manual u16397ej3v0ud (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtim bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 0001x110b 2: iics register = 0001x000b 3: iics register = 0010x010b 4: iics register = 0010x000b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 5 ? 6 1: iics register = 0001x110b 2: iics register = 0001xx00b 3: iics register = 0010x010b 4: iics register = 0010x110b 5: iics register = 0010xx00b ? 6: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 771 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtim bit = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0001x110b 2: iics register = 0001x000b 3: iics register = 00000110b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0001x110b 2: iics register = 0001xx00b 3: iics register = 00000110b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus 772 user?s manual u16397ej3v0ud 18.7.3 slave device operation (w hen receiving extension code) if an expansion code is received, the device always takes part in communication. (1) start ~ code ~ data ~ data ~ stop <1> when iicc.wtim bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0010x010b 2: iics register = 0010x000b 3: iics register = 0010x000b ? 4: iics register = 00000001b remark : always generated ? : generated only when iicc.spie bit = 1 x: don?t care <2> when wtim bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 0010x010b 2: iics register = 0010x110b 3: iics register = 0010x100b 4: iics register = 0010xx00b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 773 (2) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim bit = 0 (after restart, match with address) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 0010x010b 2: iics register = 0010x000b 3: iics register = 0001x110b 4: iics register = 0001x000b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 (after restart, match with address) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 5 ? 6 1: iics register = 0010x010b 2: iics register = 0010x110b 3: iics register = 0010xx00b 4: iics register = 0001x110b 5: iics register = 0001xx00b ? 6: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus 774 user?s manual u16397ej3v0ud (3) start ~ code ~ data ~ st art ~ code ~ data ~ stop <1> when wtim bit = 0 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 0010x010b 2: iics register = 0010x000b 3: iics register = 0010x010b 4: iics register = 0010x000b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 (after restart, extension code reception) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 5 6 ? 7 1: iics register = 0010x010b 2: iics register = 0010x110b 3: iics register = 0010xx00b 4: iics register = 0010x010b 5: iics register = 0010x110b 6: iics register = 0010xx00b ? 7: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 775 (4) start ~ code ~ data ~ st art ~ address ~ data ~ stop <1> when wtim bit = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0010x010b 2: iics register = 0010x000b 3: iics register = 00000110b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 r/w ack d7 to d0 ack st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 0010x010b 2: iics register = 0010x110b 3: iics register = 0010xx00b 4: iics register = 00000110b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus 776 user?s manual u16397ej3v0ud 18.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp ? 1 ? 1: iics register = 00000001b remark ? : generated only when iicc.spie bit = 1 18.7.5 arbitration loss operation (opera tion as slave after arbitration loss) when using the device as the master in a multimaster system, read to iics.msts bit to check the result of arbitration each time the intiic interrupt has been generated (1) when arbitration loss occurs duri ng transmission of slave address data <1> when iicc.wtim bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0101x110b 2: iics register = 0001x000b 3: iics register = 0001x000b ? 4: iics register = 00000001b remark : always generated ? : generated only when iicc.spie bit = 1 x: don?t care <2> when wtim bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0101x110b 2: iics register = 0001x100b 3: iics register = 0001xx00b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 777 (2) when arbitration loss occurs dur ing transmission of extension code <1> when wtim bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 0110x010b 2: iics register = 0010x000b 3: iics register = 0010x000b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 0110x010b 2: iics register = 0010x110b 3: iics register = 0010x100b 4: iics register = 0010xx00b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus 778 user?s manual u16397ej3v0ud 18.7.6 operation when arbitrat ion loss occurs (no communicat ion after arbitration loss) when using the device as the master in a multimaster system, read to iics.msts bit to check the result of arbitration each time the intiic interrupt has been generated (1) when arbitration loss occurs dur ing transmission of slave address data st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 ? 2 1: iics register = 01000110b ? 2: iics register = 00000001b remark : always generated ? : generated only when iicc.spie bit = 1 (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 ? 2 1: iics register = 0110x010b iicc.lrel bit is set to 1 by software ? 2: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 779 (3) when arbitration loss o ccurs during data transfer <1> when iicc.wtim bit = 0 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 ? 3 1: iics register = 10001110b 2: iics register = 01000000b ? 3: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 <2> when wtim bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack sp 1 2 ? 3 1: iics register = 10001110b 2: iics register = 01000100b ? 3: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1
chapter 18 i 2 c bus 780 user?s manual u16397ej3v0ud (4) when loss occurs due to rest art condition during data transfer <1> not extension code (example: mismatches with address) st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 ? 3 1: iics register = 1000x110b 2: iics register = 01000110b ? 3: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care dn = d6 to d0 <2> extension code st ad6 to ad0 r/w ack d7 to dn st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 ? 3 1: iics register = 1000x110b 2: iics register = 0110x010b lrel bit is set to 1 by software ? 3: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care dn = d6 to d0
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 781 (5) when loss occurs due to stop condition during data transfer st ad6 to ad0 r/w ack d7 to dn sp 1 ? 2 1: iics register = 1000x110b ? 2: iics register = 01000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care dn = d6 to d0
chapter 18 i 2 c bus 782 user?s manual u16397ej3v0ud (6) when arbitration loss occurs due to low-level da ta when attempting to gene rate a restart condition <1> when wtim bit = 0 iicc.stt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 1000x110b 2: iics register = 1000x000b (iicc.wtim bit = 1) 3: iics register = 1000xx00b (wtim bit = 0) 4: iics register = 01000000b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 stt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 1000x110b 2: iics register = 1000x100b 3: iics register = 01000100b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 783 (7) when arbitration loss occurs due to a stop conditi on when attempting to gene rate a restart condition <1> when wtim bit = 0 iicc.stt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 1000x110b 2: iics register = 1000x000b (iicc.wtim bit = 1) 3: iics register = 1000xx00b (wtim bit = 0) ? 4: iics register = 01000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 stt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack sp 1 2 ? 3 1: iics register = 1000x110b 2: iics register = 1000xx00b ? 3: iics register = 01000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus 784 user?s manual u16397ej3v0ud (8) when arbitration loss occurs due to low-level data when attemp ting to generate a stop condition <1> when wtim bit = 0 iicc.spt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp 1 2 3 4 ? 5 1: iics register = 1000x110b 2: iics register = 1000x000b (iicc.wtim bit = 1) 3: iics register = 1000x100b (wtim bit = 0) 4: iics register = 01000100b ? 5: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care <2> when wtim bit = 1 spt bit = 1 st ad6 to ad0 r/w ack d7 to d0 ack d7 to d0 ack d7 to d0 ack sp 1 2 3 ? 4 1: iics register = 1000x110b 2: iics register = 1000x100b 3: iics register = 01000100b ? 4: iics register = 00000001b remark : always generated ? : generated only when spie bit = 1 x: don?t care
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 785 18.8 interrupt request signal (intiic) generation timing and wait control the setting of the iicc.wtim bit determines the timing by which t he intiic signal is generated and the corresponding wait control, as shown below. table 18-4. intiic signal gene ration timing and wait control during slave device operation du ring master device operation wtim bit address data reception data transmission address data reception data transmission 0 9 notes 1, 2 8 note 2 8 note 2 9 8 8 1 9 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. the slave device?s intiic signal and wait period o ccurs at the falling edge of the ninth clock only when there is a match with the addr ess set to the sva register. at this point, ack is generated regardless of the va lue set to the iicc.acke bit. for a slave device that has received an extension code, the intiic signal occurs at the falling edge of the eighth clock. when the address does not match after restart, the intiic signal is generated at the falling edge of the ninth clock, but no wait occurs. 2. if the received address does not ma tch the contents of the sva regist er and extension codes have not been received, neither the intiic signal nor a wait occurs. remark the numbers in the table indicate the number of the serial clock?s cl ock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined depending on the conditions in notes 1 and 2 above regardless of the wtim bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtim bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtim bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtim bit.
chapter 18 i 2 c bus 786 user?s manual u16397ej3v0ud (4) wait cancellation method the four wait cancellation methods are as follows. ? by writing data to the iic register ? by setting the iicc.wrel bit (wait state cancellation) ? by setting the iicc.stt bit (start condition generation) ? by setting the iicc.spt bi t (stop condition generation) note master only when an 8-clock wait has been selected (wtimn bit = 0), whether or not ac k has been generated must be determined prior to wait cancellation. (5) stop condition detection the intiic signal is generated w hen a stop condition is detected. 18.9 address match detection method when in i 2 c bus mode, the master device c an select a particular slave device by transmitting the corresponding slave address. address match detection is performed autom atically by hardware. an intiic interrupt request signal occurs when a local address has been set to the sva register and when t he address set to the sva register matches the slave address sent by the master device, or when an extension code has been received. 18.10 error detection in i 2 c bus mode, the status of the serial data bus (sda) during data transmi ssion is captured by the iic register of the transmitting device, so the iic regi ster data prior to transmission can be co mpared with the transmitted iic register data to enable detection of transmission errors. a tr ansmission error is judged as having occurred when the compared data values do not match.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 787 18.11 extension code (1) when the higher 4 bits of the receive address are eit her 0000 or 1111, the extension code flag (exc) is set for extension code reception and an interrupt request signal (intiic) is issued at the falling edge of the eighth clock. the local address stored in t he sva register is not affected. (2) if 11110xx0 is set to the sva register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the int iic signal occurs at the falling edge of the eighth clock. ? higher 4 bits of data match: iics.exc bit = 1 ? 7 bits of data match: iics.coi bit = 1 (3) since the processing after the intiic signal occurs diffe rs according to the data that follows the extension code, such processing is performed by software. if an extension code is received dur ing slave operation, the device take s part in communication even if its address does not match. for example, when operation as a slav e is not desired after the extension c ode is received, set the iicc.lrel bit to 1. the cpu will enter the next communication wait state. table 18-5. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
chapter 18 i 2 c bus 788 user?s manual u16397ej3v0ud 18.12 arbitration when several master devices simult aneously generate a start condition (when t he iicc.stt bit is set to 1 before the iics.std bit is set to 1), communication among the ma ster devices is performed as the number of clocks is adjusted until the data differs. this ki nd of operation is called arbitration. when one of the master devices loses in ar bitration, an arbitration loss flag (iics. ald bit) is set (1) via the timing by which the arbitration loss occurred, and the scl and sda lines are both set fo r high impedance, which releases the bus. the arbitration loss is detec ted based on the timing of the next interrupt request signal (i ntiic) (the eighth or ninth clock, when a stop condition is detec ted, etc.) and the ald bit = 1 setti ng that has been made by software. for details of interrupt reques t signal generation timing, see 18.7 i 2 c interrupt request signals (intiic) . figure 18-12. arbitration timing example master 1 master 2 transfer lines scl sda scl sda scl sda master 1 loses arbitration hi-z hi-z
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 789 table 18-6. status during arbitration a nd interrupt request si gnal generation timing status during arbitration interr upt request signal generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack transfer period after data reception when restart condition is det ected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected duri ng data transfer when stop condition is generated (when iicc.spie bit = 1) note 2 when the sda pin is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to generate a restart condition when stop condition is generated (when spie bit = 1) note 2 when the sda pin is at low level while attempting to generate a stop condition when the scl pin is at low level while attempting to generate a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the iicc.wtim bit = 1, an in terrupt request signal occurs at t he falling edge of the ninth clock. when the wtim bit = 0 and the extension code?s slav e address is received, an interrupt request signal occurs at the falling edge of the eighth clock. 2. when there is a possibility that arbitration will occur, set the spie bi t = 1 for master device operation. 18.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request si gnal (intiic) when a local address or extension code has been received. this function makes processing more efficient by prev enting unnecessary interrupt request signals from occurring when addresses do not match. when a start condition is detected, wa keup standby mode is set. this wak eup standby mode is in effect while addresses are transmitted due to the possi bility that an arbitration loss may change the master device (which has generate a start condition) to a slave device. however, when a stop condition is detect ed, the iicc.spie bit is set regardle ss of the wake up function, and this determines whether interrupt reques t signals are enabled or disabled.
chapter 18 i 2 c bus 790 user?s manual u16397ej3v0ud 18.14 communication reservation 18.14.1 when communication reservation func tion is enabled (iicf.iicrsv bit = 0) to start master device communications when not current ly using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is re leased. there are two modes under which the bus is not used. ? when arbitration results in neit her master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iicc.lrel bit was set to ?1?). if the iicc.stt bit is set (1) while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). when the iicc.spie bit is set to 1 and an address is written to the iic register after rel ease of the bus is detected by generation of an interrupt request si gnal (intiic) (stop condition detection) , the device automatically starts communication as the master. data written to the iic register before the stop condi tion is detected is invalid. when the stt bit has been set (1), the operation mode (as start condition or as communication reservation) is determined according to the bus status. if the bus has been re leased ..............................................a start condition is generated if the bus has not been released (standby mode) ..............comm unication reservation to detect which operation mode has been det ermined for the stt bit, set the stt bi t (1), wait for the wait period, then check the iics.msts bit. wait periods, which should be set via software, are listed in table 18-7. these wait periods can be set via the settings for the iicx.clx, iiccl.smc, and iiccl.cl0 bits.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 791 table 18-7. wait periods clx bit smc bit cl0 bit prscm register division clock wait period 0 0 0 01h f xx/ 4 92 clocks 0 0 0 02h f xx /8 184 clocks 0 0 0 03h f xx /12 276 clocks 0 0 0 04h f xx /16 368 clocks 0 0 0 05h f xx /20 460 clocks 0 0 0 06h f xx /24 552 clocks 0 0 1 01h f xx /4 172 clocks 0 0 1 02h f xx /8 344 clocks 0 0 1 03h f xx /12 516 clocks 0 0 1 04h f xx /16 688 clocks 0 1 1/0 01h f xx /4 60 clocks 0 1 1/0 02h f xx /8 120 clocks 0 1 1/0 03h f xx /12 180 clocks 0 1 1/0 04h f xx /16 240 clocks 0 1 1/0 05h f xx /20 300 clocks 1 1 1/0 01h f xx /4 36 clocks 1 1 1/0 02h f xx /8 72 clocks 1 1 1/0 03h f xx /12 108 clocks 1 1 1/0 04h f xx /16 144 clocks 1 1 1/0 05h f xx /20 180 clocks the communication reservation timing is shown below.
chapter 18 i 2 c bus 792 user?s manual u16397ej3v0ud figure 18-13. communication reservation timing 2 1 3456 2 13456 789 scl sda program processing hardware processing write to iic set spd and intiic stt = 1 communication reservation set std generated by master with bus access iic: iic shift register stt: bit 1 of iic control register (iicc) std: bit 1 of iic status register (iics) spd: bit 0 of iic status register (iics) intiic: interrupt request signal communication reservations are accepted via the followi ng timing. after the iics.std bit is set to 1, a communication reservation can be made by setting the ii cc.stt bit to 1 before a st op condition is detected. figure 18-14. timing for accep ting communication reservations scl sda std spd standby mode
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 793 the communication reservation flowchart is illustrated below. figure 18-15. communication reservation flowchart di iicc.stt bit = 1 define communication reservation wait cancel communication reservation no yes iic register h ei iics.msts bit = 0? (communication reservation) note (generate start condition) ; sets stt bit (communication reservation). ; gets wait period set by software (see table 18-7 ). ; confirmation of communication reservation ; clear user flag. ; iic register write operation ; defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation oper ation executes a write to the iic register when a stop condition interrupt request occurs.
chapter 18 i 2 c bus 794 user?s manual u16397ej3v0ud 18.14.2 when communication reservation func tion is disabled (iicf.iicrsv bit = 1) when the iicc.stt bit is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. the followi ng two statuses are incl uded in the status where bus is not used. ? when arbitration results in nei ther master nor slave operation ? when an extension code is received and slave operation is disabled (ack is not returned and the bus was released when the iicc.lrel bit was set to 1) to confirm whether the start condition was generated or request was rejected, c heck the iicf.stcf flag. the wait time shown in table 18-8 is required until the stcf flag is set after setting the stt bit = 1. therefore, secure the time by software. table 18-8. wait periods cl0 bit prscm register di vision clock wait period 0 01h f xx/ 4 12 clocks 0 02h f xx /8 24 clocks 0 03h f xx /12 36 clocks 0 04h f xx /16 48 clocks 0 05h f xx /20 60 clocks 0 06h f xx /24 72 clocks 1 01h f xx /4 12 clocks 1 02h f xx /8 24 clocks 1 03h f xx /12 36 clocks 1 04h f xx /16 48 clocks
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 795 18.15 cautions (1) when iicf.stcen bit = 0 immediately after i 2 c operation is enabled, the bus communication st atus (iicf.iicbsy bit = 1) is recognized regardless of the actual bus status. to execute master communica tion in the status where a stop condition has not been detected, gener ate a stop condition and then release t he bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccl register. <2> set the iicc.iice bit. <3> set the iicc.spt bit. (2) when iicf.stcen bit = 1 immediately after i 2 c operation is enabled, the bus re leased status (iicbsy bit = 0) is recognized regardless of the actual bus status. to generate the first start condition (iicc.stt bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) when the iicc.iice bit of the v850e/ma3 is set to 1 while communications with other devices are in progress, the start condition may be detected dependi ng on the status of the communicati on line. be sure to set the iicc.iice bit to 1 when the scl and sda lines are high level. (4) determine the operation clock frequency by the ii ccl and iicx registers bef ore enabling the operation (iicc.iice bit = 1). to change the operation clo ck frequency, clear the iicc.iice bit to 0 once. (5) after the iicc.stt and iicc.spt bits have been set to 1, they must not be re-s et without being cleared to 0 first. (6) if transmission has been reserved, set the iicc.spie bit to 1 so that an interrupt request is generated by the detection of a stop condition. after an interrupt r equest has been generated, the wait state will be released by writing communication data to i 2 c, then transferring will begin. if an interrupt is not generated by the detection of a stop condition, transmission will halt in the wait st ate because an interrupt r equest was not generated. however, it is not necessary to set the spie bit to 1 for the software to detect the iics.msts bit.
chapter 18 i 2 c bus 796 user?s manual u16397ej3v0ud 18.16 communication operations the following shows three operati on procedures with the flowchart. (1) master operation in single master system the flowchart when using the v850e/ma3 as the ma ster in a single master system is shown below. this flowchart is broadly divided into the initial setti ngs and communication processi ng. execute the initial settings at startup. if communica tion with the slave is required, pr epare the communication and then execute communication processing. (2) master operation in multimaster system in the i 2 c bus multimaster system, whether the bus is released or used cannot be judged by the i 2 c bus specifications when the bus takes part in a communicati on. here, when data and clock are at a high level for a certain period (1 frame), the v850e/ma3 takes par t in a communication with bus released state. this flowchart is broadly divided into the initial setti ngs, communication waiting, and communication processing. the processing when the v850e/ma3 loos es in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. execute the initial setti ngs at startup to take part in a communication. then, wait for the co mmunication request as the master or wait for the spec ification as the slave. the actual communication is performed in the communication proce ssing, and it supports the transmission/reception with the slave and the arbitration wit h other masters. (3) slave operation an example of when the v850e/ma3 is used as the slave of the i 2 c bus is shown below. when used as the slave, operation is st arted by an interrupt. execute the in itial settings at st artup, then wait for the intiic interrupt occurrence (communication waiting). when the intiic interrupt occurs, the communication status is judged and its result is pa ssed as a flag over to the main processing. by checking the flags, necessary communication processing is performed.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 797 18.16.1 master operation in single master system figure 18-16. master operati on in single master system iicx register 0xh iiccl register xxh iicfregister 0xh set stcen bit, iicrsv bit = 0 iicc register xxh acke bit = wtim bit = spie bit = 1 iice bit = 1 set ports initialize i 2 c bus note iicc.spt bit = 1 svaregister xxh write iic register write iic register spt bit = 1 iicc.wrel bit = 1 start end read iic register acke bit = 0 wtim bit = wrel bit = 1 no no yes no no no yes yes yes yes iicf.stcen bit = 1? acke bit = 1 wtim bit = 0 intiic interrupt occurred? transfer completed? transfer completed? restarted? iics.trc bit = 1? iics.ackd bit = 1? ackd bit = 1? see table 4-19 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting communication start preparation (start condition generation) communication start (address, transfer direction specification) waiting for ack detection waiting for data transmission transmission start communication processing initial settings reception start waiting for data reception no yes intiic interrupt occurred? waiting for ack detection communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiic interrupt occurred? yes no intiic interrupt occurred? yes no yes no yes no intiic interrupt occurred? iicc.stt bit = 1 note release the i 2 c bus (scl, sda pins = high level) in conformi ty with the specificati ons of the product in communication. for example, when the eeprom outputs a low level to the sda pin, set the scl pin to the output port and output clock pulses from that output port until when the sda pi n is constantly high level. remark for the transmission and reception formats, confo rm to the specifications of the product in communication.
chapter 18 i 2 c bus 798 user?s manual u16397ej3v0ud 18.16.2 master operation in multimaster system figure 18-17. master operation in multimaster system (1/3) iicx register 0xh iiccl register xxh iicf register 0xh set stcen bit, iicrsv bit iicc register xxh acke bit = wtim bit = spie bit = 1 iice bit = 1 set ports iicc.spt bit = 1 sva bit xxh spie bit = 1 start slave operation slave operation bus release status for a certain period confirmation of bus status is in progress yes confirm bus status note master operation started? communication reservation enable communication reservation disable iics.spd bit = 1? iicf.stcen bit = 1? iicf.iicrsv bit = 0? a see table 4-19 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. transfer clock selection local address setting start condition setting (communication start request issued) (no communication start request) ? waiting for slave specification from another master ? waiting for communication start request (depending on user program) communication start preparation (stop condition generation) waiting for stop condition detection no yes yes no intiic interrupt occurred? intiic interrupt occurred? yes no yes no spd bit = 1? yes no slave operation no intiic interrupt occurred? yes no 1 b spie bit = 0 yes no waiting for communication request communication waiting initial settings note confirm that the bus release stat us (iiccl.cld bit = 1, iiccl.dad bit = 1) has been maintained for a certain period (1 frame, for example). when the sda pin is constantly low le vel, determine whether to release the i 2 c bus (scl, sda pins = high level) by referri ng to the specificati ons of the product in communication.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 799 figure 18-17. master operation in multimaster system (2/3) iicc.stt bit = 1 wait slave operation yes iics.msts bit = 1? iics.exc bit = 1 or coi bit =1? communication start preparation (start condition generation) securing wait time by software (see table 18-7 ) waiting for bus release (communication reserved) wait status after stop condition detection and start condition generation by communication reservation function no intiic interrupt occurred? yes yes no no a c stt bit = 1 wait slave operation yes iicf.iicbsy bit = 0? exc bit = 1 or coi bit =1? communication start preparation (start condition generation) communication reservation disabled communication reservation enabled securing wait time by software (see table 18-8 ) waiting for bus release stop condition detection no no intiic interrupt occurred? yes yes no yes iicf.stcf bit = 0? no b d c d communication processing communication processing
chapter 18 i 2 c bus 800 user?s manual u16397ej3v0ud figure 18-17. master operation in multimaster system (3/3) write iic register iicc.wtim bit = 1 iicc.wrel bit = 1 read iic register iicc.acke bit = 1 wtim bit = 0 wtim bit = wrel bit = 1 acke bit = 0 write iic register yes iics.trc bit = 1? restarted? iics.msts bit = 1? communication start (address, transfer direction specification) transmission start no yes waiting for data transmission reception start yes no intiic interrupt occurred? yes no transfer completed? waiting for ack detection yes no intiic interrupt occurred? waiting for data transmission not in communication yes no intiic interrupt occurred? no yes iics.ackd bit = 1? no yes no c 2 yes msts bit = 1? no yes transfer completed? no yes ackd bit = 1? no 2 yes msts bit = 1? no 2 waiting for ack detection yes no intiic interrupt occurred? yes msts bit = 1? no c 2 yes iics.exc bit = 1 or coi bit = 1? no 1 2 iicc.spt bit = 1 iicc.stt bit = 1 slave operation end communication processing communication processing remarks 1. conform the transmission and reception formats to the specifications of the product in communication. 2. when using the v850e/ma3 as the master in t he multimaster system, read the iics.msts bit for each intiic interrupt occurrence to confirm the arbitration result. 3. when using the v850e/ma3 as the slave in the multimaster system, confirm the status using the iics and iicf registers for each intiic interrupt occurrence to determine the next processing.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 801 18.16.3 slave operation the following shows the processing procedure of the slave operation. basically, the operation of the slave device is event-driven. therefore, processing by an intiic interrupt (processing requiring a significant change of the operat ion status, such as st op condition detection during communication) is necessary. the following description assumes that data communication does not support extension codes. also, it is assumed that the intiic interrupt servicing performs only status change processing and t hat the actual data communication is performed during the main processing. figure 18-18. software out line during slave operation i 2 c intiic setting, etc. setting, etc. flag data main processing interrupt servicing therefore, the following three flags are prepared so that the data transfer processing can be performed by transmitting these flags to the main pr ocessing instead of the intiic signal. (1) communication mode flag this flag indicates the following communication statuses. clear mode: data communication not in progress communication mode: data communication in progre ss (valid address detection stop condition detection, ack from master not detected, address mismatch) (2) ready flag this flag indicates that data communication is enabled. th is is the same status as an intiic interrupt during normal data transfer. this flag is set in the interr upt processing block and cleared in the main processing block. the ready flag for the first data for transmission is not set in the interrupt processing block, so the first data is transmitted without clearance processing (the address match is regarded as a request for the next data). (3) communication direction flag this flag indicates the direction of communication and is the same as the value of the iics.trc bit. the following shows the operati on of the main processing bl ock during slave operation. start i 2 c and wait for the communication enabled status. w hen communication is enabled, perform transfer using the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by interrupts, conditions are confirmed by flags). for transmission, repeat the transmission operation until the master device stops returning ack. when the master device stops returning acknowledge, transfer is complete.
chapter 18 i 2 c bus 802 user?s manual u16397ej3v0ud for reception, receive the required number of data and do not return ack for the next data immediately after transfer is complete. after that, the master device generates the stop condition or restart c ondition. this causes exit from communications. figure 18-19. slave operation flowchart (1) yes yes yes yes yes yes yes no no no no no no communication mode flag = 1? communication mode flag = 1? communication direction flag = 1? ready flag = 1? communication direction flag = 0? read iic register clear ready flag clear ready flag communication direction flag = 1? wrel bit = 1 iics.ackd bit = 1? clear communication mode flag iicc.wrel bit = 1 write iic register iicc register xxh acke bit = wtim bit = 1 spie bit = 0, iice bit = 1 sva register xxh local address setting iicx register 0xh iiccl register xxh set ports transfer clock selection iicf register 0xh set iicrsv bit start condition setting transmission start reception start no yes no communication mode flag = 1? yes no ready flag = 1? see table 4-19 settings when port pins are used for alternate functions to set the i 2 c mode before this function is used. start initial settings communication processing remark for the transmission and reception formats, confo rm to the specifications of the product in communication
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 803 the following shows an example of the pr ocessing of the slave device by an int iic interrupt (it is assumed that no extension codes are used here). during an intiic interr upt, the status is confirm ed and the following steps are executed. <1> when a stop condition is detect ed, communication is terminated. <2> when a start condition is detected, the address is confirmed. if the address does not match, communication is terminated. if the address matches, the communica tion mode is set and wait is released, and operation returns from the interrupt (the ready flag is cleared). <3> for data transmission/reception, w hen the ready flag is set, operation retu rns from the interrupt while the i 2 c bus remains in the wait status. remark <1> to <3> in the above correspond to <1> to <3> in figure 18-20 slave operation flowchart (2) . figure 18-20. slave operation flowchart (2) yes yes yes no no no intiic occurred set ready flag interrupt servicing completed iics.spd bit = 1? iics.std bit = 1? iics.coi bit = 1? clear communication direction flag, ready flag, and communication mode flag <1> <2> <3> communication direction flag iics.trc bit set communication mode flag clear ready flag
chapter 18 i 2 c bus 804 user?s manual u16397ej3v0ud 18.17 timing of data communication when using i 2 c bus mode, the master dev ice generates an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the iics.trc bit that specifies the data transfer direction and then starts serial co mmunication with the slave device. the iic register?s shift operation is synchronized with the falling edge of the se rial clock (scl pin). the transmit data is transferred to the so latch and is output (msb first) via the sda pin. data input via the sda pin is captured by the iic register at the ri sing edge of the scl pin. the data communication timing is shown below.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 805 figure 18-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iic register iics. ackd bit iics. std bit iics. spd bit iicc. wtim bit h h l l l l h h h l l iicc. acke bit iics. msts bit iicc. stt bit iicc. spt bit iicc. wrel bit intiic interrupt iics. trc bit iic register ackd bit std bit spd bit wtim bit acke bit msts bit stt bit spt bit wrel bit intiic interrupt trc bit scl pin sda pin processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iic register address iic register data iic register ffh transmit start condition receive (when iics.exc bit = 1) note note note to cancel slave wait, write ffh to t he iic register or set the iicc.wrel bit.
chapter 18 i 2 c bus 806 user?s manual u16397ej3v0ud figure 18-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iic register iics. ackd bit iics. std bit iics. spd bit iicc. wtim bit h h l l l l l l h h h h l l l l l iics. acke bit iics. msts bit iicc. stt bit iicc. spt bit iicc. wrelbit intiic interrupt iics. trc bit iic register ackd bit std bit spd bit wtim bit acke bit msts bit stt bit spt bit wrel bit intiic interrupt trc bit scl pin sda pin processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iic register data iic register ffh note iic register ffh note iic register data transmit receive note note ack ack note to cancel slave wait, write ffh to the iic register or set the wrel bit.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 807 figure 18-21. example of m aster to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iic register iics. ackd bit iics. std bit iics. spd bit iicc. wtim bit h h l l l l h h h l iicc. acke bit iics. msts bit iicc. stt bit iicc. spt bit iicc. wrel bit intiic interrupt iics. trc bit iic register ackd bit std bit spd bit wtim bit acke bit msts bit stt bit spt bit wrel bit intiic interrupt trc bit scl pin sda pin processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iic register data iic register address iic register ffh note iic register ffh note stop condition start condition transmit note note (when spie bit = 1) receive (when iicc.spie bit = 1) ack note to cancel slave wait, write ffh to the iic register or set the wrel bit.
chapter 18 i 2 c bus 808 user?s manual u16397ej3v0ud figure 18-22. example of sl ave to master communication (when 8-clock 9-clock (master)/9-clock (sl ave) wait is selected) (1/3) (a) start condition ~ address iic register iics. ackd bit iics. std bit iics. spd bit iicc. wtim bit h h l l l iicc. acke bit iicc. msts bit iicc. stt bit iicc. spt bit iicc. wrel bit intiic interrupt iics. trc bit iic register ackd bit std bit spd bit wtim bit acke bit msts bit stt bit spt bit wrel bit intiic interrupt trc bit scl pin sda pin processing by master device transfer lines processing by slave device 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iic register address iic register ffh note note iic register data stop condition start condition (when spie bit = 1) nack (when iicc.spie bit = 1) note to cancel master wait, write ffh to t he iic register or set the iicc.wrel bit.
chapter 18 i 2 c bus user?s manual u16397ej3v0ud 809 figure 18-22. example of sl ave to master communication (when 8-clock (master)/9-clock (s lave) wait is selected) (2/3) (b) data iic register iics. ackd bit iics. std bit iics. spd bit iicc. wtim bit h h h l l l l l l l h h l l l l l iicc. acke bit iics. msts bit iicc. stt bit iicc. spt bit iicc. wrel bit intiic interrupt iics. trc bit iic register ackd bit std bit spd bit wtim bit acke bit msts bit stt bit spt bit wrel bit intiic interrupt trc bit scl pin sda pin processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iic register data iic register data iic register ffh note iic register ffh note note to cancel master wait, write ffh to t he iic register or set the iicc.wrel bit.
chapter 18 i 2 c bus 810 user?s manual u16397ej3v0ud figure 18-22. example of sl ave to master communication (when 8-clock (master)/9-clock (s lave) wait is selected) (3/3) (c) stop condition iic register iics. ackd bit iics. std bit iics. spd bit iicc. wtim bit h h l l l iicc. acke bit iicc. msts bit iicc. stt bit iicc. spt bit iicc. wrel bit intiic interrupt iics. trc bit iic register ackd bit std bit spd bit wtim bit acke bit msts bit stt bit spt bit wrel bit intiic interrupt trc bit scl pin sda pin processing by master device transfer lines processing by slave device 12345678 9 1 d7 d6 d5 d4 d3 d2 d1 d0 ad6 iic register address iic register ffh note note iic register data stop condition start condition (when spie bit = 1) nack (when iicc.spie bit = 1) note to cancel master wait, write ffh to t he iic register or set the iicc.wrel bit.
user?s manual u16397ej3v0ud 811 chapter 19 dma functions (dma controller) the v850e/ma3 includes a direct memory access (dma) controller (dmac) that ex ecutes and controls dma transfer. the dmac controls data transfer between memory and i/ o, or among memories, based on requests by interrupts from on-chip peripheral i/o (serial inte rface, timer/counter, and a/d conver ter) or dma requests issued by the dmarq0 to dmarq3 pins or softwar e triggers (memory refers to inte rnal ram or external memory). 19.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? two types of transfer ? flyby (1-cycle) transfer (only in separate bus mode) ? 2-cycle transfer ? three transfer modes ? single transfer mode ? single-step transfer mode ? block transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (serial interface, timer/counter, a/d converter) ? requests via dmarq0 to dmarq3 pin input ? requests by software trigger ? transfer objects ? memory ? i/o ? memory ? memory ? dma transfer end output signals (tc0 to tc3) ? next address setting function
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 812 19.2 configuration tcn cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control block address control block count control block channel control block dmac v850e/ma3 bus interface external bus external ram external rom external i/o dma source address register (dsanh/dsanl) dma transfer count register (dbcn) dma channel control register (dchcn) dma terminal count output control register (dtoc) dma destination address register (ddanh/ddanl) dmarqn dmaakn dma addressing control register (dadcn) dma interface control register (difc) dma trigger factor register n (dtfrn) dmaak width control register (dakw) remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 813 19.3 control registers 19.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma transfer source address (28 bits) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. since these registers are configured as 2-stage fifo buffe r registers consisting of the master register and slave register, a new transfer source address for dma transfer can be specified during dma transfer (see 19.8 next address setting function ). when flyby transfer is specified with the dadcn.ttyp bit, the external memory addresses are set by the dsan register. at this time, the setting of the ddan register is ignored (n = 0 to 3). (1) dma source address registers 0h to 3h (dsa0h to dsa3h) the dsa0h to dsa3h registers can be read or written in 16-bit units. reset input makes these registers undefined. caution when setting an address of an on-chip peri pheral i/o register for the source address, be sure to specify an address between ffff000h a nd fffffffh. an address of the on-chip peripheral i/o register image (3fff000h to 3ffffffh) must not be specified. ir external memory, on-chip peripheral i/o internal ram ir 0 1 sa27 to sa16 dma transfer source specification dsanh (n = 0 to 3) 0 0 0 sa27 sa26 sa25 sa24 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah set the dma transfer source address (a27 to a16). during dma transfer, these bits store the next dma transfer source address. during flyby transfer, they store an external memory address. 15 14 13 12 11 10 9 8 sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 76 54 32 1 0 caution be sure to clear bits 14 to 12 to ?0?. if they are set to 1, the op eration is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 814 (2) dma source address registers 0l to 3l (dsa0l to dsa3l) the dsa0l to dsa3l registers can be read or written in 16-bit units. reset input makes these registers undefined. sa15 sa15 to sa0 dsanl (n = 0 to 3) sa14 sa13 sa12 sa11 sa10 sa9 sa8 after reset: undefined r/w address: dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h set the dma transfer source address (a15 to a0). during dma transfer, these bits store the next dma transfer source address. during flyby transfer, they store an external memory address. 15 14 13 12 11 10 9 8 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 76 54 32 1 0
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 815 19.3.2 dma destination address regi sters 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dma transfer destination address (28 bits) for dma channel n (n = 0 to 3). they are divided into two 16-bit registers, ddanh and ddanl. since these registers are configured as 2-stage fifo buffe r registers consisting of the master register and slave register, a new transfer destination address for dma transfer can be specified during dma transfer (see 19.8 next address setting function ). when flyby transfer is specified wit h the dadcn.ttyp bit, the setting of the ddan register is ignored. (1) dma destination address register s 0h to 3h (dda0h to dda3h) the dda0h to dda3h registers can be read or written in 16-bit units. reset input makes these registers undefined. caution when setting an address of an on-chip peripheral i/o register for the destination address, be sure to specify an address between ffff000h and fffffffh. an address of the on-chip peripheral i/o register image (3fff000h to 3ffffffh) must not be specified. ir external memory, on-chip peripheral i/o internal ram ir 0 1 da27 to da16 dma transfer destination specification ddanh (n = 0 to 3) 0 0 0 da27 da26 da25 da24 after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, dda2h fffff096h, dda3h fffff09eh set the dma transfer destination address (a27 to a16). during dma transfer, these bits store the next dma transfer destination address. this setting is ignored during flyby transfer. 15 14 13 12 11 10 9 8 da23 da22 da21 da20 da19 da18 da17 da16 76 54 32 1 0 caution be sure to clear bits 14 to 12 to ?0?. if they are set to 1, the op eration is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 816 (2) dma destination address regist ers 0l to 3l (dda0l to dda3l) the dda0l to dda3l registers can be read or written in 16-bit units. reset input makes these registers undefined. da15 da15 to da0 ddanl (n = 0 to 3) da14 da13 da12 da11 da10 da9 da8 after reset: undefined r/w address: dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch set the dma transfer destination address (a15 to a0). during dma transfer, these bits store the next dma transfer destination address. this setting is ignored during flyby transfer. 15 14 13 12 11 10 9 8 da7 da6 da5 da4 da3 da2 da1 da0 76 54 32 1 0
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 817 19.3.3 dma transfer count regi sters 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bit registers that set the byte transfer count for dma channel n (n = 0 to 3). these registers store the remaining transfer count during dma transfer. since these registers are configured as 2-stage fifo buffe r registers consisting of the master register and slave register, a new dma byte transfer count for dma transfer can be specified during dma transfer (see 19.8 next address setting function ). these registers are decremented by 1 for each tr ansfer, and transfer ends when a borrow occurs. these registers can be read or written in 16-bit units. reset input makes these registers undefined. remark if the dbcn register is read during dma transfer afte r a terminal count has occurred without the register being overwritten, the value set immediately before the dma transfer will be read out (0000h will not be read, even if dma transfer has ended). bc15 transfer count 1 or remaining transfer count transfer count 2 or remaining transfer count : transfer count 65,536 (2 16 ) or remaining transfer count bc15 to bc0 0000h 0001h : ffffh transfer count setting (store remaining transfer count during dma transfer) dbcn (n = 0 to 3) bc14 bc13 bc12 bc11 bc10 bc9 bc8 after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h 15 14 13 12 11 10 9 8 bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 76 54 32 1 0
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 818 19.3.4 dma addressing control regi sters 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-bit registers that control the dma transfer mode for dma channel n (n = 0 to 3). these registers cannot be accessed during dma operation. these registers can be read or written in 16-bit units. reset input clears these registers to 0000h. cautions 1. the ds1 and ds0 bits set how ma ny bits of data are to be transferred. when 8-bit data is set (ds1 and ds0 bits = 00), the lower bytes of the data bus (ad0 to ad7) are not always used. if the transfer data size is set to 16 bits, transfer is always started from an address with the lowest bit of the address aligned to ?0?. in th is case, transfer cannot be started from an odd address. 2. set the dadcn register when the target channels is in one of the following periods (the operation is not guaranteed if the regi ster is set at any other time). ? period from system reset to the generati on of the first dma transfer request ? period from completion of dma transfer (after terminal count) to the ge neration of the next dma transfer request ? period from forced termination of dma transfer (after the dchcn .initn bit was set to 1) to the generation of the next dma transfer request
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 819 ds1 8 bits 16 bits setting prohibited setting prohibited ds1 0 0 1 1 ds0 0 1 0 1 setting of transfer data size for dma transfer dadcn (n = 0 to 3) ds000 00 0 0 increment decrement fixed setting prohibited sad1 0 0 1 1 sad0 0 1 0 1 setting of count direction of transfer source address for dma channel n increment decrement fixed setting prohibited dad1 0 0 1 1 dad0 0 1 0 1 setting of count direction of transfer destination address for dma channel n single transfer mode single-step transfer mode setting prohibited block transfer mode tm1 0 0 1 1 tm0 0 1 0 1 setting of transfer mode during dma transfer after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h 15 14 13 12 11 10 9 8 sad1 sad0 dad1 dad0 tm1 tm0 ttyp tdir 76 54 32 1 0 2-cycle transfer flyby transfer ttyp 0 1 setting of dma transfer type memory i/o (read) i/o memory (write) tdir 0 1 setting of transfer direction during transfer between i/o and memory this setting is valid only during flyby transfer and ignored during 2-cycle transfer. caution be sure to clear bits 13 to 8 to ?0?. if they are set to 1, the operation is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 820 19.3.5 dma channel control regist ers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bit registers that co ntrol the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read or written in 8-bit or 1-bit un its. (however, bit 7 is read only and bits 2 and 1 are write only. if bits 2 and 1 are read, the read value is always 0.) reset input clears these registers to 00h. cautions 1. if transfer has been completed with the mlen bit set to 1 and if the next transfer request is made by dma transfer (hardware dma) that is started by dmarqn pin input or an interrupt from the on-chip peripheral i/o, the next transf er is executed with the tcn bit set to 1 (not automatically cleared to 0). 2. set the mlen bit when the target channel is in one of th e following periods (the operation is not guaranteed if the bit is set at any other time). ? period from system reset to the generati on of the first dma transfer request ? period from completion of dma transfer (after terminal count) to the ge neration of the next dma transfer request ? period from forced termination of dma transf er (after the initn bit of the dchcn register was set to 1) to the generation of the next dma transfer request 3. if dma transfer is forcibly terminated in the last transfer cycle with the mlen bit set to 1, the operation is performed in the same manner as when transfer is completed (the tcn bit is set to 1 and the tcn signal is output). (the enn bit is cleared to 0 upon forced termination, regardless of the value of the mlen bit.) in this case, the enn bit must be set to 1 and th e tcn bit must be read (cleared to 0) when the next dma transfer request is made. 4. upon completion of dma transfer (during terminal count), each bit is updated with the enn bit cleared to 0 and then the tc n bit set to 1. if the statuses of the tcn bit and enn bit are polled and if the dchcn register is read while each bit is updated, therefore, a value indicating the status ?transfer not completed and prohibited? (tcn bit = 0 and enn bit = 0) may be read (this is not abnormal). 5. the tcn bit does not have to be read (clear ed (0)) after dma transfer has been completed (after terminal count) only if both of the following c onditions are satisfied. if either of these conditions is not satisfied, be sure to read (clear (0)) the tcn bi t before the next dma transfer request is generated. ? the mlen bit is set (1) when dma tran sfer is completed (at terminal count). ? the next dma transfer start source is the dm arqn pin input or an interrupt request from the on-chip peripheral i/o (hardware dma). if the above two conditions are not satisfied, the operation cannot be guaranteed if the next dma transfer request is generate d when the tcn bit is set (1).
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 821 tcn dma transfer has not ended. dma transfer has ended. tcn note 1 0 1 mlen status bit that indicates whether dma transfer via dma channel n has ended or not dchcn (n = 0 to 3) 0 0 0 mlen initn stgn enn after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h when this bits is set (1) at dma transfer completion (at the terminal count output), the enn bit is not cleared (0) and the dma transfer enabled state is retained. if the next dma transfer start factor is the dmarqn pin input or the interrupt from an on-chip peripheral i/o (hardware dma), the dma transfer request is acknowledged even if the tcn bit is not read. if the next dma transfer start factor is input by setting the stgn bit to 1 (software dma), the dma transfer request is acknowledged if the tcn bit is read and cleared (0). when this bit is cleared (0) at dma transfer completion (at the terminal count output), the enn bit is cleared (0) and the dma transfer disabled state is entered. at the next dma transfer request, the tcn bit must be read and the enn bit must be set (1). initn note 2 if this bit is set (1) during dma transfer or after dma is forcibly suspended by nmi input, dma transfer is forcibly terminated. stgn note 2 if this bit is set (1) in the dma transfer enabled state (tcn bit = 0, enn bit = 1), dma transfer is started. <7> 6 5 4 <3> <2> <1> <0> this bit is set (1) at the last dma transfer and cleared (0) when it is read. dma transfer disabled dma transfer enabled enn 0 1 setting whether dma transfer via dma channel n is to be enabled or disabled ? this bit is cleared (0) when dma transfer ends. it is also cleared (0) when dma transfer is forcibly terminated by inputting nmi or setting (1) the initn bit. ? if the enn bit is set (1), do not set it until dma transfer has been completed the number of times set by the dbcn register or dma transfer is forcibly terminated by the initn bit. notes 1. tcn bit is read-only. 2. initn and stgn bits are write-only. if these bits are read, 0 is read. caution be sure to clear bits 6 to 4 to ?0?. if they are set to 1, the operation is not guaranteed.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 822 19.3.6 dma terminal count output control register (dtoc) the dma terminal count output control register (dtoc) is an 8-bit register that contro ls the terminal count output from each dma channel and dma transfer during nmi input. terminal count signals from each dma channel can be brought together and output from the tc0 pin. this register can be read or written in 8-bit units. reset input sets this register to 01h. caution to change the setting of the dtoc regi ster, be sure to stop all the dma operations. dmstpm dmstpm 0 1 0 0 0 tco3 tco2 tco1 tco0 6 7 54321 after reset: 01h r/w address: fffff8a0h dtoc 0 tco3-tco0 0 1 ? when the dmstpm bit = 0, processing of nmi can be executed immediately after the dma cycle under execution has been completed. to execute dma transfer that has been forcibly stopped, however, set the dchcn.initn bit (1) to forcibly terminate dma transfer, re-initialize, and then execute it (n = 0 to 3). ? when the dmstpm bit = 1, nmi processing is held pending in the block transfer mode until dma transfer has been executed the number of times specified in advance. in the single transfer mode and single-step transfer mode, nmi processing is executed after completion of the dma cycle under execution. to stop dma, set the dchcn.initn bit (1) and forcibly terminate dma transfer (n = 0 to 3). forcibly abort dma transfer when nmi is input. do not abort dma transfer when nmi is input. channel n terminal count signal not output from tc0 pin. channel n terminal count signal output from tc0 pin. control of dma transfer when nmi is input tc0 pin status flag the following shows an example of the case when the dtoc register is set to 03h. tc0 (output) tc2 (output) dma0 cpu dma0 dma1 dma1 cpu dma2 dma2 dma channel 2 terminal count dma channel 1 terminal count dma channel 0 terminal count
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 823 19.3.7 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that c ontrol the dma transfer start trigger via interrupt requests from on-chip peripheral i/o. the interrupt requests set by these register s serve as dma transfer startup factors. these registers can be read or written in 8-bit or 1-bit uni ts. however, bit 7 (dfn) and bits 5 to 0 (ifcn5 to ifcn0) can be read or written in 8-bit units. reset input clears these registers to 00h. cautions 1. to change the setti ng of the dtfrn register, be su re to stop the dma operation. 2. an interrupt request from an on-chip pe ripheral i/o input in the standby mode (idle or software stop mode) is held pending as a dma transfer start factor. the held dma start factor is executed after restor ing to the normal operation mode. 3. if the start source of dma transfer has been changed by us ing the ifcn5 to ifcn0 bits, be sure to clear the dfn bit (0) with an instruction immediately after. 4. if the transmission enable interrupt request signal (intstn) of uarta is used as the start source of dma transfer, for example, the start s ource of dma transfer that is started by the interrupt request signal generate d when the last transfer data is transferred to the uartan transmit shift register is held. in this case, clear the dfn bit (0) an d clear the dma transfer start source. dma transfer not requested dma transfer requested dfn note 0 1 dma transfer request flag dtfrn (n = 0 to 3) after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 <7>6543210 note only 0 can be written to this flag. if the interrupt specified as the dma transfer start fa ctor occurs and it is necessary to clear the dma transfer request while dma transfer is disabled (including when it is suspended by nmi, and is forcibly terminated by software), stop the operation of the source causing t he interrupt, and then clear the dfn bit (for example, disable reception in the case of serial reception). if it is clear that the interrupt will not occur until dma transfer is resumed next, it is not nec essary to stop the operati on of the source causing the interrupt. cautions 1. for the ifcn5 to ifcn0 bi ts, see table 19-1 dma start factors. 2. be sure to set bit 6 to 0. the operati on is not guaranteed when it is set to 1.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 824 table 19-1. dma start factor (1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request from on-chip peripheral i/o disabled 0 0 0 0 0 1 intp000/intccp00 0 0 0 0 1 0 intp001/intccp01 0 0 0 0 1 1 intp004/intcc101 0 0 0 1 0 0 intp005/intcc100 0 0 0 1 0 1 intp106 0 0 0 1 1 0 intp107 0 0 0 1 1 1 intp010/intccq0 0 0 1 0 0 0 intp011/intccq1 0 0 1 0 0 1 intp012/intccq2 0 0 1 0 1 0 intp013/intccq3 0 0 1 0 1 1 intp114 0 0 1 1 0 0 intp115 0 0 1 1 0 1 intp021/intccp10 0 0 1 1 1 0 intp022/intccp11 0 0 1 1 1 1 intp124 0 1 0 0 0 0 intp125 0 1 0 0 0 1 intp126 0 1 0 0 1 0 intp130 0 1 0 0 1 1 intp131 0 1 0 1 0 0 intp132 0 1 0 1 0 1 intp133 0 1 0 1 1 0 intp134 0 1 0 1 1 1 intp137 0 1 1 0 0 0 intp050/intccp20 0 1 1 0 0 1 intp051/intccp21 0 1 1 0 1 0 intcmd0 0 1 1 0 1 1 intcmd1 0 1 1 1 0 0 intcmd2 0 1 1 1 0 1 intcmd3 0 1 1 1 1 0 intcm100 0 1 1 1 1 1 intcm101 1 0 0 0 0 0 intovq 1 0 0 0 0 1 intser0/intcsier0 1 0 0 0 1 0 intsr0/intcsir0 1 0 0 0 1 1 intst0/intcsit0 1 0 0 1 0 0 intser1/intcsier1 1 0 0 1 0 1 intsr1/intcsir1 1 0 0 1 1 0 intst1/intcsit1 remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 825 table 19-1. dma start factor (2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 1 0 0 1 1 1 intser2/intcsier2 1 0 1 0 0 0 intsr2/intcsir2 1 0 1 0 0 1 intst2/intcsit2 1 0 1 0 1 0 intser3 1 0 1 0 1 1 intsr3/intiic 1 0 1 1 0 0 intst3 1 0 1 1 0 1 intad other than above setting prohibited remark n = 0 to 3 the relationship between the dmarqn signa l and the interrupt source that serv es as a dma transfer trigger is as follows (n = 0 to 3). dmarqn ifcn0 to ifcn5 internal dma request signal interrupt source selector cautions 1. if a dmarqn pin is sp ecified as the dma transfer start f actor, clear the dtfrn register to 00h. if an interrupt request is specified as the dma transfer start factor, mask the dmarqn signal input on the port side (pmc0 register, etc. ). in this case, an interrupt request will be generated with the start of dma transfer. to prevent an interrupt request from being generated, mask the interrupt by setting the interrupt request c ontrol register. dma transfer starts even if an interrupt is masked. 2. the start request of dma transfer by the dm arqn signal input in the standby mode (idle or software stop mode) does not serve as the start source of dma transfer. 3. if the frequency of the cpu clock falls be low the clock of each on-ch ip peripheral i/o because of the setting of the pcc.ck1 and pcc.ck0 bits, the start source of dma transfer may not be acknowledged.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 826 19.3.8 dma interface control register (difc) the difc register is an 8-bit regist er that of each dma channel and contro ls the mask function (dma mask mode) of the dmarqn signal (n = 0 to 3). this register can be read or written in 8-bit units. reset input clears this register to 00h. 0 drmkn 0 1 specification of dma mask mode (mask bit of dmarqn signal) (n = 0-3) 0 0 0 drmk3 drmk2 drmk1 drmk0 6 7 54321 difc 0 after reset: 00h r/w address: fffff8a8h do not mask the dmarqn signal. mask input of the dmarqn signal for the duration of 3 bus clocks from the rise of the dmaakn signal. cautions 1. be sure to clear bits 7 to 4 to ?0?. if they are set to 1, the operation is not guaranteed. 2. the mask function of the dmarqn signal (dma mask mode) is to mask only the dmarqn signal being serviced so that the dmarqn signal is not inadvertently ge nerated two times. after the dmaakn signal of the same channe l as the dmarqn signal is asserted, the dmarqn signal is masked for a mask period. masking of the other channels is not affected. if only the dmarqn signal of a high priority is masked and if a contention with other dmarqn signal occurs, the other dmarqn si gnal is not acknowledge d first during the mask period, regardle ss of the priority of the dmarqn signal.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 827 19.3.9 dmaak width control register (dakw) this 8-bit register controls the active width of the dmaakn signal of each dma channel (n = 0 to 3). this register can be read or written in 8-bit units. reset input clears this register to 00h. 00000 dakw2 dakw1 dakw0 6 7 54321 dakw 0 dakw2 0 0 0 0 1 1 1 1 dakw1 0 0 1 1 0 0 1 1 0cpu clock 1cpu clock 2cpu clock 3cpu clock 4cpu clock 5cpu clock 6cpu clock 7cpu clock specification of active extension width of dmaakn signal (n = 0 to 3) dakw0 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff8ach ? the active width of the dmaakn signal is extended in synchronization with the cpu clock (f cpu ). ? set the active width of the dmaakn signal at least one cpu clock width wider than the period of busclk. cautions 1. during flyby transfer , the active width of the dmaakn si gnal is not extended regardless of the set value of the dakw register. 2. the set value of the dakw register is reflected on all of signals dmaak0 to dmaak3. 3. if one or both of the following conditi ons is satisfied when the active width of the dmaakn signal is extended, the next dmaakn signal is asserted while an active extension width of the dmaakn signal is appended. as a result, the active cycle of two or more dmaakn signals is used as one dmaakn signal. consequently, the number of times the dmaakn signal is asserted may be less than the actual number of dma cycles. ? during block transfer or single-step transfer ? if the next dmarqn signal is asserted be fore the first dmaakn signal is deasserted during single transfer 4. be sure to clear bits 7 to 3 to ?0?. the operation cannot be guarant eed if these bits are set to 1.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 828 19.4 transfer modes 19.4.1 single transfer mode in single transfer mode, the dmac releases the bus at eac h byte/halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. if another dma trans fer request with a lower priority occurs one clock after single transfer has been completed, however, this request does not take precedence even if the previous dma transfer request signal with a higher priority remains acti ve. dma transfer with the newly requested lower priority request is executed after the cpu bus has been released. figures 19-1 to 19-4 show examples of single transfer. figure 19-1. single transfer example 1 cpu dmarq3 (input) cpu dma3 cpu dma3 cpu dma3 cpu cpu cpu cpu cpu cpu dma3 cpu dma3 cpu cpu cpu dma channel 3 terminal count note note note note note the bus is always released. figure 19-2 shows an example of a single transfer in which a higher priority dma request is issued. dma channels 0 to 2 are in the block transfer mode and channel 3 is in the single transfer mode. figure 19-2. single transfer example 2 cpu cpu cpu dma3 cpu dma0 dma0 cpu dma1 dma1 cpu dma2 dma2 cpu dma3 cpu dma3 dmarq3 (input) dmarq2 (input) dmarq1 (input) dmarq0 (input) dma channel 3 terminal count dma channel 0 terminal count dma channel 2 terminal count note note note note dma channel 1 terminal count note the bus is always released.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 829 figure 19-3 is an example of single transfer where a dma transfer request with a lower priority is issued one clock after single transfer has been completed. dma channels 0 and 3 are used for single transfer. if two dma transfer request signals become active at the same time, tw o dma transfer operations are alternately executed. figure 19-3. single transfer example 3 cpu cpu cpu dma0 dma0 cpu dma0 cpu dma0 cpu dma0 cpu cpu cpu dma0 cpu dma3 cpu dma3 dma channel 3 terminal count dma channel 0 terminal count dmarq3 (input) dmarq0 (input) note note note note note note note note the bus is always released. figure 19-4 is an example of single transfer where two or more dma transfer requests with a lower priority are issued one clock after single transfer has been completed. dma channels 0, 2, and 3 are used for single transfer. if three or more dma transfer request signals become active at the same time, two dma transfer operations are alternately executed, starting from the one with the highest priority. figure 19-4. single transfer example 4 cpu dma3 cpu dma3 cpu dma2 cpu dma2 cpu dma2 cpu dma2 cpu dma3 cpu cpu cpu dma3 cpu dma0 cpu dma0 dma channel 0 terminal count dma channel 2 terminal count dma channel 3 terminal count dmarq2 (input) dmarq3 (input) dmarq0 (input) note note note note note note note note note note the bus is always released.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 830 19.4.2 single-step transfer mode in single-step transfer mode, the dmac releases the bus at each byte/halfword transfer. if there is a subsequent dma transfer request signal (dmarq0 to dmarq3), transfe r is performed again. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher prio rity dma transfer request is issued, the higher priority dma request always takes precedence. the following shows an example of a single-step transfer. figure 19-6 shows an example of single-step transfer made in which a higher priority dma request is issued. dma channels 0 and 1 are in t he single-step transfer mode. figure 19-5. single-step transfer example 1 cpu cpu cpu dma1 cpu dma1 cpu dma1 cpu dma1 cpu cpu cpu cpu cpu cpu cpu dma channel 1 terminal count dmarq1 (input) note note note note the bus is always released. figure 19-6. single-step transfer example 2 cpu cpu cpu dma1 cpu dma1 cpu dma0 cpu dma0 cpu dma0 cpu dma1 cpu dma1 cpu dma channel 0 terminal count dma channel 1 terminal count dmarq1 (input) dmarq0 (input) note note note note note note note the bus is always released.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 831 19.4.3 block transfer mode in the block transfer mode, once transfer starts, the dm ac continues the transfer oper ation without releasing the bus until a terminal count occurs. no other dma requests are acknowledged during block transfer. after the block transfer ends and the dmac releases t he bus, another dma transfer can be acknowledged. the bus cycle of the cpu is not inserted during block transfer, but bus hold and refresh cycles are inserted between dma transfer operations. the following shows an example of block transfer in which a higher priority dma request is issued. dma channels 2 and 3 are in the block transfer mode. figure 19-7. block transfer example cpu cpu cpu dma3 dma3 dma3 dma3 dma3 dma3 dma3 dma3 cpu dma2 dma2 dma2 dma2 dma2 dma channel 3 terminal count the bus is always released. dmarq3 (input) dmarq2 (input)
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 832 19.5 transfer types 19.5.1 2-cycle transfer in 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and readin g is performed from the source to the dmac. in the second cycle, the destination address is output and writi ng is performed from the dmac to the destination. cautions 1. an idle cycle of 1 to 2 clocks is always inserted betwee n a read cycle and a write cycle. 2. for 2-cycle transfer from the on-chip periphera l i/o to the internal ram, refer to caution 4 of table 19-3 relationship between tran sfer type and transfer object. the dma access timing when no data exists in the write buffer is shown in figures 19-8 to 19-11 . refer to 5.6 write buffer function for the write buffer.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 833 figure 19-8. sram, external ro m, and external i/o access timing during 2-cycle dma transfer (sram external i/o): bmc register = 01h (1/2) (a) bcc register setting for sram: bcm1, bcm0 bits = 00, bcc register setting for external i/o: bcn1, bcn0 bits = 00 ti note 1 t2 t2 t1 t1 address data data address busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 2 (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in external i/o area (output) notes 1. idle state (ti) independent of the bcc register settings. 2. ube, lbe remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 834 figure 19-8. sram, external ro m, and external i/o access timing during 2-cycle dma transfer (sram external i/o): bmc register = 01h (2/2) (b) bcc register setting for sram: bcm1, bcm0 bits = 11, bcc register setting for external i/o: bcn1, bcn0 bits = 00 busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 3 (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in external i/o area (output) ti note 2 ti note 1 ti note 1 ti note 1 t2 t2 t1 t1 address data address data notes 1. idle state (ti) inserted depend ing on the bcc register settings. 2. idle state (ti) independent of the bcc register settings. 3. ube, lbe remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 835 figure 19-9. timing during 2-cycle dma transfer (sram external i/o): in sing le-step transfer mode (bcc register setting for sram: bcm1, bcm0 bits = 00, bcc register setting for external i/o: bcn1, bcn0 bits = 00) ti note 1 ti note 1 ti note 1 ti note 1 ti note 1 ti note 1 t2r t2w t1r t2w t1w t1w t2r t1r busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 2 (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in external i/o area (output) address address address address data data data data notes 1. idle state (ti) independent of the bcc register settings. 2. ube, lbe remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 836 figure 19-10. timing during 2-cycle dma transfer (sram sdram): bmc register = 01h (1/3) (a) in single transfer mode (csdc re gister setting for sram: csdcm bit = 1, asc register setting for sram: acm1, acm0 bits = 01) row col . twr tact t2r t1r tasw ti note 1 busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 2 (output) note 3 (output) sdras (output) sdcas (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in sdram area (output) data data address notes 1. idle state (ti) independent of the bcc register settings. 2. uwe/udqm, lwe/ldqm 3. ube/udqm, lbe/ldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6, m = 0, 4, 6, 7 (n m), x = 0 to 3 3. col.: column address row: row address
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 837 figure 19-10. timing during 2-cycle dma transfer (sram sdram): bmc register = 01h (2/3) (b) in single-step transfer mode (csdc register setting for sram: csdcm bit = 1, asc register setting for sram: acm1, acm0 bits = 01) busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 2 (output) note 3 (output) sdras (output) sdcas (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in sdram area (output) twr t2r t1r t2r t1r tasw tact twr tasw ti note 1 ti note 1 ti ti ti ti row col . col . data data data data address address notes 1. idle state (ti) independent of the bcc register settings. 2. uwe/udqm, lwe/ldqm 3. ube/udqm, lbe/ldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6, m = 0, 4, 6, 7 (n m), x = 0 to 3 3. col.: column address row: row address
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 838 figure 19-10. timing during 2-cycle dma transfer (sram sdram): bmc register = 01h (3/3) (c) in block transfer mode (csdc regi ster setting for sram: csdcm bit = 1, asc register setting for sram: acm1, acm0 bits = 01) row col. col. busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 2 (output) note 3 (output) sdras (output) sdcas (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in sdram area (output) data data data data address address twr t2r t1r t2r t1r tasw tact twr tasw ti note 1 ti note 1 notes 1. idle state (ti) independent of the bcc register settings. 2. uwe/udqm, lwe/ldqm 3. ube/udqm, lbe/ldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6, m = 0, 4, 6, 7 (n m), x = 0 to 3 3. col.: column address row: row address
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 839 figure 19-11. timing during 2-cycle dma transfer (sdram sram): bmc register = 01h (1/3) (a) in single transfer mode (csdc re gister setting for sram: csdcm bit = 1, asc register setting for sram: acm1, acm0 bits = 01) (scrn register setting for sdram: latency = 2, bcw = 2) h row col . busclk dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 2 (output) note 3 (output) sdras (output) sdcas (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in sdram area (output) data data address t2w t1w tlate tlate tact tread tw tasw ti note 1 notes 1. idle state (ti) independent of the bcc register settings. 2. uwe/udqm, lwe/ldqm 3. ube/udqm, lbe/ldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6, m = 0, 4, 6, 7 (n m), x = 0 to 3 3. col.: column address row: row address
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 840 figure 19-11. timing during 2-cycle dma transfer (sdram sram): bmc register = 01h (2/3) (b) in single-step transfer mode (csdc register setting for sram: csdcm bit = 1, asc register setting for sram: acm1, acm0 bits = 01) (scrn register setting for sdram: latency = 2, bcw = 2) row col . col . t1w t2w ti ti tread tlate tlate tasw t1w t2w tasw tlate tlate tread tact tw h ti note 1 ti note 1 ti note 1 busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 2 (output) note 3 (output) sdras (output) sdcas (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in sdram area (output) data data data data address address notes 1. idle state (ti) independent of the bcc register settings. 2. uwe/udqm, lwe/ldqm 3. ube/udqm, lbe/ldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6, m = 0, 4, 6, 7 (n m), x = 0 to 3 3. col.: column address row: row address
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 841 figure 19-11. timing during 2-cycle dma transfer (sdram sram): bmc register = 01h (3/3) (c) in block transfer mode (csdc regi ster setting to sram: csdcm bit = 1, asc register setting for sram: acm1, acm0 bits = 01) (scrn register setting to sdram: latency = 2, bcw = 2) h row col . col . busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) we (output) note 2 (output) note 3 (output) sdras (output) sdcas (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in sdram area (output) data data data data address address t1w t2w tread tlate tlate tasw t1w t2w tasw tlate tlate tread tact tw ti note 1 ti note 1 ti note 1 notes 1. idle state (ti) independent of the bcc register settings. 2. uwe/udqm, lwe/ldqm 3. ube/udqm, lbe/ldqm remarks 1. the broken lines indicate the high-impedance state. 2. n = 1, 3, 4, 6, m = 0, 4, 6, 7 (n m), x = 0 to 3 3. col.: column address row: row address
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 842 (1) active width of dmaakn signal the active width of the dmaakn signal output from the dm a controller is from the start of the read operation to the end of the writ e operation of the dma controller (n = 0 to 3) . however, the dmaakn signal is not asserted in cycles to write or read the internal ram. when t he external memory is written, asserting the dmaakn signal ends as soon as data has been transferred to th e write buffer. therefor e, handshaking between the dmarqn and dmaakn signals must be comp leted before the external i/o or exte rnal memory is written. if data of three buffers has already been stored in the wr ite buffer, for example, the data transferred by dma is stored in the fourth st age of the buffer and asserting the dmaakn sign al ends. after a write operation of the stored data has been executed three times, transfer to the external i/o or external memory that is controlled by the dmaakn signal whose assertion has ended is executed. (2) dmaakn signal active width extension function the dmaakn signal is output in synchro nization with the internal bus cycle during 2-cycle transfer, and is not synchronized with the external bus cycle (n = 0 to 3). depending on the target of dma transfer, the configuration may allo w the dmaakn signal to be asserted only for the duration of two internal system clocks (f clk ). in this case, assertion of the dmaakn signal may not be sampled with busclk if the internal system clock is divided and the bus clock (busclk) is used (e.g., bmc register = 02h: internal system clock divided by three). to sample assertion of the dmaakn signal with busclk , extend the active width of the dmaakn signal by setting the dakw register. the minimum value of the active width of the dmaakn during 2-cycle transfer is shown in the table below. table 19-2. minimum value of active widt h of dmaakn signal during 2-cycle transfer transfer destination external i/o/external memory on-chip peripheral i/o internal ram external i/o/external memory read cycle + 4 internal system clocks read cycle + (5+i) internal system clocks read cycle + 1 internal system clock on-chip peripheral i/o (6+i) internal system clocks (7+2i) internal system clocks (3+i) internal system clocks transfer source internal ram 2 internal system cl ocks (3+i) internal system clocks ? caution the function to extend the active width of the dmaakn signal can be used only during 2-cycle transfer (n = 0 to 3). the act ive width of the dmaakn signal is not extended regardless of the dakw register. the operation is not guaranteed if it is used during flyby transfer. during flyby transfer, the dmaakn signal synchroni zed with the bus cycle is output. remark i: number of wait cycles set by vswc register
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 843 (3) outline of 2-cycle transfer timing the timing of 2-cycle transfer when no data exists in the write buffer is outlined below. refer to 5.6 write buffer function for the write buffer. figure 19-12. outline of timing during 2-cycle transfer (sram sram): divided by 1 (0 sram waits) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 844 figure 19-13. outline of timing during 2-cycle transfer (sram sram): divided by 2 (0 sram waits) (a) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write (b) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 845 figure 19-14. outline of timing during 2-cycle transfer (sram sram): divided by 3 (0 sram waits) (1/2) (a) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write (b) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 846 figure 19-14. outline of timing during 2-cycle transfer (sram sram): divided by 3 (0 sram waits) (2/2) (c) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 847 figure 19-15. outline of timing during 2-cycle transfer (sram sram): divided by 4 (0 sram waits) (1/2) (a) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write (b) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 848 figure 19-15. outline of timing during 2-cycle transfer (sram sram): divided by 4 (0 sram waits) (2/2) (c) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write (d) t1 t2 t1 t2 internal system clock (f clk ) external bus status external memory cycle dmaakn (output) busclk (output) read write read write remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 849 19.5.2 flyby transfer since data is transferred in 1 cycle during a flyby transfe r, a memory address is always output irrespective of whether it is a source address or a destination address, and read/write signals of the memory and external i/o become active at the same time. ther efore, the external i/o is selected by the dmaak0 to dmaak3 signals. flyby transfer can be used only in the separate bus mode. to perform a normal access to the external i/o by means other than dma transfer, externally and the csm and dmaakx signals (m = 0 to 7, x = 0 to 3), and connect the result ant signal to the chip select signal of the external i/o. a circuit example of a normal access, other than dma transfer, to external i/o is shown below. caution if the memory is connected in the multiplexed bus mode, fl yby transfer cannot be executed. flyby transfer whose transfer object is sdram cannot be executed. figure 19-16. circuit example when flyby transfer is performed between external i/o and sram ax to axx d0 to d7 oe we csn sram ax to axx d8 to d15 oe we csn sram external i/o d0 to d15 rd wr cs ax to axx d0 to d15 rd lwr csn uwr v850e/ma3 iord csm iowr dmaakx remark n = 0 to 7, m = 0 to 7 (n m) x = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 850 figure 19-17. timing during dma flyby transfer (sram external i/o): in single transfer mode (t asw = 1, ti = 1 inserted) ti t2 t1 tasw data address busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) rd (output) iowr (output) note (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in external i/o area (output) note ube, lbe remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m), x = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 851 figure 19-18. timing during dm a flyby transfer (external i/o sram) (1/2) (a) in single-step transfer mode ti ti ti ti ti ti t2 t1 t2 t1 data data address address busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) we (output) iord (output) note (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in external i/o area (output) note ube, lbe remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m), x = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 852 figure 19-18. timing during dm a flyby transfer (external i/o sram) (2/2) (b) in block transfer mode t2 t1 t2 t1 data data address address busclk (output) dmarqx (input) dmaakx (output) tcx (output) bcyst (output) csm in sram area (output) we (output) iord (output) note (output) ad0 to ad15 (i/o) a0 to a25 (output) csn in external i/o area (output) note ube, lbe remarks 1. the broken lines indicate the high-impedance state. 2. n = 0 to 7, m = 0 to 7 (n m), x = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 853 19.6 transfer object 19.6.1 transfer type and transfer object table 19-3 lists the relationships between the transfer type and transfer object. the mark ? ? means ?transfer possible?, and the mark ? ? means ?transfer impossible?. table 19-3. relationship between tran sfer type and transfer object destination 2-cycle transfer flyby transfer note 3 internal rom on-chip peripheral i/o note 1 external i/o internal ram external memory internal rom on-chip peripheral i/o external i/o internal ram external memory on-chip peripheral i/o note 1 note 2 external i/o note 4 internal ram external memory note 2 note 2 note 4 source internal rom notes 1. if the transfer object is the on-chip peripher al i/o, only the single transfer mode can be used. 2. transfer can also be executed between a little-endian area and a big-endian area. 3. can be used only in separate bus mode. 4. flyby transfer of which transfer object is sdram cannot be executed. cautions 1. the operation is not guaranteed for comb inations of transfer dest ination and source marked with ? ? in table 19-3. 2. in the case of flyby transfer, make the da ta bus width the same for the source and destination. 3. addresses between 3fff000h and 3ffffffh ca nnot be specified for the source and destination address of dma transfer. be sure to specify an address between ffff000h and fffffffh. 4. when 2-cycle dma transfer from the on-chip peripheral i/o to the internal ram is executed during dma transfer of 2 cycles, tcn signal outp ut may be asserted twice, instead of once, after transfer of the last data, and the dma tr ansfer end interrupt (i ntdman) may occur twice (n = 0 to 3). however, dma transfer itself is normally ended. no such problem occurs during flyby transfer. to prevent this, do not use the tcn signal. for the excessive dma transfer end interrupts (intdman), execute the followi ng processing <1> and <2> in that order in the dma transfer end interrupt servicing routine. after processing <2>, by executing the appli cation processing that is normally executed and recovery from the interrupt, the second dma tr ansfer end interrupt (intdman) occurrence can be suppressed. <1> write 00h to the was register <2> clear the dmaicn.dmaifn bit to 0 in th e same channel as the dma transfer end interrupt (intdman) currently being serviced (n = 0 to 3).
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 854 remark during 2-cycle dma transfer, if the data bus width of the transfer source an d that of the transfer destination are different, the operation becomes as follows. if dma transfer is executed to transfer data of an on-chip peripheral i/o register (as a transfer source or destination), be sure to specify the same transfer size as the register size. for example, to execute dma transfer of an 8-bit register, be sure to specify byte (8-bit) transfer. <16-bit transfer> ? transfer from a 16-bit bus to an 8-bit bus a read cycle (16 bits) is generated and then a writ e cycle (8 bits) is generated twice consecutively. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated twice consecut ively and then a write cycle (16 bits) is generated. data is written to the transfer destination in the or der of the lower and higher byes in little endian, and in the order of the higher and lower bytes in big endian. <8-bit transfer> ? transfer from a 16-bit bus to an 8-bit bus a read cycle (the higher 8 bits are high impedance) is generate d and then a write cycle (8 bits) is generated. ? transfer from an 8-bit bus to a 16-bit bus a read cycle (8 bits) is generated and then a writ e cycle (the higher 8 bits are high impedance) is generated. data is written to the transfer destination in the order of the lower and higher byes in little endian, and in the order of the hi gher and lower bytes in big endian. 19.6.2 external bus cycles during dma transfer the external bus cycles during dma transfer are shown below. table 19-4. external bus cycles during dma transfer transfer type transfer object external bus cycle on-chip peripheral i/o, internal ram none ? external i/o yes sram cycle 2-cycle transfer external memory yes memory acce ss cycle set by the bct register flyby transfer between external memory and external i/o yes dma flyby transfer cycle accessing memory that is set as external memory by the bct register
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 855 19.7 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 in the block transfer mode, the channel used for transfer is never switched. in the single-step transfer mode, if a hi gher priority dma transfer request is issued while the bus is released, the higher priority dma transfer request is acknowledged. caution if dma is started by inputting the same signa l to more than one dmarqn pin (n = 0 to 3), a dma channel with a lower priority m ay be acknowledged before a dm a channel with a higher priority.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 856 19.8 next address setting function the dsanh, dsanl, ddanh, ddanl, and cbcn registers are two-stage fifo buffer registers consisting of a master register and a slave register (n = 0 to 3). when the terminal count is issued, these registers ar e automatically rewritten wit h the value that was set immediately before. if new dma transfer setting is made to these registers duri ng dma transfer, therefore, t he values of the registers are automatically updated to the new value after completion of transfer note . note to make new dma transfer setting, confirm that dm a transfer has been started. if a new setting is made before the start of dma transfer, t he set value is overwritten to bot h the master and slave registers. figure 19-9 shows the configur ation of the buffer register. figure 19-19. buffer register configuration data read data write master register slave register address/ count controller internal bus the actual dma transfer is executed in accor dance with the contents of the slave register. the set value to be reflected upon the master register and slave register differs as follows, depending on the timing (period) of setting. (1) period from system reset to the start of the first dma transfer the set values are reflected on bot h the master and slave registers. (2) during dma transfer (period start of dm a transfer to completion of dma transfer) the set value is reflected only on the master register an d not on the slave register (the slave register holds the set value for the next dma transfer). after completion of dma transfer, however, the contents of the master register are aut omatically overwritten to the slave register. if the value of each register is read during this per iod, the value of the sl ave register is read. to check that dma transfer has been started, confirm that the dmaakn signa l has been asserted or that the first transfer has been executed, by reading the dbcn register (n = 0 to 3). (3) period from completion of dma tran sfer to start of next dma transfer the set value is reflected on both the master and slave registers. remark ?completion of dma transfer? means either of the following cases. ? completion of dma transfer (terminal count) ? forced termination of dma transfer (setti ng initn bit of dchcn register to 1).
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 857 19.9 dma transfer start factors there are 3 types of dma transfer start factors, as shown below. (1) request from an external pin (dmarqn) requests from the dmarqn pin are sampled each time the busclk signal rises (n = 0 to 3). hold the request from dmarqn pin until the corresponding dmaakn si gnal becomes active. if a state whereby the dchcn.enn bit = 1 and tcn bit = 0 is set, the dmarqn signal becomes valid. if the dmarqn signal set by the dtfrn register becomes active in this status, dma transfer starts. (2) request from software if the dchcn.stgn, dchcn.enn, and dchcn.tcn bits are set as follows, dma transfer starts (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (3) request from on-chip peripheral i/o if, when the dchcn.enn and dchcn.tcn bits are set as show n below, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 858 19.10 terminal count output upon dma transfer end the terminal count signal (tcn) becomes active for one cl ock of busclk during the last dma transfer cycle (n = 3 to 0). the tcn signal becomes active at the clock following the clock in which the bcyst si gnal becomes active during the last dma transfer cycle. figure 19-20. terminal count sign al (tcn) timing example (1) cpu cpu dman dman dman cpu cpu dmarqn (input) tcn (output) dma channel n terminal count remark n = 0 to 3 the tcn signal becomes active for one clock at the beginni ng of the write cycle of t he last dma transfer when 2- cycle transfer is executed. when flyby transfer is executed, the tcn signal becomes active for one clo ck at the beginning of the last dma transfer cycle. figure 19-21. terminal count sign al (tcn) timing example (2) (1) 2-cycle transfer read cycle 2-cycle transfer (last) write cycle busclk (output) tcn (output) (2) flyby transfer flyby transfer cycle (last) busclk (output) tcn (output) remark n = 0 to 3
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 859 19.11 forcible interruption if the dtoc.dmstpm bit is 0, dma transfer can be forc ibly interrupted by nmi input during dma transfer. at such a time, the dmac resets the dchcn.enn bit of all channels to 0 and the dma transfer disabled state is entered. an nmi request can then be acknowledged after the dma transfer that was being executed when the nmi was input is comple te (n = 0 to 3). forcibly terminate and initialize dma by using the dchcn.initn bit.
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 860 19.12 forcible termination dma transfer can be forcibly terminated by the dchcn.initn bit, in addition to the forcible interruption operation by means of nmi input (n = 0 to 3). an example of forcible termination by the in itn bit is illustrated below (n = 0 to 3). figure 19-22. example of forcible termination of dma transfer (a) block transfer via dma channel 3 is st arted during block transfer via dma channel 2 cpu cpu cpu cpu dma2 dma2 dma2 dma2 dma2 cpu dma3 dma3 dma3 dma3 cpu cpu cpu dmarq2 (input) dmarq3 (input) dma channel 3 transfer start dma channel 3 terminal count forcible termination of dma channel 2 transfer, bus released dsa2, dda2, dbc2, dadc2, dchc2 register set dchc2 (init2 bit = 1) register set dsa3, dda3, dbc3, dadc3, dchc3 register set e22 bit = 1 tc2 bit = 0 e22 bit 0 tc2 bit = 0 e33 bit = 1 tc3 bit = 0 e33 bit 0 tc3 bit 1 (b) when transfer is aborted dur ing dma channel 1 block transfer, and transfer under another condition is executed cpu cpu cpu cpu dma1 dma1 dma1 dma1 dma1 dma1 cpu cpu cpu cpu dma1 dma1 dma1 cpu dmarq1 (input) forcible termination of dma channel 1 transfer, bus released dma channel 1 terminal count dsa1, dda1, dbc1, dadc1, dchc1 register set dadc1, dchc1 register set dchc1 (init1 bit = 1) register set dsa1, dda1, dbc1 register set e11 bit = 1 tc1 bit = 0 e11 bit 0 tc1 bit = 0 e11 bit 1 tc1 bit = 0 e11 bit 0 tc1 bit 1 remark the values of the dsan, ddan, and dbcn registers (n = 0 to 3) are retained even when dma transfer is forcibly stopped, because these regi sters are fifo-format buffer registers. the next transfer condition can be set to these registers even while dma transfer is in progress. on the other hand, the setting of the dadcn an d dchcn registers is invalid during dma transfer because these registers are not buffer registers (see 19.8 next address setting function , 19.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) , and 19.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) ).
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 861 19.13 times related to dma transfer the overhead before and after dma transfer and minimum number of execution internal system clocks for dma transfer are listed below. in the case of external memory access, the time depends on the type of external memory connected. table 19-5. number of minimum execution internal system clocks in dma cycle dma cycle minimum number of execution clocks <1> time to respond to dma re quest 4 internal system clocks note 1 external memory access differs depending on the memory connected internal ram access 2 in ternal system clocks note 2 <2> memory access on-chip peripheral i/o register access 4 internal system clocks + number of wait cycles specified by vswc register notes 1. if an external interrupt (intpn) is specified as a fact or of starting dma transfer, noise elimination time is added (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 11 4, 115, 124 to 126, 130 to 134, 137). 2. two clocks are required for the dma cycle. the minimum execution clock in the dma cycl e in each transfer mode is as follows. 2-cycle transfer ? single transfer: dma response time (<1>) + transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>) ? block transfer: dma response time (<1>) + (transfer source memory access (<2>) + 1 note + transfer destination memory access (<2>)) number of transfers note one clock is always inserted between the read cycl e and write cycle of dma transfer. however, two clocks are inserted when the undivided external bus clock is used. flyby transfer: dma response time (< 1>) + external memory access (<2>)
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 862 19.14 maximum response time for dma transfer request the response time for a dma transfer request becomes the longest under the following conditions (state in which all the refresh cycles for the sdram are enabled). caution the wait time caused by the fo llowing conditions is not included. ? when dma transfer triggered by ot her than the dmarqn pin input occurs ? external bus hold condition instruction fetch from an extern al memory using 8-bit data bus width execution of a bit manipulation in struction (set1, clr1, or not1) a branch instruction (jr, jarl, jmp, or bc ond) follows a bit manipulation instruction either dma transfer source or destination is internal ram the difc.drmkn bit = 1 sdram is used in four csm spaces response time tinst 16 + tdata 2 + tref 4 + busclk 4 dmaakn (output) ad0 to ad15 (i/o) dmarqn (input) dma cycle refresh data read data write fetch (32 bits) 2 fetch (32 bits) 2 busclk 4 dmarqn input masked for 4 busclk clocks from the rise of the dmaakn signal. number of channels in sdram area (4 max.) previous dma transfer ends tdata tdata tref 4 tinst 8 (8-bit bus) tinst 8 (8-bit bus) remarks 1. tinst: number of clocks per bus cycle during inst ruction fetch tdata: number of clocks per bus cycle dur ing data access tref: number of clocks per refresh cycle busclk 4: time for maski ng dmarqn input 2. n = 0 to 3 m = 1, 3, 4, 6
chapter 19 dma functions (dma controller) user?s manual u16397ej3v0ud 863 19.15 cautions (1) memory boundary the transfer operation is not guarant eed if the source or the destination address exceeds the area of dma objects (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (2) transfer of misaligned data dma transfer of 32-/16-bit bus width misaligned data is no t supported. if the source or the destination address is set to an odd address, the lsb of t he address is forcibly handled as ?0?. (3) bus arbitration for cpu when an external device is targeted for dma transfer, the cpu can access the internal rom and internal ram (when not subject to dma transfer). the cpu can access the internal ro m during dma transfer between the on-chip peripheral i/o and internal ram. (4) holding dmarqn signal be sure to keep the dmarqn signal active until the dmaakn signal becomes active (n = 0 to 3). (5) dmaakn signal output when the transfer object is internal ram, the dmaakn signal is not output during a dma cycle for internal ram (for example, if 2-cycle transfer is performed fr om internal ram to an ex ternal memory, the dmaakn signal is output only during a dma writ e cycle for the external memory). if the transfer object is the on-chip peripheral i/o, the dmaakn signal is output even in the dma cycle executed on the on- chip peripheral i/o. (6) dma start factors do not start two or more dma channels with the same fa ctor. if two or more dma channels are started with the same factor, the dma channel with a lower priority may be accepted before the dma channel with a higher priority. operation is not guaranteed in this case. (7) program execution and dma transfer with internal ram do not execute dma transfer to/from the internal ram a nd an instruction in the internal ram simultaneously. 19.15.1 suspension factors dma transfer is suspended if the following factors are issued. ? bus hold ? refresh cycle if the factor that is suspending dma transfer disappears, dma transfer promptly restarts. 19.16 dma transfer end when dma transfer ends and the dchcn.tcn bit is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3).
user?s manual u16397ej3v0ud 864 chapter 20 interrupt/exception processing function the v850e/ma3 is provided with a dedica ted interrupt controller (intc) for interrupt servicing and can process a total of 77 interrupt requests. an interrupt is an event that occu rs independently of program execution, and an except ion is an event whose occurrence is dependent on program execution. the v850e/ma3 can process interrupt requests from t he on-chip peripheral hardwar e and external sources. moreover, exception processing can be st arted by the trap instruction (softwar e exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 20.1 features { interrupts ? non-maskable interrupts: 2 sources (e xternal: 1 source, internal: 1 source) caution p20 is fixed to nmi input. the level of the nmi pin is read when the p2.p20 bit is read, regardless of the value of the pm2 and pmc2 regi sters. set the valid edge of the nmi pin by using the nmir and nmif registers (d efault value: falling edge detection). ? maskable interrupts external: 25 sources, internal: 49/50 sources (see table 1-1 ) ? 8 levels of programmable priorities (maskable interrupts) ? multiple interrupt contro l according to priority ? masks can be specified for each maskable interrupt request. ? noise elimination, edge detection, and valid edge specification for ex ternal interrupt request signals. { exceptions ? software exceptions: 32 sources ? exception traps: 2 sources ( illegal opcode exception and debug trap) interrupt sources are listed in table 20-1.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 865 table 20-1. interrupt source list (1/3) interrupt/exception source type classification name control register generating source generating unit default priority exception code handler address restored pc ? reset pin input pin reset interrupt reset ? wdt overflow (wdtres) wdt ? 0000h 00000000h undefined nmi ? nmi pin valid edge input pin 0010h 00000010h nextpc non-maskable interrupt intwdt ? wdt overflow wdt 0020h 00000020h undefined exception trap0n note 1 ? trap instruction ? ? 004nh 00000040h nextpc software exception exception trap1n note 1 ? trap instruction ? ? 005nh 00000050h nextpc exception trap exception ilgop/ dbg0 ? illegal instruction code/ dbtrap instruction ? ? 0060h 00000060h nextpc interrupt intwdtm wdtic wdt overflow (interval timer mode) wdt 0 0080h 00000080h nextpc interrupt intp000/ intccp00 p00ic0 intp000 pin/ tp0ccr0 capture input/ compare match pin/ tmp0 1 0090h 00000090h nextpc interrupt intp001/ intccp01 p00ic1 intp001 pin/ tp0ccr1 capture input/ compare match pin/ tmp0 2 00a0h 000000a0h nextpc interrupt intp004/ intcc101 p00ic4 intp004 pin/ cc101 capture input/ compare match pin/ tmenc10 3 00b0h 000000b0h nextpc interrupt intp005/ intcc100 p00ic5 intp005 pin/ cc100 capture input/ compare match pin/ tmenc10 4 00c0h 000000c0h nextpc interrupt intp106 p10ic6 intp106 pin pin 5 00d0h 000000d0h nextpc interrupt intp107 p10ic7 intp107 pin pin 6 00e0h 000000e0h nextpc interrupt intp010/ intccq0 p01ic0 intp010 pin/ tq0ccr0 capture input/ compare match note 2 pin/ tmq0 7 00f0h 000000f0h nextpc interrupt intp011/ intccq1 p01ic1 intp011 pin/ tq0ccr1 capture input/ compare match pin/ tmq0 8 0100h 00000100h nextpc interrupt intp012/ intccq2 p01ic2 intp012 pin/ tq0ccr2 capture input/ compare match pin/ tmq0 9 0110h 00000110h nextpc interrupt intp013/ intccq3 p01ic3 intp013 pin/ tq0ccr3 capture input/ compare match pin/ tmq0 10 0120h 00000120h nextpc interrupt intp114 p11ic4 intp114 pin pin 11 0130h 00000130h nextpc interrupt intp115 p11ic5 intp115 pin pin 12 0140h 00000140h nextpc maskable interrupt intp021/ intccp10 p02ic1 intp021 pin/ tp1ccr0 capture input/ compare match pin/ tmp1 13 0150h 00000150h nextpc notes 1. n = 0 to fh 2. when tmq0 is used in the 6-phase pw m output mode, it functions as in tccq0 (crest interrupt) from the tmq0 option (tmqop0).
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 866 table 20-1. interrupt source list (2/3) interrupt/exception source type classification name control register generating source generating unit default priority exception code handler address restored pc interrupt intp022/ intccp11 p02ic2 intp022 pin/ tp1ccr1 capture input/ compare match pin/ tmp1 14 0160h 00000160h nextpc interrupt intp124 p12ic4 intp124 pin pin 15 0170h 00000170h nextpc interrupt intp125 p12ic5 intp125 pin pin 16 0180h 00000180h nextpc interrupt intp126 p12ic6 intp126 pin pin 17 0190h 00000190h nextpc interrupt intp130 p13ic0 intp130 pin pin 18 01a0h 000001a0h nextpc interrupt intp131 p13ic1 intp131 pin pin 19 01b0h 000001b0h nextpc interrupt intp132 p13ic2 intp132 pin pin 20 01c0h 000001c0h nextpc interrupt intp133 p13ic3 intp133 pin pin 21 01d0h 000001d0h nextpc interrupt intp134 p13ic4 intp134 pin pin 22 01e0h 000001e0h nextpc interrupt intp137 p13ic7 intp137 pin pin 23 01f0h 000001f0h nextpc interrupt intp050/ intccp20 p05ic0 intp050 pin/ tp2ccr0 capture input/ compare match pin/ tmp2 24 0200h 00000200h nextpc interrupt intp051/ intccp21 p05ic1 intp051 pin/ tp2ccr1 capture input/ compare match pin/ tmp2 25 0210h 00000210h nextpc interrupt intcmd0 cmicd0 cmd0 compar e match tmd0 26 0220h 00000220h nextpc interrupt intcmd1 cmicd1 cmd1 compar e match tmd1 27 0230h 00000230h nextpc interrupt intcmd2 cmicd2 cmd2 compar e match tmd2 28 0240h 00000240h nextpc interrupt intcmd3 cmicd3 cmd3 compar e match tmd3 29 0250h 00000250h nextpc interrupt intcm100 cm10ic0 cm100 compare match tmenc10 30 0260h 00000260h nextpc interrupt intcm101 cm10ic1 cm101 compare match tmenc10 31 0270h 00000270h nextpc interrupt intovp0 ovpic0 tmp0 over flow tmp0 32 0280h 00000280h nextpc interrupt intovq ovqic tmq0 overflow/underflow note tmq0 33 0290h 00000290h nextpc interrupt intovp1 ovpic1 tmp1 overfl ow tmp1 34 02a0h 000002a0h nextpc interrupt intovp2 ovpic2 tmp2 overfl ow tmp2 35 02b0h 000002b0h nextpc interrupt intdma0 dmaic0 dma channel 0 transfer completion dma0 36 02c0h 000002c0h nextpc interrupt intdma1 dmaic1 dma channel 1 transfer completion dma1 37 02d0h 000002d0h nextpc interrupt intdma2 dmaic2 dma channel 2 transfer completion dma2 38 02e0h 000002e0h nextpc interrupt intdma3 dmaic3 dma channel 3 transfer completion dma3 39 02f0h 000002f0h nextpc interrupt intser0/ intcsier0 seic0 uarta0 receive error/ csib0 receive error uarta0/ csib0 40 0300h 00000300h nextpc maskable interrupt intsr0/ intcsir0 sric0 uarta0 reception completion/csib0 reception completion uarta0/ csib0 41 0310h 00000310h nextpc note when tmq0 is used in the 6-phase pw m output mode, it functions as in tovq (valley interrupt) from the tmq0 option (tmqop0).
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 867 table 20-1. interrupt source list (3/3) interrupt/exception source type classification name control register generating source generating unit default priority exception code handler address restored pc interrupt intst0/ intcsit0 stic0 uarta0 transmission enable/csib0 transmission enable uarta0/ csib0 42 0320h 00000320h nextpc interrupt intser1/ intcsier1 seic1 uarta1 receive error/ csib1 receive error uarta1/ csib1 43 0330h 00000330h nextpc interrupt intsr1/ intcsir1 sric1 uarta1 reception completion/csib1 reception completion uarta1/ csib1 44 0340h 00000340h nextpc interrupt intst1/ intcsit1 stic1 uarta1 transmission enable/csib1 transmission enable uarta1/ csib1 45 0350h 00000350h nextpc interrupt intser2/ intcsier2 seic2 uarta2 receive error/ csib2 receive error uarta2/ csib2 46 0360h 00000360h nextpc interrupt intsr2/ intcsir2 sric2 uarta2 reception completion/csib2 reception completion uarta2/ csib2 47 0370h 00000370h nextpc interrupt intst2/ intcsit2 stic2 uarta2 transmission enable/csib2 transmission enable uarta2/ csib2 48 0380h 00000380h nextpc interrupt intser3 seic3 uarta3 receiv e error uarta3 49 0390h 00000390h nextpc interrupt intsr3/ intiic note sric3 uarta3 reception completion/i 2 c serial transfer completion uarta3/ i 2 c 50 03a0h 000003a0h nextpc interrupt intst3 stic3 uarta3 transmission enable uarta3 51 03b0h 000003b0h nextpc maskable interrupt intad adic a/d conversion completion adc 52 03c0h 000003c0h nextpc note i 2 c bus versions (y products) only (see table 1-1 ) remarks 1. default priority: the priority order when tw o or more maskable interrupt request signals are generated at the same time. the highest priority is 0. restored pc: the value of the program counter (pc) saved to ei pc, fepc, or dbpc of the cpu when interrupt servicing is started. no te, however, that the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being exec uted does not become the nextp c. (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished. in this case, the address of the aborted instruction is the restore pc.) ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (onl y if an interrupt is generated before the stack pointer is updated) nextpc: the pc value from which the pr ocessing starts following interrupt/exception processing. 2. the execution address of the ill egal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4).
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 868 20.2 non-maskable interrupts a non-maskable interrupt request signal is acknowledged unc onditionally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupt request signals. the v850e/ma3 has the following two non-maskable interrupt request signals. ? nmi pin input (nmi) ? non-maskable interrupt request signal generat ed by overflow of watchdog timer (intwdt) the valid edge of the nmi pin is sele cted from the rising edge, falling edge, or both rising/falling edge by the nmir and nmif registers. intwdt functions when the wdtm.wdtm4 and wdtm.wdtm3 bits are set to ?10?. if two or more non-maskable interrupts occu r at the same time, the interrupt wit h a higher priority is serviced, as follows (the interrupt with a lower priority is ignored). intwdt > nmi if a new nmi or intwdt request is issued while an nm i is being serviced, it is serviced as follows. (1) if new nmi request is issu ed while nmi is being serviced the new nmi request is held pending, r egardless of the value of the psw.n p bit in the cpu. the pending nmi interrupt is acknowledged after the nmi currently under execution has been serviced (a fter the reti instruction has been executed). however, even if two or more ne w nmi requests are generated during nmi servicing, only one nmi request is acknowledged. (2) if intwdt request is issu ed while nmi is being serviced the intwdt request is held pending if the psw.np bit rema ins set (1) while the nmi is being serviced. the pending intwdt request is acknowledged after the nmi currently under execution has been serviced (after the reti instruction has been executed). if the psw.np bit is cleared (0) while the nmi is being serviced, the newly generated intwdt request is executed (the nmi servicing is stopped). caution if a non-maskable interrupt request is generated, the values of the pc and psw are saved to the nmi status save registers (fepc and fepsw). at this time, execution can be returned by the reti instruction only from an nmi. executi on cannot be returned wh ile intwdt is being serviced. therefore, reset the system a fter the interrupt has been serviced. figure 20-1. non-maskable interrupt requ est signal acknowledgment operation (1/2) (a) nmi and intwdt request signa ls generated at the same time main routine system reset nmi and intwd t requests (generated simultaneously) intwd t servicing
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 869 figure 20-1. non-maskable interrupt requ est signal acknowledgment operation (2/2) (b) non-maskable interrupt request signal ge nerated during non-maskable interrupt servicing non-maskable interrupt being serviced non-maskable interrupt request signal generated during non-maskable interrupt servicing nmi intwdt nmi ? nmi request generated during nmi servicing ? intwdt request generated during nmi servicing (psw.np bit = 1 retained before intwdt request) main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request main routine system reset nmi request nmi servicing (held pending) intwdt servicing intwdt request ? intwdt request generated during nmi servicing (np bit = 0 set before intwdt request) main routine system reset nmi request nmi servicing intwdt servicing intwdt request ? intwdt request generated during nmi servicing (np bit = 0 set after intwdt request) main routine system reset nmi request nmi servicing intwdt servicing np bit = 0 ? intwdt request generated during intwdt servicing main routine system reset intwdt request intwdt servicing (invalid) ? nmi request generated during intwdt servicing intwdt main routine system reset intwdt request intwdt servicing (invalid) nmi request (held pending) intwdt request intwdt request np bit = 0
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 870 20.2.1 operation if a non-maskable interrupt request signal is generated, t he cpu performs the following processing, and transfers control to the handler routine. (1) saves the restored pc to fepc. (2) saves the current psw to fepsw. (3) writes the exception code (0010h, 0020h) to the higher halfword (fecc) of ecr. (4) sets the psw.np and psw.id bits to 1 and clears the psw.ep bit to 0. (5) loads the handler address (00000010h, 00000020h) of the non-maskable interrupt routine to the pc, and transfers control. the following shows the non-mask able interrupt servicing. figure 20-2. non-maskable interrupt servicing nmi input non-maskable interrupt request interrupt servicing interrupt request pending fepc fepsw ecr. fecc psw. np psw. ep psw. id pc restored pc psw exception code 1 0 1 handler address 00000010h (nmi) 00000020h (intwdt) handler address: intc acknowledged cpu processing psw. np 1 0
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 871 20.2.2 restore (1) nmi input execution is restored from the nmi se rvicing by the reti instruction. when the reti instruction is execut ed, the cpu performs the following proc essing, and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw fr om fepc and fepsw, respectively, because the psw.ep bit is 0 and the psw.np bit is 1. <2> transfers control back to the address of the restored pc and psw. the following illustrates how the reti instruction is processed. figure 20-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during nmi servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep bit back to 0 and psw.np bit back to 1 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow. (2) intwdt signal execution cannot be restored by the re ti instruction. reset the system after interrupt servicing has been completed.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 872 20.2.3 non-maskable interrupt status flag (np) the np flag is a status flag that indicates that non-maskable interrupt servicing is under execution. this flag is set when a non-maskable interrupt r equest signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt servicing in progress np 0 1 non-maskable interrupt servicing status after reset: 00000020h
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 873 20.3 maskable interrupts maskable interrupt request signals can be masked by interrupt control registers. t he v850e/ma3 has 75 maskable interrupt sources. if two or more maskable interrupt request signals ar e generated at the same ti me, they are acknowledged according to the default priority. in addition to the default prio rity, eight levels of prioriti es can be specified by using the interrupt control registers (p rogrammable priority control). when an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (di) status is set. when the ei instruction is ex ecuted in an interrupt service routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a higher priority than the interrupt reques t signal in progress (specified by the interrupt control register). note t hat only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to enable multiple interrupt servicing, however, save ei pc and eipsw to memory or registers before executing the ei instruction, and ex ecute the di instruction before the reti instruction to restor e the original values of eipc and eipsw. 20.3.1 operation if a maskable interrupt occurs, the cpu performs the fo llowing processing, and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the psw.id bit to 1 and clears the psw.ep bit to 0. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request signal masked by interrupt controller (intc) and the maskable interrupt request signal generated while another interrupt is being serviced (while psw.np bit = 1 or psw.id bit = 1) are held pending inside the intc. in this case, servicing a new maskable in terrupt is started in accor dance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unm asked or np and id bits are cleared to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 874 figure 20-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc acknowledged yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address note for the ispr register, see 20.3.6 in-service prio rity register (ispr) .
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 875 20.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is execut ed, the cpu performs the following steps , and transfers control to the address of the restored pc. <1> restores the values of the pc and the psw fr om eipc and eipsw because t he psw.ep bit is 0 and the psw.np bit is 0. <2> transfers control to the address of the restored pc and psw. the following illustrates the proce ssing of the reti instruction. figure 20-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 20.3.6 in-service prio rity register (ispr) . caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to restor e the pc and psw correctly during recovery by the reti instruction, it is necessary to set ep bit back to 0 a nd np bit back to 0 using the ldsr instruction immediately be fore the reti instruction. remark the solid line shows the cpu processing flow.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 876 20.3.3 priorities of maskable interrupts the v850e/ma3 provides multiple inte rrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority leve l control: control based on the default priority leve ls, and control based on the programmable priority levels that are spec ified by the interrupt priority level s pecification bit (xxprn ) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupts ar e serviced in order depending on the priority level allocated to each interrupt request signal type (default priority level) beforehand. for more information, see table 20-1 interrupt source list . programmable priority control customizes interrupt request signals into eight levels by the setting of the priority level specification flag. note that when an interrupt request signal is acknowledged, the psw.id flag is aut omatically set to 1. therefore, when multiple interrupts are to be used, cl ear the id flag to 0 beforehand (for exampl e, by placing the ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see table 20-2 )
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 877 figure 20-6. example of processing in which a nother interrupt request signal is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 878 figure 20-6. example of processing in which a nother interrupt request signal is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 879 figure 20-7. example of servicing interrupt request signals simu ltaneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. nmi request caution to perform multiple interrupt servicing, the values of the eipc and ei psw registers must be saved before executing the ei instru ction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates t he relative priority between two interrupt request signals.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 880 20.3.4 interrupt control register (xxlcn) the xxicn register is assigned to each maskable interrupt request signal and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 47h. caution be sure to read the xxicn. xxifn bit while interrupts are disabled (d i). if the xxifn bit is read while interrupts are enabled (ei), an incorrect value may be read if there is a conflict between acknowledgment of the interrupt and reading of the bit. xxifn interrupt request signal not generated interrupt request signal generated xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 enable interrupt servicing disable interrupt servicing (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest) specifies level 1 specifies level 2 specifies level 3 specifies level 4 specifies level 5 specifies level 6 specifies level 7 (lowest) xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff110h to fffff178h < > < > note automatically reset by hardware when in terrupt request signal is acknowledged. remark xx: identifying name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see tables 20-2 ) the following tables list the addresses and bits of the interrupt control registers.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 881 table 20-2. addresses and bits of interrupt control registers (1/2) bit address register <7> <6> 5 4 3 2 1 0 fffff110h wdtic wdtif wdtmk 0 0 0 wdtpr2 wdtpr1 wdtpr0 fffff112h p00ic0 p00if0 p00mk0 0 0 0 p00pr02 p00pr01 p00pr00 fffff114h p00ic1 p00if1 p00mk1 0 0 0 p00pr12 p00pr11 p00pr10 fffff116h p00ic4 p00if4 p00mk4 0 0 0 p00pr42 p00pr41 p00pr40 fffff118h p00ic5 p00if5 p00mk5 0 0 0 p00pr52 p00pr51 p00pr50 fffff11ah p10ic6 p10if6 p10mk6 0 0 0 p10pr62 p10pr61 p10pr60 fffff11ch p10ic7 p10if7 p10mk7 0 0 0 p10pr72 p10pr71 p10pr70 fffff11eh p01ic0 p01if0 p01mk0 0 0 0 p01pr02 p01pr01 p01pr00 fffff120h p01ic1 p01if1 p01mk1 0 0 0 p01pr12 p01pr11 p01pr10 fffff122h p01ic2 p01if2 p01mk2 0 0 0 p01pr22 p01pr21 p01pr20 fffff124h p01ic3 p01if3 p01mk3 0 0 0 p01pr32 p01pr31 p01pr30 fffff126h p11ic4 p11if4 p11mk4 0 0 0 p11pr42 p11pr41 p11pr40 fffff128h p11ic5 p11if5 p11mk5 0 0 0 p11pr52 p11pr51 p11pr50 fffff12ah p02ic1 p02if1 p02mk1 0 0 0 p02pr12 p02pr11 p02pr10 fffff12ch p02ic2 p02if2 p02mk2 0 0 0 p02pr22 p02pr21 p02pr20 fffff12eh p12ic4 p12if4 p12mk4 0 0 0 p12pr42 p12pr41 p12pr40 fffff130h p12ic5 p12if5 p12mk5 0 0 0 p12pr52 p12pr51 p12pr50 fffff132h p12ic6 p12if6 p12mk6 0 0 0 p12pr62 p12pr61 p12pr60 fffff134h p13ic0 p13if0 p13mk0 0 0 0 p13pr02 p13pr01 p13pr00 fffff136h p13ic1 p13if1 p13mk1 0 0 0 p13pr12 p13pr11 p13pr10 fffff138h p13ic2 p13if2 p13mk2 0 0 0 p13pr22 p13pr21 p13pr20 fffff13ah p13ic3 p13if3 p13mk3 0 0 0 p13pr32 p13pr31 p13pr30 fffff13ch p13ic4 p13if4 p13mk4 0 0 0 p13pr42 p13pr41 p13pr40 fffff13eh p13ic7 p13if7 p13mk7 0 0 0 p13pr72 p13pr71 p13pr70 fffff140h p05ic0 p05if0 p05mk0 0 0 0 p05pr02 p05pr01 p05pr00 fffff142h p05ic1 p05if1 p05mk1 0 0 0 p05pr12 p05pr11 p05pr10 fffff144h cmicd0 cmif0 cmmk0 0 0 0 cmpr02 cmpr01 cmpr00 fffff146h cmicd1 cmif1 cmmk1 0 0 0 cmpr12 cmpr11 cmpr10 fffff148h cmicd2 cmif2 cmmk2 0 0 0 cmpr22 cmpr21 cmpr20 fffff14ah cmicd3 cmif3 cmmk3 0 0 0 cmpr32 cmpr31 cmpr30 fffff14ch cm10ic0 cm10if0 cm10mk0 0 0 0 cm10pr02 cm10pr01 cm10pr00 fffff14eh cm10ic1 cm10if1 cm10mk1 0 0 0 cm10pr12 cm10pr11 cm10pr10 fffff150h ovpic0 ovpif0 ovpmk0 0 0 0 ovppr02 ovppr01 ovppr00 fffff152h ovqic ovqif ovqmk 0 0 0 ovqpr2 ovqpr1 ovqpr0 fffff154h ovpic1 ovpif1 ovpmk1 0 0 0 ovppr12 ovppr11 ovppr10 fffff156h ovpic2 ovpif2 ovpmk2 0 0 0 ovppr22 ovppr21 ovppr20 fffff158h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 882 table 20-2. addresses and bits of interrupt control registers (2/2) bit address register <7> <6> 5 4 3 2 1 0 fffff15ah dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff15ch dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff15eh dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff160h seic0 seif0 semk0 0 0 0 sepr02 sepr01 sepr00 fffff162h sric0 srif0 srmk0 0 0 0 srpr02 srpr01 srpr00 fffff164h stic0 stif0 stmk0 0 0 0 stpr02 stpr01 stpr00 fffff166h seic1 seif1 semk1 0 0 0 sepr12 sepr11 sepr10 fffff168h sric1 srif1 srmk1 0 0 0 srpr12 srpr11 srpr10 fffff16ah stic1 stif1 stmk1 0 0 0 stpr12 stpr11 stpr10 fffff16ch seic2 seif2 semk2 0 0 0 sepr22 sepr21 sepr20 fffff16eh sric2 srif2 srmk2 0 0 0 srpr22 srpr21 srpr20 fffff170h stic2 stif2 stmk2 0 0 0 stpr22 stpr21 stpr20 fffff172h seic3 seif3 semk3 0 0 0 sepr32 sepr31 sepr30 fffff174h sric3 srif3 srmk3 0 0 0 srpr32 srpr31 srpr30 fffff176h stic3 stif3 stmk3 0 0 0 stpr32 stpr31 stpr30 fffff178h adic adif admk 0 0 0 adpr2 adpr1 adpr0
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 883 20.3.5 interrupt mask register s 0 to 3 (imr0 to imr3) the imr0 to imr3 registers set the interrupt mask st ate for the maskable interrupt s. the imr0.xxmkn to imr3.xxmkn bits are equivalent to the xxicn.xxmkn bit. the imrm register can be read or written in 16-bit units. if the higher 8 bits of the imrm regi ster are used as the im rmh register and the lowe r 8 bits as the imrml register, these registers can be read or written in 8-bit or 1-bit units. reset input sets these registers to ffffh. caution the device file defines the xxicn.xxmkn bit as a reser ved word. if a bit is manipulated using the name of xxmkn, the contents of th e xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). cm10mk1 p13mk7 imr1 (imr1h note ) (imr1l) cm10mk0 p13mk4 cmmk3 p13mk3 cmmk2 p13mk2 cmmk1 p13mk1 cmmk0 p13mk0 p05mk1 p12mk6 p05mk0 p12mk5 after reset: ffffh r/w address: imr1 fffff102h imr1l fffff102h, imr1h fffff103h after reset: ffffh r/w address: imr2 fffff104h imr2l fffff104h, imr2h fffff105h after reset: ffffh r/w address: imr3 fffff106h imr3l fffff106h, imr3h fffff107h srmk2 dmamk3 imr2 (imr2h note ) (imr2l) semk2 dmamk2 stmk1 dmamk1 srmk1 dmamk0 semk1 ovpmk2 stmk0 ovpmk1 srmk0 ovqmk semk0 ovpmk0 1 1 xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled imr3 (imr3h note ) (imr3l) 1 1 1 1 1 admk 1 stmk3 1 srmk3 1 semk3 1 stmk2 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 p12mk4 p01mk0 imr0 (imr0h note ) (imr0l) p02mk2 p10mk7 p02mk1 p10mk6 p11mk5 p00mk5 p11mk4 p00mk4 p01mk3 p00mk1 p01mk2 p00mk0 p01mk1 wdtmk after reset: ffffh r/w address: imr0 fffff100h imr0l fffff100h, imr0h fffff101h 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 interrupt mask flag setting 14 15 1 2 3 4 5 6 7 0 note when reading/writing bits 15 to 8 of t he imr0 to imr3 registers in 8-bit or 1-bit units, specify these bits as bits 7 to 0 of the imr0h to imr3h registers. caution set bits 15 to 5 of the imr3 register (bits 7 to 0 of the imr3h register and bits 7 to 5 of the imr3l register) to 1. if these bits ar e not 1, the operation cannot be guaranteed. remark xx: identification name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see table 20-2 )
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 884 20.3.6 in-service priori ty register (ispr) the ispr register holds the priority level of the maskable interrupt curr ently acknowledged. when an interrupt request signal is acknowledged, the bit of th is register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. when the reti instruction is execut ed, the bit corresponding to the inte rrupt request signal having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non- maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. caution in the interrupt enabled (ei) state, if an interrupt is acknowle dged during the reading of the ispr register, the value of the ispr register may be read after the bit is set (1) by this interrupt acknowledgment. to read the value of the ispr register properly before interrupt acknowledgment, read it in the interrupt disabled (di) state. ispr7 interrupt request signal with priority n is not acknowledged interrupt request signal with priority n is being acknowledged isprn 0 1 priority of interrupt currently being acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah < > < > < > < > < > < > < > < > remark n: 0 to 7 (priority level) 20.3.7 maskable interrupt status flag (id) the id flag controls the maskable in terrupt?s operating state, and stores control information regarding enabling or disabling of interrupt requests. t he id flag is allocated to the psw. this flag is set to 00000020h after reset. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled (pending) id 0 1 maskable interrupt servicing specification note after rest: 00000020h note interrupt disable flag (id) function id is set (1) by the di instruction and cleared (0) by t he ei instruction. its val ue is also modified by the reti instruction or ldsr inst ruction when referencing the psw. non-maskable interrupts and exceptions are ackno wledged regardless of this flag. when a maskable interrupt is acknowledged, the id flag is automatically set (1) by hardware. an interrupt request signal generated during the a cknowledgment disabled period (id flag = 1) can be acknowledged when the xxicn.xxifn bit is se t (1), and the id flag is cleared (0).
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 885 20.4 external interrupt request input pins (nmi, intpn) 20.4.1 noise elimination (1) noise elimination of nmi pin nmi pin incorporates a noise eliminator using analog delay. the delay time is typ. 80 ns. a signal input that changes within the delay time is not internally acknowledged. (2) noise elimination of intpn pin the intpn pin incorporates a noise eliminator us ing analog delay (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, and 137). the delay time is typ. 80 ns. a signal input that changes within the delay ti me is not internally acknowledged. 20.4.2 edge detection the valid edge of the nmi and intpn pins can be select ed by program (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, and 137). moreover , a level trigger can be selected for the intpn pin. the edge that can be selected as the valid edge is one of the following. ? rising edge ? falling edge ? both the rising and falling edges the edge-detected nmi and intpn signal s become interrupt sources. the valid edge and level trigger are specified by nmir, nmif, intr0 to intr3, in tr5, intf0 to intf3, and intf5 registers. caution to change the mode from th e external interrupt input (intpn) mode to the port mode or other alternate functions, mask the external interr upt input by using the xxica.xxmka bit. remark xx: identifying name of each peripheral unit (see table 20-2 ) a: peripheral unit number (see table 20-2 )
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 886 (1) nmi rising edge specification register (nmir) , nmi falling edge specification register (nmif) the nmir and nmif registers are regi sters that specify the valid edge of an nmi pin. the nmi valid edge can be specified to be either the rising edge, t he falling edge, or both the rising and falling edges. this register can be read or written in 8-bit or 1-bit units. reset input clears these registers to 00h. 7 0 nmif 6 0 5 0 4 0 3 0 2 0 1 0 <0> nmif0 after reset: 00h r/w address: fffffc1eh 7 0 nmir 6 0 5 0 4 0 3 0 2 0 1 0 <0> nmir0 after reset: 00h r/w address: fffffc3eh remark for how to specify a valid edge, see table 20-3 . table 20-3. valid edge specification nmif0 nmir0 valid edge specification 0 0 falling edge 0 1 rising edge 1 0 setting prohibited 1 1 both rising and falling edges
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 887 (2) external interrupt rising edge specification register 0 (intr0), external interrupt falling edge specification register 0 (intf0) the intr0 and intf0 registers are 8- bit registers that specify the tr igger mode of the intp000, intp001, intp004, intp005, intp106, and intp107 pins and c an specify the valid edge independently for each pin (rising edge, falling edge, or both rising and falling edges). these registers can be read or wr itten in 8-bit or 1-bit units. reset input clears the intr0 register to 00h and sets the intf0 register to f3h. caution before setting the intp000, intp001, in tp004, intp005, intp106, or intp107 pin in the trigger mode, set the pmc0 register. if the pmc0 register is set after the intr 0 and intf0 registers have been set, an illegal interrupt may occur, depending on the timing of setting the pmc0 register. <7> intf07 intf0 <6> intf06 <5> intf05 <4> intf04 3 0 2 0 <1> intf01 <0> intf00 after reset: f3h r/w address: fffffc00h <7> intr07 intr0 <6> intr06 <5> intr05 <4> intr04 3 0 2 0 <1> intr01 <0> intr00 after reset: 00h r/w address: fffffc20h remark for the valid edge specification, see table 20-4 . table 20-4. valid edge specification of intp000, intp001, intp004, intp005, intp106, and intp107 pins intf0n intr0n valid edge specification (n = 0, 1, 4 to 7) 0 0 level detection (low level detection) note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges note when a lower priority level-detection interrupt r equest (intpm) occurs while another interrupt is being serviced and this newly generated level-detection interr upt request becomes inacti ve before the current interrupt servicing is complete, this new interr upt request (intpm) is held pending (m = 000, 001, 004, 005, 106, 107). to avoid acknowledging this intpm interrupt request, clear the px0ifn bit of the interrupt control register. remark n = 0, 1, 4 to 7: control of intp000, in tp001, intp004, intp005, intp106, and intp107 pins
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 888 (3) external interrupt rising edge specification register 1 (intr1), external interrupt falling edge specification register 1 (intf1) the intr1 and intf1 registers are 8-bi t registers that specify the tri gger mode of the intp010 to intp013, intp114, and intp115 pins and can specify the valid edge independently for each pin (rising edge, falling edge, or both rising and falling edges). these registers can be read or wr itten in 8-bit or 1-bit units. reset input clears the intr1 register to 00h and sets the intf1 register to 3fh. caution before setting the intp010 to intp013, intp 114, or intp115 pin in the trigger mode, set the pmc1 register. if the pmc1 register is set after the intr 1 and intf1 registers have been set, an illegal interrupt may occur, depending on the timing of setting the pmc1 register. 7 0 intf1 6 0 <5> intf15 <4> intf14 <3> intf13 <2> intf12 <1> intf11 <0> intf10 after reset: 3fh r/w address: fffffc02h 7 0 intr1 6 0 <5> intr15 <4> intr14 <3> intr13 <2> intr12 <1> intr11 <0> intr10 after reset: 00h r/w address: fffffc22h remark for the valid edge specification, see table 20-5 . table 20-5. valid edge specification of intp010 to intp013, intp114, and intp115 pins intf1n intr1n valid edge specification (n = 0 to 5) 0 0 level detection (low level detection) note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges note when a lower priority level-detection interrupt r equest (intpm) occurs while another interrupt is being serviced and this newly generated level-detection interr upt request becomes inacti ve before the current interrupt servicing is complete, this new interr upt request (intpm) is hel d pending (m = 010 to 013, 114, 115). to avoid acknowledging this intpm interrupt r equest, clear the px1ifn bit of the interrupt control register. remark n = 0 to 5: control of intp010 to intp013, intp114, and intp115 pins
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 889 (4) external interrupt rising edge specification register 2 (intr2), external interrupt falling edge specification register 2 (intf2) the intr2 and intf2 registers are 8-bi t registers that specify the tri gger mode of the intp021, intp022, and intp124 to intp126 pins and can specify the valid edge independently for each pin (rising edge, falling edge, or both rising and falling edges). these registers can be read or wr itten in 8-bit or 1-bit units. reset input clears the intr2 register to 00h and sets the intf2 register to 76h. caution before setting the intp021, intp022, or in tp124 to intp126 pin in the trigger mode, set the pmc2 register. if the pmc2 register is set after the intr 2 and intf2 registers have been set, an illegal interrupt may occur, depending on the timing of setting the pmc2 register. 7 0 intf2 <6> intf26 <5> intf25 <4> intf24 3 0 <2> intf22 <1> intf21 0 0 after reset: 76h r/w address: fffffc04h 7 0 intr2 <6> intr26 <5> intr25 <4> intr24 3 0 <2> intr22 <1> intr21 0 0 after reset: 00h r/w address: fffffc24h remark for the valid edge specification, see table 20-6 . table 20-6. valid edge specification of intp021, intp022, and intp024 to intp126 pins intf2n intr2n valid edge specification (n = 1, 2, 4 to 6) 0 0 level detection (low level detection) note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges note when a lower priority level-detection interrupt r equest (intpm) occurs while another interrupt is being serviced and this newly generated level-detection interr upt request becomes inacti ve before the current interrupt servicing is complete, this new interr upt request (intpm) is hel d pending (m = 021, 022, 124 to 126). to avoid acknowledging this intpm interrupt r equest, clear the px2ifn bit of the interrupt control register. remark n = 1, 2, 4 to 6: control of in tp021, intp022, and intp124 to intp126 pins
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 890 (5) external interrupt rising edge specification register 3 (intr3), external interrupt falling edge specification register 3 (intf3) the intr3 and intf3 registers are 8- bit registers that specify the tr igger mode of the intp130 to intp134 and intp137 pins and can specify t he valid edge independently for each pin (rising edge, falling edge, or both rising and falling edges). these registers can be read or wr itten in 8-bit or 1-bit units. reset input clears the intr3 register to 00h and sets the intf3 register to 9fh. caution before setting the intp130 to intp134 or intp137 pin in the trigger mode, set the pmc3 register. if the pmc3 register is set after the intr 3 and intf3 registers have been set, an illegal interrupt may occur, depending on the timing of setting the pmc3 register. <7> intf37 intf3 6 0 5 0 <4> intf34 <3> intf33 <2> intf32 <1> intf31 <0> intf30 after reset: 9fh r/w address: fffffc06h <7> intr37 intr3 6 0 5 0 <4> intr34 <3> intr33 <2> intr32 <1> intr31 <0> intr30 after reset: 00h r/w address: fffffc26h remark for the valid edge specification, see table 20-7 . table 20-7. valid edge specification of intp130 to intp134, and intp137 pins intf3n intr3n valid edge specification (n = 0 to 4, 7) 0 0 level detection (low level detection) note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges note when a lower priority level-detection interrupt r equest (intpm) occurs while another interrupt is being serviced and this newly generated level-detection interr upt request becomes inacti ve before the current interrupt servicing is complete, this new interr upt request (intpm) is held pending (m = 130 to 134, 137). to avoid acknowledging this intpm interrupt request, clear the p13ifn bit of the in terrupt control register. remark n = 0 to 4, 7: control of intp130 to intp134, and intp137 pins
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 891 (6) external interrupt rising edge specification register 5 (intr5), external interrupt falling edge specification register 5 (intf5) the intr5 and intf5 registers are 8-bit registers t hat specify the trigger m ode of the intp050 and intp051 pins and can specify the valid edge independently for each pin (rising edge, falling edge, or both rising and falling edges). these registers can be read or wr itten in 8-bit or 1-bit units. reset input clears the intr5 register to 00h and sets the intf5 register to 03h. caution before setting the intp050 or intp051 pin in the trigger mode, set the pmc5 register. if the pmc5 register is set after the intr 5 and intf5 registers have been set, an illegal interrupt may occur, depending on the timing of setting the pmc5 register. 7 0 intf5 6 0 5 0 4 0 3 0 2 0 <1> intf51 <0> intf50 after reset: 03h r/w address: fffffc0ah 7 0 intr5 6 0 5 0 4 0 3 0 2 0 <1> intr51 <0> intr50 after reset: 00h r/w address: fffffc2ah remark for the valid edge specification, see table 20-8 . table 20-8. valid edge specification of intp050 and intp051 pins intf5n intr5n valid edge specification (n = 0, 1) 0 0 level detection (low level detection) note 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges note when a lower priority level-detection interrupt r equest (intpm) occurs while another interrupt is being serviced and this newly generated level-detection interr upt request becomes inacti ve before the current interrupt servicing is complete, this new interrupt request (intpm) is held pending (m = 050, 051). to avoid acknowledging this intpm interrupt request, clear the p05ifn bit of the interrupt control register. remark n = 0, 1: control of intp050 and intp051 pins
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 892 20.5 software exception a software exception is generated when the cpu ex ecutes the trap instru ction, and can always be acknowledged. 20.5.1 operation if a software exception occurs, the cpu performs the fo llowing processing, and transfe rs control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the psw.ep and psw.id bits to 1 <5> sets the handler address (00000040h or 00000050h) corre sponding to the software exception to the pc, and transfers control. the following illustrates the proce ssing of a software exception. figure 20-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 00h to 1fh.) the handler address is determined by the trap instruction?s operand (vector). if the vector is 00h to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 893 20.5.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instru ction, the cpu carries out the following pr ocessing and shifts control to the restored pc?s address. <1> loads the restored pc and psw from eipc and eipsw because the psw.ep bit is 1. <2> transfers control to the address of the restored pc and psw. the following illustrates the proce ssing of the reti instruction. figure 20-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instructi on, it is necessary to set the ep bit back to 1 and clear the np bit to 0 using the ldsr instruction imme diately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 894 20.5.3 exception status flag (ep) the ep flag is a status flag used to indi cate that exception processing is in progress. it is set when an exception occurs. the ep flag is allocated to the psw. this flag is set to 00000020h after reset. 0 np ep id sat cy ov s z psw exception processing not in progress exception processing in progress ep 0 1 exception processing status after reset: 00000020h
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 895 20.6 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instructi on takes place. in the v850e/ma3, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 20.6.1 illegal opcode the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an in struction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible that th is instruction may be assigned to an illegal opcode in th e future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the follo wing processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep, and psw.id bits to 1. <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. the following illustrates the proce ssing of the exception trap.
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 896 figure 20-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the db ret instruction. by execut ing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. the following illustrates the restore processing from an exception trap. figure 20-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 897 20.6.2 debug trap the debug trap is an exception that can be acknowledged anytime and is gener ated by execution of the dbtrap instruction. when the debug trap is generat ed, the cpu performs the following processing. (1) operation <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the psw.np, psw.ep and psw.id bits to 1. <4> sets the handler address (00000060h) corresponding to the debug trap to the pc and transfers control. the following illustrates the pr ocessing of the debug trap. figure 20-12. debug trap processing dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h debug monitor routine processing cpu processing
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 898 (2) restore recovery from a debug trap is carried out by the dbret in struction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. caution dbpc and dbpsw can be accessed duri ng the period between when the dbtrap instruction is executed and when the dbret instruction is executed. the following illustrates the restor e processing from a debug trap. figure 20-13. restore processing from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 899 20.7 multiple interrupt servicing control multiple interrupt servicing control is a process by which an interrupt request signal that is currently being serviced can be interrupted during servicing if t here is an interrupt request signal with a higher priority level, and the higher priority interrupt request is acknowledged and serviced first. if there is an interrupt request signal with a lower priority level than the interrupt r equest currently being serviced, that interrupt request signal is held pending. multiple interrupt servicing control of maskable interrupts is executed when interrupts are enabled (psw.id bit = 0). thus, to execute multiple interrupts, it is necessary to set the interrupt enabled state (id bit = 0) even in an interrupt servicing routine. if maskable interrupts are enabled or a software excepti on is generated in a maskable interrupt or software exception servicing program, it is necessary to save eipc and eipsw. this is accomplished by the following procedure. (1) acknowledgment of maskab le interrupt request si gnal in servicing program service program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ? ei instruction (interr upt acknowledgment enabled) ... ... maskable interrupt acknowledgment ... ... ? di instruction (interr upt acknowledgment disabled) ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 900 (2) generation of exception in servicing program servicing program of maskable interrupt or exception ... ... ? eipc saved to memory or register ? eipsw saved to memory or register ... ? trap instruction exception such as trap instruction acknowledged. ... ? saved value restored to eipsw ? saved value restored to eipc ? reti instruction the priority order for multiple interrupt servicing cont rol has 8 levels, from 0 to 7 for each maskable interrupt request signal (0 is the highest priority), but it can be set as desired via software. the priority order is set using the xxprn0 to xxprn2 bits of the interrupt control request register (xxlcn), provided for each maskable interrupt request signal. after system reset, an interr upt request signal is masked by the xxmkn bit and the priority order is set to level 7 by the xxprn0 to xxprn2 bits. the priority order of maskable interrupts is as follows. (high) level 0 > level 1 > level 2 > level 3 > level 4 > level 5 > level 6 > level 7 (low) interrupt servicing that has been sus pended as a result of multiple servic ing control is resumed after the servicing of the higher priority interrupt has been co mpleted and the reti instru ction has been executed. a pending interrupt request signal is acknowledged after the current interrupt servicing has been completed and the reti instructi on has been executed. caution in a non-maskable interrupt servicing routin e (time until the reti instruction is executed), maskable interrupts are susp ended and not acknowledged. remark xx: identification name of each peripheral unit (see table 20-2 ) n: peripheral unit number (see table 20-2 )
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 901 20.8 interrupt latency time the v850e/ma3 interrupt latency time (f rom interrupt request generation to start of interrupt servicing) is described below. figure 20-14. pipeline operation at inte rrupt request acknowledgment (outline) if if if id ex df wb ifx ifx ifx idx 4 system clocks if if if id int1 int2 int3 int4 internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (start instruction of interrupt servicing routine) interrupt request remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt latency time (internal system clock) external interrupt internal interrupt intpn condition minimum 4 4 + analog delay time maximum 8 8 + analog delay time the following cases are exceptions. ? in idle/software stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to on-chip peripheral i/o register remark n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137
chapter 20 interrupt/exception processing function user?s manual u16397ej3v0ud 902 20.9 periods in which cpu does not acknowledge interrupts the cpu acknowledges an interrupt wh ile an instruction is being execut ed. however, no interrupt will be acknowledged between an interrupt request non- sample instruction and the next instru ction (interrupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the command register (prcmd) ? the store, set1, not1, and clr1 inst ructions for the following registers. ? interrupt-related registers: interrupt control register (xxicn), interr upt mask registers 0 to 3 (imr0 to imr3) ? power save control register (psc) 20.10 cautions (1) caution on intwdt if the non-maskable interrupt (intwdt) is generated because wdt overflows, execute reset processing in the interrupt routine. note that the reti instruction cannot be executed at this time. (2) caution when port is used as ext ernal interrupt input pin (intpn) when a port is used as external interrupt input pins (intpn), note that the interrupts related to the timer/counter and serial interface t hat are multiplexed with the port ar e not generated (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137).
user?s manual u16397ej3v0ud 903 chapter 21 standby function 21.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available stan dby modes are listed in table 21-1. table 21-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle mode mode to stop all the operations of the internal circuit except the oscillator, csib in the slave mode, and uarta when external clock is selected software stop mode mode to stop all the operations of the in ternal circuit except csib in the slave mode and uarta when external clock is selected
chapter 21 standby function user?s manual u16397ej3v0ud 904 figure 21-1. status transition normal operation mode wait for stabilization of oscillation end of oscillation stabilization time count setting of halt mode interrupt request note 1 , reset input setting of stop mode idle mode halt mode software stop mode interrupt request note 3 , reset input interrupt request note 2 , reset signal note 4 setting of idle mode notes 1. non-maskable interrupt request signal (nmi pin input), unmasked external interrupt request note 5 , or unmasked internal interrupt request signal (csib-related interrupt request signal in the slave mode and uarta-related interrupt request signal when external clock is selected) from peripheral functions operable in idle mode. 2. non-maskable interrupt request signal (nmi pin input, non-maskable interrupt request signal (intwdt) generation by overflow) or unmas ked maskable interrupt request signal. 3. non-maskable interrupt request signal (nmi pin input), unmasked external interrupt request signal note 5 , or unmasked internal interrupt request signal (csib-related interrupt request signal in the slave mode and uarta-related interrupt request signal when external clock is selected) from peripheral functions operable in software stop mode. 4. reset pin input, reset signal (wdtres) generation by watchdog timer overflow 5. intpn (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137) when it is specified t hat the level of the intpn pin is to be detected, the software stop mode and idle mode cannot be released.
chapter 21 standby function user?s manual u16397ej3v0ud 905 21.2 control registers (1) power save control register (psc) the psc register is an 8-bit register t hat controls the standby function. the stb bit of this register is used to specify the standby mode. this re gister is a special register (see 3.4.9 special registers ). this register can be written only by a combinat ion of specific sequences. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 psc 0 nmim intm 0 0 stb 0 standby mode release enabled by nmi request standby mode release disabled by nmi request nmim 0 1 control of non-maskable interrupt request (nmi) from nmi pin note 1 standby mode release enabled by intxx request standby mode release disabled by intxx request intm 0 1 control of all maskable interrupt requests note 1 (intxx note 2 ) normal mode standby mode stb 0 1 setting operation mode note 3 after reset: 00h r/w after reset: fffff1feh < > < > < > notes 1. setting these bits is valid only in the idle/software stop mode. 2. for details, see tables 20-1 interrupt source list . 3. for the setting procedure, see 21.7 procedure for setting and restoring from idle and software stop modes . cautions 1. be sure to clear bits 0, 2, 3, 6, and 7 to ?0?. 2. to set the idle mode or software stop m ode, set the psmr.psm bit first and then set the stb bit to 1.
chapter 21 standby function user?s manual u16397ej3v0ud 906 21.3 halt mode 21.3.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock generator continues operating. only clo ck supply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the inte rnal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 21-3 shows the operation status in the halt mode. the average power consumpti on of the system can be reduced by using the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop in structions after the halt instruction. 2. if the halt instruction is executed while an unmasked interrupt request signal is being held pending, the halt mode is set but is released immediately by the pending interrupt request signal. 21.3.2 releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input, non-maskable interrupt request signal (intwdt) gener ation by overflow), an unma sked maskable interrupt reques t signal, and reset signal (reset pin input, reset signal generation by watchdog ti mer overflow (wdtres)). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-m askable interrupt request signal or unmasked maskable interrupt request the halt mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the halt mode is set in an interrupt servicing routine, however, an interrupt request si gnal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower th an or same as the interrupt request signal currently being serviced is generated, the halt mode is released, but the newly generated interrupt is not acknowledged. the interrupt request signal itself is retained. theref ore, execution starts at the next instruction after the halt instruction. (b) if an interrupt request signal with a priority higher than that of the interrupt request signal currently being serviced is issued (including a non-maskable interrupt request signal), the halt mode is released and that interrupt request signal is acknowledged. t herefore, execution branche s to the handler address. table 21-2. operation after releasing ha lt mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address unmasked maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed
chapter 21 standby function user?s manual u16397ej3v0ud 907 (2) releasing halt mode by reset pi n input or wdtres signal generation the same operation as the normal reset operation is performed. table 21-3. operation status in halt mode setting of halt mode item operation status clock generator operates system clock (f xx ) supply cpu stops operation dma operable interrupt controller operable rom correction operable tmp0 to tmp2 operable tmq0 operable tmd0 to tmd3 operable timer tmenc10 operable watchdog timer operable csib0 to csib2 operable i 2 c note operable serial interface uarta0 to uarta3 operable a/d converter operable d/a converter operable external bus interface see chapter 5 bus control function . port function retains status before halt mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set. note i 2 c bus versions (y products) only (see table 1-1 )
chapter 21 standby function user?s manual u16397ej3v0ud 908 21.4 idle mode 21.4.1 setting and operation status the idle mode is set by clearing the psmr.psm bit to 0 and setting the psc.stb bit to 1 in the normal operation mode. in the idle mode, the clock generat or continues operation but clock s upply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle mode was set are retained. the cpu and other on-chip peripheral functions st op operating. however, the on- chip peripheral functions that can operate with an exter nal clock continue operating. table 21-5 shows the operation status in the idle mode. the idle mode can reduce the power consumption more t han the halt mode because it stops the operation of the on-chip peripheral functions. the clock generator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabiliz ation time after the idle mode has be en released, in the same manner as when the halt mode is released. caution for the idle mode setting procedure, see 21. 7 procedure for setting and restoring from idle and software stop modes. 21.4.2 releasing idle mode the idle mode is released by a non-maskable interrupt request signal (nmi pin input), unmasked external interrupt request signal (intpn pin input) note , unmasked internal interrupt request signal (csib-related interrupt request signal in the slave mode and uarta-related interrupt reques t signal when external clock is selected) from the peripheral functions operable in the idle mode, or reset input (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137). after the idle mode has been released, th e normal operation mode is restored. note when it is specified that the leve l of the intpn pin is to be detected, the idle mode cannot be released. (1) releasing idle mode by non-mask able interrupt request signal (nmi pin input) or unmasked maskable interrupt request signal the idle mode is released by a non-maskable interr upt request signal (nmi pin input) or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request sign al. if the idle mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. caution when psc.intm bit = 1, the idle mode cannot be released by the unmasked maskable interrupt request signal. (a) if an interrupt request with a priority lower than or same as the interrupt request signal currently being serviced is generated, the idle mode is released, but the newly generated interrupt is not acknowledged. the interrupt request signal itself is retained. therefore, execution star ts at the next instruction after the idle instruction. (b) if an interrupt request signal with a priority higher th an that of the interrupt request signal currently being serviced is issued (including a non-maskable interrupt request signal), the idle mode is released and that interrupt request signal is acknowledged. ther efore, execution branche s to the handler address.
chapter 21 standby function user?s manual u16397ej3v0ud 909 table 21-4. operation after releasing id le mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address unmasked maskable interrupt request signal execution branches to the handler address or the next instruction is executed the next instruction is executed (2) releasing idle mode by reset pin input the same operation as the normal reset operation is performed. table 21-5. operation status in idle mode setting of idle mode item operation status clock generator operates system clock (f xx ) stops supply cpu stops operation dma stops operation interrupt controller stops operation rom correction stops operation tmp0 to tmp2 stops operation tmq0 stops operation tmd0 to tmd3 stops operation timer tmenc10 stops operation watchdog timer stops operation csib0 to csib2 operable when sckn input clock is selected as operation clock (in slave mode) (n = 0 to 2) i 2 c note stops operation serial interface uarta0 to uarta3 operable when asckn input clock is selected as operation clock (when external clock is selected) (n = 0 to 2) a/d converter stops operation d/a converter operable (retains output value before idle mode was set.) external bus interface see chapter 5 bus control function . port function retains status before idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle mode was set. note i 2 c bus versions (y products) only (see table 1-1 )
chapter 21 standby function user?s manual u16397ej3v0ud 910 21.5 software stop mode 21.5.1 setting and operation status the software stop mode is set when the psmr.psm bit is set to 1 and the psc.stb bit is set to 1 in the normal operation mode. in the software stop mode, the clock generator stops operation. clock supply to the cpu and the on-chip peripheral functions is stopped. as a result, program execution is st opped, and the conten ts of the internal ram before the software stop mode was set are retained. the cpu and other on-chip peripher al functions stop operating. however, the on-chip peripheral functions that can operate with an external clock continue operating. table 21-7 shows the operation stat us in the software stop mode. because the software stop stops operat ion of the clock generator, it reduces the power consumption to a level lower than the idle mode. if the external clock is not used, the power consumption can be minimized with only leakage current flowing. caution for the software stop mode setting procedure, see 21.7 pr ocedure for setting and restoring from idle and software stop modes. 21.5.2 releasing soft ware stop mode the software stop mode is released by a non-maskable interrupt request signal (nmi pin input), unmasked external interrupt request signal (intpn pin input) note , unmasked internal interrupt request signal (csib-related interrupt request signal in the slave mode and uarta-related interrupt request signal when external clock is selected) from the peripheral functions operable in the software stop mode, or reset pin input (n = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 11 4, 115, 124 to 126, 130 to 134, 137). after the software stop mode has been released, the no rmal operation mode is restored after the oscillation stabilization time has been secured. note when it is specified that the leve l of the intpn pin is to be detected, the software stop mode cannot be released. (1) releasing software stop mode by non-maskable in terrupt request signal (nmi pin input) or unmasked maskable interrupt request signal the software stop mode is released by a non-maskabl e interrupt request signal (nmi pin input) or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the software stop mode is set in an interrupt servicing rout ine, however, an interrupt request signal that is issued later is serviced as follows. caution when psc.intm bit = 1, the software st op mode cannot be released by the unmasked maskable interrupt request signal. (a) if an interrupt request signal with a priority lower th an or same as the interrupt request signal currently being serviced is generated, the softw are stop mode is released, but the newly generated interrupt is not acknowledged. the interrupt request signal itself is retained. theref ore, execution starts at the next instruction after the stop instruction. (b) if an interrupt request signal with a priority higher than that of the interrupt request signal currently being serviced is issued (including a non-maskable interrupt request signal), the software stop mode is released and that interrupt request signal is acknowle dged. therefore, execution branches to the handler address.
chapter 21 standby function user?s manual u16397ej3v0ud 911 table 21-6. operation after releasing softwar e stop mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal ex ecution branches to the handler address unmasked maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing oscillation stabilization time the next instruction is executed after securing oscillation stabilization time (2) releasing software stop mode by reset pin input the same operation as the normal reset operation is performed. table 21-7. operation status in software stop mode setting of software stop mode item operation status clock generator stops operation system clock (f xx ) stops supply cpu stops operation dma stops operation interrupt controller stops operation rom correction stops operation tmp0 to tmp2 stops operation tmq0 stops operation tmd0 to tmd3 stops operation timer tmenc10 stops operation watchdog timer stops operation csib0 to csib2 operable when sckn input clock is selected as operation clock (in slave mode) (n = 0 to 2) i 2 c note stops operation serial interface uarta0 to uarta3 operable when asckn input clock is selected as operation clock (when external clock is selected) (n = 0 to 2) a/d converter stops operation d/a converter operable (retains output value before software stop mode was set.) external bus interface see chapter 5 bus control function . port function retains status before software stop mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the software stop mode was set. note i 2 c bus versions (y products) only (see table 1-1 )
chapter 21 standby function user?s manual u16397ej3v0ud 912 21.6 securing oscillation stabilization time when the software stop mode is released, the oscillation st abilization time set by the osts register elapses. when releasing the software stop mode by reset pin inpu t, however, secure the oscillation stabilization time by the low-level width of the reset signal because t he oscillation stabilization time is not inserted. the timer for counting the oscillation stabilization time is shared with the watchdog timer, so oscillation stabilization time equal to the overflow time of the watchdog timer elapses. the operation performed when the software stop mode is re leased by an interrupt request signal is shown below. figure 21-2. oscillation stabilization time oscillated waveform clock generator stops oscillation stabilization time count f clk software stop mode status interrupt request caution for details of the osts register, see 7.3 (5 ) oscillation stabilization time select register (osts).
chapter 21 standby function user?s manual u16397ej3v0ud 913 21.7 procedure for setting and restoring from idle and software stop modes to set the idle mode or software stop mode, be sure to select a multiplication factor for the clock generator by using the ckc register so that the system clock (f xx ) is less than 25 mhz. to restore operation from the idle mode or software stop mode, be sure to restor e the multiplication factor to the origi nal set value by using the ckc register. (1) procedure of setting idle and software stop mode set the idle or software stop mode in the following sequence. in the following example, ?[(number)]? in the sequence corresponds to a line number. [to set] <1> prepare data to be set to the ck c.ckdiv1 and ckdiv0 bits [(1)]. <2> write the data prepared in <1 > to the prcmd register [(2)]. <3> write the data prepared in <1> to the ckc register (by using the following instructions) [(3)]. ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <4> insert 10 or more nop in structions [(4) to (13)]. <5> prepare data to be set to the psc register [(14)]. <6> write the data prepared in <5 > to the prcmd register [(15)]. <7> write the data prepared in <5> to the psc regi ster (by using the following instructions) [(16)]. ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <8> insert five or more nop instructions [(17) to (21)]. [to restore] <9> prepare data to be set to the ck c.ckdiv1 and ckdiv0 bits [(22)]. <10> write the data prepared in <9 > to the prcmd register [(23)]. <11> write the data prepared in <9> to the ckc r egister (by using the following instructions) [(24)]. ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) a description example is shown below.
chapter 21 standby function user?s manual u16397ej3v0ud 914 [example] at 80 mhz operation [to set] st.b r11, psmr[r0] ; sets psmr register. ; (r11 = 0: idle mode, r11 = 1: stop mode) (1) mov 0x01, r12 (2) st.b r12, prcmd[r0] ; writes prcmd register. (3) st.b r12, ckc[r0] ; sets ckc register (fxx = 2.5 x fx = 20 mhz). ; fxx = 25 mhz or less (4) nop ; dummy instructions (10 instructions) (5) nop (6) nop (7) nop (8) nop (9) nop (10) nop (11) nop (12) nop (13) nop (14) mov 0x02, r10 (15) st.b r10, prcmd[r0] ; writes prcmd register. (16) st.b r10, psc[r0] ; sets psc register (sets standby mode). (17) nop ; dummy instructions (5 instructions). (18) nop (19) nop (20) nop (21) nop [to restore] (22) mov 0x03, r10 (23) st.b r10, prcmd[r0] ; writes prcmd register. (24) st.b r10, ckc[r0] ; sets ckc register (fxx = 10 x fx = 80 mhz). ; sets original multiplication factor. (normal application codes follow.) cautions 1. no special sequence is n ecessary for reading sp ecial registers. 2. stop all dma transfer operations before executing this processing. 3. because the ckc and psc regist ers are special registers, it is assumed that <2> and <3>, <6> and <7>, and <10> and <11> are perfo rmed by successive store instructions. if another instruction is placed between <2> a nd <3>, <6> and<7>, and <10> and <11>, the above sequence may not be established if an interrupt is acknowledged by that instruction, causing malfunctioning. 4. the multiplication factor of the system clock (f xx ) is changed within the duration of 10 system clocks after the ckc.ckdiv1 and ckdiv0 bits have been set.
user?s manual u16397ej3v0ud 915 chapter 22 reset functions 22.1 overview ? system reset by reset pin input ? system reset (wdtres) by watchdog timer (wdt) overflow ? forced reset by on-chip debug function (dcu) and reset mask function (see chapter 24 on-chip debug function (dcu) .) 22.2 configuration reset rg main block v850e/ma3 cg rg filter block cpu core wdt remark rg: reset generator wdt: watchdog timer (see chapter 13 watchdog timer functions ) cg: clock generator (see chapter 7 clock generator )
chapter 22 reset functions user?s manual u16397ej3v0ud 916 22.3 control register (1) watchdog timer reset status register (wdres) the wdres register can be used to check whethe r the v850e/ma3 is reset by the watchdog timer (wdtres). this register is a special register and indicates the status of wdtres. this register is set only by an 8-bit units when it is written, and by an 8-bit or 1-bit units when it is read. to write data to the wdres register, a specific sequenc e using the prcmd register as a command register is necessary. if the wdres register is written in an illegal se quence, writing is invalid, the protect error bit (bit 0 of the sys register: prerr) is set to 1, and the write operation is not performed. reset input clears this register to 00h. 7 0 wdtres did not occur. wdtres occurred. wresf 0 1 wdtres detection flag wdres 6 0 5 0 4 0 3 0 2 0 1 0 <0> wresf after reset: 00h r/w address: fffff82ah set (1) condition: occurrence of reset due to overflow of watchdog timer (wdt) clear (0) condition: writing 0 to this flag by instruction or reset pin input only 0 can be written to the wresf bit. caution write 0 to the wresf bit af ter confirming that wresf bit is 1 (read) in order to avoid conflict with setting the flag. remark the wresf bit can be read/written but it can only be cleared by writing 0, 1 cannot be written to it.
chapter 22 reset functions user?s manual u16397ej3v0ud 917 22.4 operation when a low level is input to the reset pin or when th e watchdog timer overflows (wdtres), the v850e/ma3 is reset, and each hardware unit is initialized to a specific status. the reset status is released when the reset pin input goes from low to high or if the wdtres signal is automatically released. after the reset status has been released, the cpu starts program execution. when the reset status is released by reset pin input, t he oscillation stabilization time is not inserted. when inputting the reset signal with the clock generator stopped (power-on reset or reset input to release the idle or software stop mode), therefore, the oscillation stabilizati on time must be secured by the low-level width of the reset pin input. the status of each hardware unit during the reset period and after the reset status is released is shown below. hardware during reset period after reset is released clock generator (in clock-through mode) oscillation/supply continues however, the following setting is initialized. ? system clock (f xx ) is initialized to 1 f x . ? internal system clock (f clk )/cpu clock (f cpu ) is initialized to f xx . clock generator (in pll mode) oscillation/supply stops however, the following setting is initialized. ? system clock (f xx ) is initialized to 1.25 f x . ? internal system clock (f clk )/cpu clock (f cpu ) is initialized to f xx . cpu stops operation operable internal ram undefined if power-on reset or writing data to ram (by cpu or dma) conflicts with reset input (data destroyed). otherwise, re tains value immediately before reset input on-chip debug function operable on-chip peripheral i/o registers initialized to specific status on-chip peripheral functions other than above stops operation can start operation pin function see 2.2 pin status . the reset operation by reset pin input is illustrated below. figure 22-1. reset operation by reset pin input f x operation at f xx = f x 8 initialized to operation at f xx = f x 5 system clocks min. f clk reset (input) internal system reset analog delay (eliminated as noise) analog delay analog delay analog delay (eliminated as noise)
chapter 22 reset functions user?s manual u16397ej3v0ud 918 the reset operation at power on is illustrated below. figure 22-2. reset operation at power on v dd f x initialized to operation at f xx = f x analog delay time until oscillation starts 6 system clocks min. oscillation stabilization time secured f clk reset (input) internal system reset cautions 1. secure the oscillation stabilization ti me by the low-level width of the reset signal. 2. turn on power in the order of v dd (power to the internal circuitry) and ev dd (power to the external circuitry). if the power to the internal circuitry (v dd ) is outside the guaranteed operating range (2.3 to 2.7 v) in the power-on/off sequence when a volt age is applied to the power supplies for the external circuitry (ev dd , cv dd , av dd0 , and av dd1 ), the following phenomena may occur. ? a current of about 130 ma (typ.) flows into the ev dd pin. ? an undefined level is output from the following pins. tdo/tc3/p27 pin ano0/p80 pin ano1/p81 pin for details, see 26.2 power-on/off sequence.
user?s manual u16397ej3v0ud 919 chapter 23 rom correction function 23.1 overview the rom correction function is used to replace part of th e program in the mask rom or flash memory with the program of an external memory or the internal ram. by using this function, program bugs found in the mask rom or flash memory can be corrected at up to four places. figure 23-1. block diag ram of rom correction instruction address bus block replacing bug with dbtrap instruction instruction/data bus rom dbtrap instruction generation block correction address register n (coradn) correction control register (corenn bit) comparator remark n = 0 to 3
chapter 23 rom correction function user?s manual u16397ej3v0ud 920 23.2 control registers (1) correction address registers 0 to 3 (corad0 to corad3) the corad0 to corad3 registers are used to set the first address of the program to be corrected. the program can be corrected at up to four places because four coradn r egisters are provided (n = 0 to 3). these registers can be read or written in 32-bit units. if the higher 16 bits of the coradn re gister are used as the coradnh regi ster, and the lower 16 bits as the coradnl register, these registers can be read or written in 16-bit units. reset input clears these registers to 00000000h. because the rom capacity differs depending on the produ ct, set correction addresses in the following ranges. pd703131a, 703131ay, 70313 2a, 703132ay, 703136a, 703136ay (256 kb): 0000000h to 003fffeh pd703133a, 703133ay, 70313 4a, 703134ay, 70f3134a, 70f3134ay (512 kb): 000 0000h to 007fffeh fix bits 0 and 20 to 31 to 0. correction address fixed to 0 0 coradn (n = 0 to 3) after reset: 00000000h r/w address: 2019 1 0 31 corad0 fffff840h, corad0l fffff840h, corad0h fffff842h, corad1 fffff844h, corad1l fffff844h, corad1h fffff846h, corad2 fffff848h, corad2l fffff848h, corad2h fffff84ah, corad3 fffff84ch, corad3l fffff84ch, corad3h fffff84eh
chapter 23 rom correction function user?s manual u16397ej3v0ud 921 (2) correction control register (corcn) the corcn register disables or enables the correction operation at the address set to the coradn register (n = 0 to 3). each channel can be enabled or disabled by this register. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 7 0 disabled enabled corenn 0 1 enables/disables correction operation corcn 6 0 5 0 4 0 <3> coren3 <2> coren2 <1> coren1 <0> coren0 after reset: 00h r/w address: fffff880h remark n = 0 to 3 table 23-1. correspondence between corcn register bits and coradn registers corcn register bit corresponding coradn register coren3 corad3 coren2 corad2 coren1 corad1 coren0 corad0 23.3 rom correction operation and program flow <1> if the address to be corrected and the fetch address of t he internal rom match, the fetch code is replaced by the dbtrap instruction. <2> when the dbtrap instruction is execut ed, execution branches to address 00000060h. <3> software processing after branching causes the result of rom correction to be judged (the fetch address and rom correction operation are confirmed) and exec ution to branch to the correction software. <4> after the correction software has been executed, the return address is set, and return processing is started by the dbret instruction. cautions 1. when setting an address to be corrected to the coradn regist er, clear the higher bits to 0 in accordance with the capacity of the internal rom. 2. the rom correction function cannot be used to correct the data of the internal rom. it can only be used to correct instructi on codes. if rom correction is u sed to correct data, that data is replaced with the dbtrap instruction code. 3. use of rom correction is prohibited if self-programming is performed in the pd70f3134a or 70f3134ay. 4. when dma transfer is exec uted in the internal ram, do not execute instructions allocated in the internal ram.
chapter 23 rom correction function user?s manual u16397ej3v0ud 922 figure 23-2. rom correction operation and program flow reset & start fetch address = coradn? coradn = dbpc-2? corenn bit = 1? initialize microcontroller set coradn register change fetch code to dbtrap instruction branch to rom correction judgment address branch to correction code address of corresponding channel n execute fetch code read data for setting rom correction from external memory execute dbtrap instruction jump to address 00000060h execute correction code execute dbret instruction write return address to dbpc. write value of psw to dbpsw as necessary. set corcn register yes yes yes no no remarks 1. : processing by user program (software) 2. n = 0 to 3 : processing by rom correction (hardware) load program for judgment of rom correction and correction codes execute fetch code ilgop processing no
user?s manual u16397ej3v0ud 923 chapter 24 on-chip debug function (dcu) an on-chip debug unit is provided in the v850e/ma3 and realizes standalone on-chip debugging of the v850e/ma3 by connecting an n-wire type emulator. caution the debug function is supported by the v850e/m a3, but whether this function can be used or not depends on the debugger used. 24.1 function overview 24.1.1 on-chip debug unit type the on-chip debug unit incorporated in the v850e/ma3 is r cu1 (run control unit 1). the on-chip unit incorporated differs depending on the microcontroller, and also features different functions. 24.1.2 debug function (1) debug interface this interface establishes communication with the hos t machine by using the trst, tck, tms, tdi, and tdo signals, via an n-wire type emulator. the communication spec ifications of n-wire are used for this interface. it does not support a boundary scan function. (2) on-chip debug on-chip debugging can be performed by providing wiri ng and connectors for debugg ing on the target system. connect an n-wire type emulator to the emulator connector. (3) forced reset function the v850e/ma3 can be forcibly reset. (4) break reset function the cpu can be started in the debug mode immediat ely after resetting the cpu has been cleared. (5) forced break function execution of the user program can be forcibly stopped (however, the handl er of the illegal instruction code exception (first address: 00000060h) cannot be used). (6) hardware break function two common instruction fetch/access breakpoints can be used. by using the instruction breakpoint, program execution can be suspended at an arbitrary address. by using the access breakpoint, program execution can be suspended by data-accessing an arbitrary address. in addition to these two breakpoints, a software break function is available. up to four software breakpoints can be set in the internal rom area. the number of software breakpoints that can be set in the internal ram area differs depending on the debugger used.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 924 (7) debug monitor function during debugging, a memory space for debugging that differs from the user memory space is used (background monitor format). the user prog ram can be executed starting from any address. while execution of the user program is stopped, the user resources (suc h as memory and i/o) can be read or written, and the user pr ogram can be downloaded. (8) mask function the reset, wdtres, nmi, inwdt, wait, and hldrq signals can be masked. the mask functions of the debugger (id850nwc or id85 0nw) and corresponding functions of the v850e/ma3 are shown below. mask function of debugger (id850nwc, id 850nw) corresponding functions of v850e/ma3 nmi0 nmi pin input nmi1 generation of non-maskable interrupt request signal (intwdt) nmi2 stop hold hldrq pin input reset generation of reset signal (wdtres) by reset pin input or overflow of watchdog timer wait wait pin input (9) timer function the execution time of the us er program can be measured.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 925 24.1.3 rom security function (1) security id the flash memory versions of the v850e/ma3 perform authentication using a 10-byte id code to prevent the contents of the rom from being read by an unauthori zed person during on-chip debugging by the n-wire emulator. set the id code in the 10-byte internal rom area from 0000070h to 0000079h to allow the debugger perform id authentication. if the ids match, the security is released and reading rom and using the n-wire emulator are enabled. ? set the 10-byte id code to 0000070h to 0000079h. ? bit 7 of 0000079h is the n-wire emulator enable flag. (0: disable, 1: enable) ? when the n-wire emulator is star ted, the debugger requests id input. when the id code input on the debugger and the id code set in 0000070h to 0000079h match, the debugger starts. ? debugging cannot be performed if the n-wire emulator enable flag is 0, even if the id codes match. 0000079h 0000070h 0000000h security id (10 bytes) caution when the data in the fl ash memory has been deleted, all the bits are set to 0xff. therefore, id code is ffffffffffffffffffffh.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 926 (2) setting when the id code is ?112233445566778899aah? address value 0x70 0xaa 0x71 0x99 0x72 0x88 0x73 0x77 0x74 0x66 0x75 0x55 0x76 0x44 0x77 0x33 0x78 0x22 0x79 0x11 when the ca850 is used, continue usi ng the handler at address 0x60 (ilgop) to input the security code and the data of the system reserved area (00h). caution description of a link dir ective is not necessary because the handler name at address 0x60 is used. [program example] #-------------------------------------- # ilgop handler #-------------------------------------- .section "ilgop" --interrupt handler address 0x60 -- input ilgop handler code .org 0x10 -- skip handler address to 0x70 #-------------------------------------- # securityid (continue ilgop handler) #-------------------------------------- .word 0x778899aa --0-3 byte code .word 0x33445566 --4-7 byte code .hword 0x1122 --8-9 byte code
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 927 24.2 selecting on-chip debug function and port function (including alternate functions) in the v850e/ma3, pins p06, p07, p26, and p27 also function as on-chip debug pins. the on-chip debug function or port function (including the al ternate functions) can be selected by using the level of the trst pin, as shown in the table below. trst pin low-level input trst pin high-level input p06/dmarq2/intp106 tms p07/dmarq3/intp107 tck p26/tc2/intp126 tdi p27/tc3 tdo caution when the tms, tck, tdi, and tdo pins are used for the on-chip debug function, other alternate functions cannot be used.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 928 24.3 connection with n-wire type emulator 24.3.1 kel connector when the ie-v850e1-cd-nw is used, use of the following connector is recommended. part number ? 8830e-026-170s: straight type ? 8830e-026-170l: right-angle type an emulator and the connection circuit must be mounted on the target system. figure 24-1. example of connecting n-wire ty pe emulator (ie-v850e1-cd-nw (n-wire card)) host machine pcmcia card slot target system ie-v850e1-cd-nw connector for emulator 8830e-026-170s (1) pin configuration the following shows the pin conf iguration of t he emulator connector (target system side). figure 24-2. pin configuration of emulat or connector (on target system side) board edge (top view) b12 a12 b2 a2 b13 a13 b1 a1 caution design the board based on the dimensions of the connector when actually mounting the connector on the board.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 929 (2) pin functions the following table shows the pin functions of the emulator connector (on the target system side). table 24-1. emulator connector pin functions (on target system side) pin no. pin name i/o pin function a1 (reserved 1) ? (connect this pin to gnd) a2 (reserved 2) ? (connect this pin to gnd) a3 (reserved 3) ? (connect this pin to gnd) a4 (reserved 4) ? (connect this pin to gnd) a5 (reserved 5) ? (connect this pin to gnd) a6 (reserved 6) ? (connect this pin to gnd) a7 ddi output data output for debug serial interface a8 dck output clock output for debug serial interface a9 dms output transfer mode select output for debug serial interface a10 ddo input data input for debug serial interface a11 drst output dcu reset output a12 (reserved 7) ? (leave this pin open) a13 flmd0 output flash download control signal b1 gnd ? ? b2 gnd ? ? b3 gnd ? ? b4 gnd ? ? b5 gnd ? ? b6 gnd ? ? b7 gnd ? ? b8 gnd ? ? b9 gnd ? ? b10 gnd ? ? b11 port0_in ? (connect this pin to gnd) b12 port1_in ? (connect this pin to gnd) b13 v dd ? +3.3 v input (for monitoring power to target) cautions 1. the connection of pins not supported by the v850e/m a3 depends on the emulator used. 2. the pattern on the target board must satisfy the following conditions. ? keep the pattern length to within 100 mm. ? shield the clock signal with gnd. remark input/output is when viewed from the emulator side.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 930 (3) recommended circuit example the following figure shows an example of the recommend ed circuit of the emulator connector (on the target system side). figure 24-3. example of recommended emulator connector v850e/ma3 mode1 (reserved 1) (reserved 2) (reserved 3) (reserved 4) (reserved 5) (reserved 6) ddi dck dms ddo drst (reserved 7) flmd0 v dd note 3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd port0_in port1_in note 1 note 1 note 1 note 1 note 1 (open) (open) (open) note 2 +3.3 v +3.3 v a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 b13 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 tdi tck tms tdo trst kel connector (8830e-026-170s) notes 1 . keep the pattern length to within 100 mm. 2. shield the clock signal with gnd. 3. for detecting power to the target board. caution the recommended circuit example shown above assumes that a 3. 3 v interface is used.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 931 24.3.2 amp connector part number ? 2-767004-2 (mictor connector): 38-pin type a connector for the emulator and a connection ci rcuit must be provided on the target system. figure 24-4. connecting n-wire type emulator to host machine n-wire emulator target system mictor connector (plug) (amp) mictor connector (receptacle (2-767004-2)) (amp) (1) pin configuration the following shows the pin conf iguration of t he emulator connector (target system side). remark the following connector is recommended. ? 2-767004-2 (amp): 38-pin type figure 24-5. pin configuration of emulat or connector (on target system side) (top view) 1 2 37 38
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 932 (2) pin functions the following table shows the pin functions of the emulator connector (on the target system side). table 24-2. emulator connector pin functions (on target system side) pin no. pin name i/o pin function 1 gnd ? ? 2 gnd ? ? 3 dck output clock output for debug serial interface 4 v dd ? +3.3 v input (for monitoring power to target) 5 dms output transfer mode select output for debug serial interface 6 drst output dcu reset output 7 ddi output data output for debug serial interface 8 port0_out output (leave this pin open) 9 ddo input data input for debug serial interface 10 flmd0 output flash download control signal 11 (reserved 1) ? (leave this pin open) 12 port2_out output (leave this pin open) 13 (reserved 2) ? (leave this pin open) 14 port0_in input (connect this pin to gnd) 15 (reserved 3) ? (leave this pin open) 16 port1_in input (connect this pin to gnd) 17 (reserved 4) ? (connect this pin to gnd) 18 port2_in input (connect this pin to gnd) 19 (reserved 5) ? (connect this pin to gnd) 20 (reserved 14) ? (leave this pin open) 21 (reserved 6) ? (connect this pin to gnd) 22 (reserved 15) ? (connect this pin to gnd) 23 (reserved 7) ? (connect this pin to gnd) 24 (reserved 16) ? (connect this pin to gnd) 25 (reserved 8) ? (connect this pin to gnd) 26 (reserved 17) ? (connect this pin to gnd) 27 (reserved 9) ? (connect this pin to gnd) 28 (reserved 18) ? (connect this pin to gnd) 29 (reserved 10) ? (connect this pin to gnd) 30 (reserved 19) ? (connect this pin to gnd) 31 (reserved 11) ? (connect this pin to gnd) 32 (reserved 20) ? (connect this pin to gnd) 33 (reserved 12) ? (connect this pin to gnd) 34 (reserved 21) ? (connect this pin to gnd) 35 (reserved 13) ? (connect this pin to gnd) 36 (reserved 22) ? (connect this pin to gnd) 37 gnd ? ? 38 gnd ? ? remarks 1. input/output is when viewed from the emulator side. 2. cautions are given on the next page.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 933 cautions 1. the connection of pins not supported by the v850e/m a3 depends on the emulator used. 2. the pattern on the target board must satisfy the following conditions. ? lay out the pattern with the odd pi ns facing the device (v850e/ma3). ? keep the pattern length to within 100 mm. ? shield the clock signal with gnd. v850e/ma3 mictor connector (receptacle (2-767004-2)) 2 38 1 37
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 934 (3) recommended circuit example the following figure shows an example of the recommend ed circuit of the emulator connector (on the target system side). figure 24-6. example of recommended emulator connector v850e/ma3 tck tms tdi tdo trst mode1 note 2 note 1 note 1 note 1 note 1 dck dms ddi ddo (reserved 1) (reserved 2) (reserved 3) (reserved 4) (reserved 5) (reserved 6) (reserved 7) (reserved 8) (reserved 9) (reserved 10) (reserved 11) (reserved 12) (reserved 13) gnd gnd v dd note 3 drst port0_out flmd0 port2_out port0_in port1_in port2_in (reserved 14) (reserved 15) (reserved 16) (reserved 17) (reserved 18) (reserved 19) (reserved 20) (reserved 21) (reserved 22) gnd (open) (open) (open) (open) note 1 +3.3 v +3.3 v 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 1, 37 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 2, 38 ground bus mictor connector (receptacle) 2-767004-2 (open) notes 1. keep the pattern length to within 100 mm. 2. shield the tck signal by gnd. 3. for detecting power to the target board caution the recommended circuit example shown above assumes that a 3. 3 v interface is used.
chapter 24 on-chip debug function (dcu) user?s manual u16397ej3v0ud 935 24.4 cautions (1) the flash memory of the device used in debugging is rewritten during debugging, so the number of flash memory rewrites cannot be guaranteed. therefore, do not use the device used in debugging for a mass production product. (2) even if reset is masked by using the mask function, the i/o buffers (port pins, etc.) are set to the reset state when the reset signal is input. (3) the software breakpoint set in the internal rom is realiz ed by the rom correction function, and therefore, it is temporarily disabled when the target is reset or when reset is caused by watchdog timer overflow (wdtres). the breakpoint is enabled again once a break has occurr ed because of a hardware break or forced break, but no software break occurs until then. (4) reset signal input during a break is masked. (5) the rom correction func tion cannot be emulated.
user?s manual u16397ej3v0ud 936 chapter 25 flash memory the following products are the flash memory versions of the v850e/ma3. caution there are differences in noi se immunity and noise radiation be tween the flash memory and mask rom versions. when preproducing an applicatio n set with the flash memory version and then mass producing it with the mask rom version, be sure to c onduct sufficient evaluations on the commercial samples (cs) (not engineering samples (es)) of the mask rom versions. for the electrical specifications related to the flash memory rewriting, see chapter 26 electrical specifications. ? pd70f3134a, 70f3134ay: products with 512 kb flash memory writing to flash memory can be performed with memory m ounted on the target system (on board). a dedicated flash programmer is connected to t he target system to perform writing. the following can be considered as the development env ironment and the applications using flash memory. ? software can be changed after the v850e/ma3 is solder-mounted on the target system. ? small scale production of various models is made easier by differentiating software. ? data adjustment in starting mass production is made easier. 25.1 features ? all block batch erase, or erase in bl ock units (block 0: 64 kb, block 1: 448 kb) ? communication via serial interface from the dedicated flash programmer ? erase/write voltage: v dd = 2.5 v ? on-board programming 25.2 writing with flash programmer writing can be performed either on-board or off-board by the dedicated flash programmer. (1) on-board programming the contents of the flash memory are rewritten after t he v850e/ma3 is mounted on the target system. mount connectors, etc., on the target system (recommended targ et connector: 7616-5002sc (sumitomo 3m ltd.)) to connect the dedicated flash programmer. (2) off-board programming writing to flash memory is performed by the dedicated program adapter (fa series), etc., before mounting the v850e/ma3 on the target system. remarks 1. the fa series is a product of na ito densei machida mfg. co., ltd. 2. when the flash memory is written with a dedicated flash programmer, the operation is always performed at a frequency multiplied by 10 in the pll mode. 3. when the flash memory is written with power s upplied from the dedicated flash programmer to the v850e/ma3, be sure to input 4 mhz frequency to the x1 pin. if power is supplied from an external source, i nput a frequency in the range of 4 mhz to 8 mhz to the x1 pin.
chapter 25 flash memory user?s manual u16397ej3v0ud 937 table 25-1. wiring of v850e/ma3 fl ash writing adapte r (fa-144gj-uen-a) flash programmer (pg-fp4) connection pin csib0 + hs used csib0 used uarta0 used signal name i/o note 1 pin function name of fa board pin pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal si so0 55 so0 55 txd0 55 so/txd output transmit signal so si0 54 si0 54 rxd0 54 sck output transfer clock sck sck0 53 sck0 53 not needed not needed clk output clock to v850e/ma3 clkout x1 58 x1 58 x1 58 /reset output reset signal /reset reset 66 reset 66 reset 66 flmd0 output write mode setting flmd0 mode1 65 mode1 65 mode1 65 flmd1 output write mode setting flmd1 mode0 or unused note 2 64 mode0 or unused note 2 64 mode0 or unused note 2 64 hs input handshake signal for csi0 + hs reserve/ hs pcm0 91 not needed not needed not needed not needed ev dd 8, 37, 98, 112, 134 ev dd 8, 37, 98, 112, 134 ev dd 8, 37, 98, 112, 134 cv dd 56 cv dd 56 cv dd 56 av dd0 72 av dd0 72 av dd0 72 vdd ? vdd voltage generation/ voltage monitor vdd av dd1 67 av dd1 67 av dd1 67 vdd2 ? write voltage vdd2 v dd 23, 62, 81, 124 v dd 23, 62, 81, 124 v dd 23, 62, 81, 124 v ss 24, 63, 82, 125 v ss 24, 63, 82, 125 v ss 24, 63, 82, 125 ev ss 9, 38, 99, 113, 135 ev ss 9, 38, 99, 113, 135 ev ss 9, 38, 99, 113, 135 cv ss 59 cv ss 59 cv ss 59 av ss0 71 av ss0 71 av ss0 71 gnd ? ground gnd av ss1 70 av ss1 70 av ss1 70 notes 1. input/output is when viewed from t he flash programmer (pg-fp4) side. 2. when unused, be sure to connect the mode0 pin to v ss via a resistor on the board side.
chapter 25 flash memory user?s manual u16397ej3v0ud 938 figure 25-1. wiring example of v850e/ma3 flash writing adapter (fa-144gj-uen-a) (1/2) pd70f3134a si so sck /reset v pp reserve/hs clkout vdd2 vdd gnd gnd vdd vdd2 gnd vdd vdd2 vdd2 vdd gnd connect to vdd. connect to vdd2. connect to gnd. 109 113 112 81 91 99 73 98 82 108 23 9 1 8 24 36 55 59 63 61 note 67 65 53 37 56 58 66 64 62 72 70 54 38 134 144 124 125 135 71 rfu-3 rfu-2 vde flmd1 flmd0 rfu-1
chapter 25 flash memory user?s manual u16397ej3v0ud 939 figure 25-1. wiring example of v850e/ma3 flash writing adapter (fa-144gj-uen-a) (2/2) note the psel pin must be fixed to the high level or lo w level, depending on the frequency in put to the x1 pin. input level of psel pin clock frequency input to x1 pin l 4.0 to 5.5 mhz h 5.5 to 8.0 mhz remarks 1. process the pins not shown above in the sa me manner as when they are not used (see 2.3 pin i/o circuits and recommende d connection of unused pins ). to connect a pin to ev dd or ev ss via resistor, using a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is designed for a 144-pin plastic lqfp package for single-power flash memory. 3. this figure shows the wiring of csib0 supporting handshaking. 4. to write the flash memory with a flash prog rammer, the operation is always performed at a frequency multiplied by 10 in the pll mode. 5. when the flash memory is written with power s upplied from the flash programmer (pg-fp4) to the v850e/ma3, be sure to set the frequency input to the x1 pin to 4 mhz. if supplying power from an external source, input a frequency in the range of 4 mhz to 8 mhz to the x1 pin.
chapter 25 flash memory user?s manual u16397ej3v0ud 940 table 25-2. wiring of v850e/ma3 fl ash writing adapter (fa-161f1-en4-a) flash programmer (pg-fp4) connection pin csib0 + hs used csib0 used uarta0 used signal name i/o note 1 pin function name of fa board pin pin name pin no. pin name pin no. pin name pin no. si/rxd input receive signal si so0 l8 so0 l8 txd0 l8 so/txd output transmit signal so si0 p7 si0 p7 rxd0 p7 sck output transfer clock sck sck0 n7 sck0 n7 not needed not needed clk output clock to v850e/ma3 clkout x1 p10 x1 p10 x1 p10 /reset output reset signal /reset reset p12 reset p12 reset p12 flmd0 output write mode setting flmd0 mode1 m10 mode1 m10 mode1 m10 flmd1 output write mode setting flmd1 mode0 or unused note 2 l9 mode0 or unused note 2 l9 mode0 or unused note 2 l9 hs input handshake signal for csi0 + hs reserve /h s pcm0 g11 not needed not needed not needed not needed ev dd a12, c6, f4, f12, p1 ev dd a12, c6, f4, f12, p1 ev dd a12, c6, f4, f12, p1 cv dd p9 cv dd p9 cv dd p9 av dd0 l10 av dd0 l10 av dd0 l10 vdd ? vdd voltage generation/ voltage monitor vdd av dd1 n13 av dd1 n13 av dd1 n13 vdd2 ? write voltage vdd2 v dd c8, j1, k14, m8 v dd c8, j1, k14, m8 v dd c8, j1, k14, m8 v ss b8, j4, k13, n8 v ss b8, j4, k13, n8 v ss b8, j4, k13, n8 ev ss a1, a5, b1, b5, b14, c1, c11, c14, d1, d14, e14, l1, m1, n1, p2, p5 ev ss a1, a5, b1, b5, b14, c1, c11, c14, d1, d14, e14, l1, m1, n1, p2, p5 ev ss a1, a5, b1, b5, b14, c1, c11, c14, d1, d14, e14, l1, m1, n1, p2, p5 cv ss n10 cv ss n10 cv ss n10 av ss0 m11 av ss0 m11 av ss0 m11 gnd ? ground gnd av ss1 n12 av ss1 n12 av ss1 n12 notes 1. input/output is when viewed from t he flash programmer (pg-fp4) side. 2. when unused, be sure to connect the mode0 pin to ev ss via a resistor on the board side. caution the clock cannot be supplied from the clk pin of the flash programmer. provide an oscillator on the board to supply the clock.
chapter 25 flash memory user?s manual u16397ej3v0ud 941 figure 25-2. wiring example of v850e/ma3 flash writing adapter (fa-161f1-en4-a) (1/2) pd70f3134a si so sck /reset v pp reserve/hs clkout vdd2 vdd gnd gnd vdd vdd2 gnd vdd vdd2 vdd2 vdd gnd leave open. connect to vdd. connect to vdd2. connect to gnd. b14 c14 a14 a12 c11 a10 c8 c6 e14 f12 k14 n12 n14 m14 p14 p12 k13 g11 e11 n13 p11 m11 a5 e5 a1 f4 j4 b1 c1 d1 p1 l9 p10 p9 l1 n1 m1 p5 p2 p7 p8 note m8 m10 j1 d14 b8 b5 n10 l10 l8 n8 n7 rfu-3 rfu-2 vde flmd1 flmd0 rfu-1 a1
chapter 25 flash memory user?s manual u16397ej3v0ud 942 figure 25-2. wiring example of v850e/ma3 flash writing adapter (fa-161f1-en4-a) (2/2) note the psel pin must be fixed to the high level or lo w level, depending on the frequency in put to the x1 pin. input level of psel pin clock frequency input to x1 pin l 4.0 to 5.5 mhz h 5.5 to 8.0 mhz remarks 1. process the pins not shown above in the sa me manner as when they are not used (see 2.3 pin i/o circuits and recommende d connection of unused pins ). to connect a pin to ev dd or ev ss via a resistor, using a resistor of 1 k ? to 10 k ? is recommended. 2. this adapter is designed for a 161-pin plastic fbga package for single-power flash memory. 3. this figure shows the wiring of csib0 supporting handshaking. 4. to write the flash memory with a flash prog rammer, the operation is always performed at a frequency multiplied by 10 in the pll mode. 5. when the flash memory is written with power s upplied from the flash programmer (pg-fp4) to the v850e/ma3, be sure to set the frequency input to the x1 pin to 4 mhz. if supplying power from an external source, input a frequency in the range of 4 mhz to 8 mhz to the x1 pin.
chapter 25 flash memory user?s manual u16397ej3v0ud 943 25.3 programming environment the following shows the environment required for writi ng programs to the flash memory of the v850e/ma3. figure 25-3. environment required fo r writing program to flash memory rs-232c dedicated flash programmer v850e/ma3 reset uarta0/csib0 host machine pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x xx yy y xxxxx xxxxxx xxxx x x xx y y y y statve flmd0 flmd1 v dd v dd2 gnd mode1 mode0 ev dd v dd ev ss usb a host machine is required for controlling the dedicated flash programmer. uarta0 or csib0 is used for the interface between the dedicated flash programmer and the v850e/ma3 to perform writing, erasing, etc. a dedicated program adapter (fa series) is required for off-board writing.
chapter 25 flash memory user?s manual u16397ej3v0ud 944 25.4 communication mode communication between the dedicated flash programmer and the v850e/ma3 is performed via serial communication using uarta0 or csib0. remark the recommended target connector is as follows. ? 7616-5002sc (sumitomo 3m ltd.) the following figure outlines the connector (w hen viewed from the connector insertion side). figure 25-4. target connector outline (viewed from connector insertion side) 1 2 15 16 (1) uarta0 transfer rate: 9,600 to 153,600 bps (lsb first) table 25-3. wiring correspondence between dedicated flash programmer and v850e/ma3 v850e/ma3 pin no. pin no. dedicated flash programmer (pg-fp4) i/o (pg-fp4 side) pin name gj f1 1 gnd ? ev ss 9, 38, 99, 113, 135 note 2 reset output reset 66 p12 3 si/rxd input txd0 55 l8 4 v dd ? ev dd 8, 37, 98, 112, 134 a12, c6, f4, f12, p1 5 so/txd output rxd0 54 p7 6 v pp nc ? ? 7 sck nc ? ? 8 h/s nc ? ? 9 clk output x1 58 p10 10 vde nc ? ? 11 v dd2 ? v dd 23, 62, 81, 124 c8, j1, k14, m8 12 flmd1 output mode0 64 l9 13 rfu-1 nc ? ? 14 flmd0 output mode1 65 m10 15 not used nc ? ? 16 not used nc ? ? note a1, a5, b1, b5, b14, c1, c11, c14, d1, d14, e14, l1, m1, n1, p2, p5 remark nc: no connection gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 25 flash memory user?s manual u16397ej3v0ud 945 (2) csib0 transfer rate: 2.4 khz to 2,500 khz (msb first) table 25-4. wiring correspondence between dedicated flash programmer and v850e/ma3 v850e/ma3 pin no. pin no. dedicated flash programmer (pg-fp4) i/o (pg-fp4 side) pin name gj f1 1 gnd ? ev ss 9, 38, 99, 113, 135 note 2 reset output reset 66 p12 3 si/rxd input so0 55 l8 4 v dd ? ev dd 8, 37, 98, 112, 134 a12, c6, f4, f12, p1 5 so/txd output si0 54 p7 6 v pp nc ? ? 7 sck output sck0 53 n7 8 h/s nc ? ? 9 clk output x1 58 p10 10 vde nc ? ? 11 v dd2 ? v dd 23, 62, 81, 124 c8, j1, k14, m8 12 flmd1 output mode0 64 l9 13 rfu-1 nc ? ? 14 flmd0 output mode1 65 m10 15 not used nc ? ? 16 not used nc ? ? note a1, a5, b1, b5, b14, c1, c11, c14, d1, d14, e14, l1, m1, n1, p2, p5 remark nc: no connection gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 25 flash memory user?s manual u16397ej3v0ud 946 (3) csib0 + hs transfer rate: 2.4 khz to 2,500 khz (msb first) table 25-5. wiring correspondence between dedicated flash programmer and v850e/ma3 v850e/ma3 pin no. pin no. dedicated flash programmer (pg-fp4) i/o (pg-fp4 side) pin name gj f1 1 gnd ? ev ss 9, 38, 99, 113, 135 note 2 reset output reset 66 p12 3 si/rxd input so0 55 l8 4 v dd ? ev dd 8, 37, 98, 112, 134 a12, c6, f4, f12, p1 5 so/txd output si0 54 p7 6 v pp nc ? ? 7 sck output sck0 53 n7 8 h/s input pcm0 91 g11 9 clk output x1 58 p10 10 vde nc ? ? 11 v dd2 ? v dd 23, 62, 81, 124 c8, j1, k14, m8 12 flmd1 output mode0 64 l9 13 rfu-1 nc ? ? 14 flmd0 output mode1 65 m10 15 not used nc ? ? 16 not used nc ? ? note a1, a5, b1, b5, b14, c1, c11, c14, d1, d14, e14, l1, m1, n1, p2, p5 remark nc: no connection gj: 144-pin plastic lqfp (fine pitch) (20 20) f1: 161-pin plastic fbga (13 13)
chapter 25 flash memory user?s manual u16397ej3v0ud 947 25.5 pin connection when performing on-board writing, install a connector on the target system (recommended target connector: 7616- 5002sc (sumitomo 3m ltd.)) to connect the dedicated flash pr ogrammer. also, design a function to switch from the normal operation mode (single-chip mode) to the flash memory programming mode. in the flash memory programming mode, all the pins not used for flash memory programming enter the same status as they were immediately after reset. therefor e, because all the ports becom e output high-impedance, pin connection is required when the external device do es not acknowledge the output high-impedance status. 25.5.1 mode1 pin in the normal operation mode, 0 v is input to the mode 1 pin. in the flash memory programming mode, the mode1 pin becomes high level. the following shows an example of the connec tion of the mode1 pin. figure 25-5. example of mode1 pin connection v850e/ma3 mode1 pull-down resistor (r flmd0 ) dedicated flash programmer connection pin flmd0
chapter 25 flash memory user?s manual u16397ej3v0ud 948 25.5.2 serial interface pins the following shows the pins used by each serial interface. table 25-6. pins used by serial interface serial interface pins used uarta0 txd0, rxd0 csib0 so0, si0, sck0 csib0 + hs so0, si0, sck0, pcm0 when connecting a dedicated flash programmer to a serial interface pin that is connected to other devices on- board, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc. (1) conflict of signals when connecting a dedicated flash programmer (output) to a serial interface pin (input) that is connected to another device (output), a conflic t of signals occurs. to avoid the conf lict of signals, isolate the connection to the other device or set the other dev ice to the output high-impedance status. figure 25-6. conflict of signals (serial interface input pin) v850e/ma3 input pin output pin other device dedicated flash programmer connection pin conflict of signals in the flash memory programming mode, the signal that the dedicated flash programmer outputs conflicts with signals the other device outputs. therefore, isolate the signals on the other device side.
chapter 25 flash memory user?s manual u16397ej3v0ud 949 (2) malfunction of other device when connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) connected to another device (input), t he signal output to the other device may cause the device to malfunction. to avoid this, isolate the connection to the other device. figure 25-7. malfunction of other device v850e/ma3 output pin input pin other device dedicated flash programmer connection pin in the flash memory programming mode, if the signal the v850e/ma3 outputs affects the other device, isolate the signal on the other device side. v850e/ma3 input pin input pin other device dedicated flash programmer connection pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side.
chapter 25 flash memory user?s manual u16397ej3v0ud 950 25.5.3 reset pin when connecting the reset signals of the dedicated flash programmer to the reset pin, which is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signal s, isolate the connection to the reset signal generator. when the reset signal is input from the user system in flash memory programming mode, the programming operations will not be performed correct ly. therefore, do not input signals other than the reset signal from the dedicated flash programmer. figure 25-8. conflict of signals (reset pin) v850e/ma3 reset output pin reset signal generator dedicated flash programmer connection pin conflict of signals in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side.
chapter 25 flash memory user?s manual u16397ej3v0ud 951 connect the reset signal of the dedicated flash programme r to the reset signal of the v850e/ma3 at the location where the two reset signals are the same. figure 25-9. example of reset pin connection (a) connection example 1 ev dd = 3.3 v ev dd = 3.3 v v850e/ma3 reset reset signal of dedicated flash programmer (b) connection example 2 ev dd = 3.3 v v850e/ma3 reset reset signal of dedicated flash programmer 25.5.4 nmi pin do not change the signal input to the nmi pin in flash me mory programming mode. if it is changed in flash memory programming mode, programming may not be performed correctly. 25.5.5 mode0, mode1 pins if mode0 is set as a low-level input and mode1 is set as a high-level input, when reset is released, these pins change to the flash memory programming mode.
chapter 25 flash memory user?s manual u16397ej3v0ud 952 25.5.6 port pins when the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer become output high-impedance. these pins must be connected according to the recommended connection of unused pins (see 2.3 pin i/o circuits and recommended connection of unused pins ). if a problem such as prohibition of output high-impe dance state occurs in the external device connected to the port, connect the port to v dd or v ss via a resistor. 25.5.7 other signal pins connect x1 and x2 in the same status as in the normal operation mode. 25.5.8 power supply supply the same power (v dd , v ss , av dd0 , av ss0 , av dd1 , av ss1 , cv dd , cv ss , ev dd , and ev ss ) as in normal operation mode. connect v dd , gnd, and v dd2 of the dedicated flash programmer to ev dd , ev ss , and v dd . (v dd and v dd2 of the dedicated flash programmer are provid ed with a power supply monitoring function.) 25.6 programming method 25.6.1 flash memory control the following shows the procedure for manipulating the flash memory. figure 25-10. flash memory operation flow start switch to flash memory programming mode reset release select communication mode manipulate flash memory end? end no yes mode1 = high level input mode1 pulse input
chapter 25 flash memory user?s manual u16397ej3v0ud 953 25.6.2 flash memory programming mode when rewriting the contents of flash memory using the dedicated flash pr ogrammer, set the v850e/ma3 to the flash memory programming mode. to switch to this m ode, set the mode0 and mode1 pins before releasing reset. when performing on-board writing, swit ch modes using a jumper, etc. ? mode0: low-level input ? mode1: high-level input figure 25-11. flash memory programming mode oscillation stabilization time pulse input note mode0 mode1 0 v l reset ... n 12 the levels of mode0 and mode1 are latched at the rising edge of the reset signal and the operation mode is determined. note for the number of pulses, see table 25-7 . 25.6.3 selection of communication mode in the v850e/ma3, the communication mode is selected by inputting pulses (11 pulses max.) to the mode1 pin after switching to the flash memory programming mode. the mode1 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 25-7. list of communication modes mode1 pulses communication mode remarks 0 uarta0 transfer rate: 9,600 bps (at reset), lsb first 8 csib0 11 csib0 + hs v850e/ma3 performs slave operation, msb first other rfu (reserved) setting prohibited
chapter 25 flash memory user?s manual u16397ej3v0ud 954 25.6.4 communication commands the v850e/ma3 communicates with the dedicated flash programmer by means of commands. a command sent from the dedicated flash programmer to the v850e/ma3 is ca lled the ?command?. the response signal sent from the v850e/ma3 to the dedicated flash prog rammer is called the ?response command?. figure 25-12. communication command v850e/ma3 dedicated flash programmer command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y s tat v e the following shows the commands for controlling the flas h memory of the v850e/ma3. all of these commands are issued from the dedicated flash programmer, and the v850e/ma3 performs the various processing corresponding to the commands. table 25-8. flash memory control command category command name function verify verify command compares the contents of the entire memory and the input data. chip erase command erases the contents of the entire memory. erase block erase command erases the contents of the specified block. blank check block blan k check command checks the erase state of the specified block. data write write command writes data by the specification of the write address and the number of bytes to be written, and executes verify check. status command acquires the status of operations. oscillating frequency setting command sets the oscillation frequency. baud rate setting command sets the baud rate when uarta0 is used silicon signature command reads outs the silicon signature information. version acquisition command read outs the device version information. check sum command read outs the data check sum value of the specified block. system setting and control reset command escapes from each state. the v850e/ma3 sends back response commands for the comm ands issued from the dedicated flash programmer. the following shows the response commands the v850e/ma3 sends out. table 25-9. response commands response command name function ack (acknowledge) acknowledges command/data, etc. nak (not acknowledge) acknowledges illegal command/data, etc.
chapter 25 flash memory user?s manual u16397ej3v0ud 955 25.6.5 turning off power when all the communication commands have been executed or to stop processing during rewrite processing, make the reset pin low and then turn off power (v dd , ev dd ) as shown below. figure 25-13. turning off power v dd , ev dd reset reset input turn off power
user?s manual u16397ej3v0ud 956 chapter 26 electrical specifications 26.1 normal operation mode absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v dd pin ? 0.5 to +3.6 v v ss v ss pin ? 0.5 to +0.5 v ev dd ev dd pin ? 0.5 to +4.6 v ev ss ev ss pin ? 0.5 to +0.5 v cv dd cv dd pin ? 0.5 to +4.6 v cv ss cv ss pin ? 0.5 to +0.5 v av dd0 av dd0 pin, ev dd ? 0.5 v < av dd0 < ev dd + 0.5 v ? 0.5 to +4.6 v av ss0 av ss0 pin ? 0.5 to +0.5 v av dd1 av dd1 pin, ev dd ? 0.5 v < av dd1 < ev dd + 0.5 v ? 0.5 to +4.6 v supply voltage av ss1 av ss1 pin ? 0.5 to +0.5 v input voltage v i excluding x1 pin, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v ? 0.5 to ev dd + 0.5 note v clock input voltage v k x1 pin, v dd = 2.5 v 0.2 v, cv dd = 3.3 v 0.3 v ? 0.5 to cv dd + 0.5 note v per pin 4.0 ma output current, low i ol total of all pins 100 ma per pin ? 4.0 ma output current, high i oh total of all pins ? 100 ma output voltage v o v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v ? 0.5 to ev dd + 0.5 note v analog input voltage v ian p70/ani0 to p77/ani7 pins, v dd = 2.5 v 0.2 v, av dd0 = 3.3 v 0.3 v ? 0.5 to av dd0 + 0.5 note v analog output voltage v oan p80/ano0, p81/ano1, v dd = 2.5 v 0.2 v, av dd1 = 3.3 v 0.3 v ? 0.5 to av dd1 + 0.5 note v operating ambient temperature t a ? 40 to +85 c 144-pin plastic lqfp version ? 55 to +150 c storage temperature t stg 161-pin plastic fbga version ? 40 to +125 c note be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage. cautions 1. do not directly connect the output (or i/ o) pins of ic products to each other, or to v dd , ev dd , and gnd. open-drain pins or open-collector pins, howe ver, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedan ce state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the absolu te maximum ratings are not exceeded. the ratings and conditions indicated for dc ch aracteristics and ac characteristics represent the quality assurance range during normal operation.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 957 capacitance (t a = 25 c, v dd = v ss = ev dd = ev ss = cv dd = cv ss = av dd0 = av ss0 = av dd1 = av ss1 = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o fc = 1 mhz unmeasured pins returned to 0 v. 15 pf operating conditions operation mode system clock frequency (f xx ) operating ambient temperature (t a ) supply voltage (v dd ) clock through mode 5 to 25 mhz pll mode 5 to 80 mhz ? 40 to +85 c v dd = 2.5 v 0.2 v ev dd = 3.3 v 0.3 v cv dd = 3.3 v 0.3 v av dd0 = 3.3 v 0.3 v av dd1 = 3.3 v 0.3 v
chapter 26 electrical specifications user?s manual u16397ej3v0ud 958 recommended oscillator (a) ceramic resonator (i) kyocera (t a = ? 40 to +85 c) x1 x2 c2 c1 recommended circuit constant oscillation voltage range type part number oscillation frequency f x (mhz) c1 c2 min. (v) max. (v) oscillation stabilization time (max.) t os (ms) pbrc4.00hr 4.00 on chip (30 pf) on chip (30 pf) 3.0 3.6 0.04 pbrc5.00hr 5.00 on chip (30 pf) on chip (30 pf) 3.0 3.6 0.02 pbrc6.60hr 6.60 on chip (30 pf) on chip (30 pf) 3.0 3.6 0.03 surface mounting pbrc8.00hr 8.00 on chip (30 pf) on chip (30 pf) 3.0 3.6 0.03 cautions 1. keep the oscillator as clo se to the x1 and x2 pins as possible. 2. do not route other signal lines thr ough the area enclosed by broken lines. 3. these oscillator constants are reference values based on evaluation under a specific environment by the resonator manufacturer. when optimization of the oscillator charact eristics on the actual app lication is necessary, request evaluation on the mounting circuit from the resonator manufacturer. the oscillation voltage and oscilla tion frequency indicate only o scillator characteristics, therefore use the v850e/ma3 within the dc ch aracteristics and ac characteristics for internal operation conditions. (b) external clock open external clock high-speed cmos inverter x2 x1 cautions 1. keep the high-speed cmos as close to the x1 pin as possible. 2. sufficiently evaluate the matching of th e v850e/ma3 and high-speed cmos inverter.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 959 dc characteristics (t a = ? 40 to +85 c, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v, v ss = ev ss = cv ss = av ss0 = av ss1 = 0 v) (1/2) parameter symbol conditions min. typ. max. unit pins other than notes 1, 2, 3, 4, 5 2.0 3.6 v note 1 0.8ev dd 3.6 v notes 3, 5 0.7ev dd 3.6 v note 2 0.7av dd0 3.6 v input voltage, high v ih note 4 0.7av dd1 3.6 v pins other than notes 1, 2, 3, 4, 5 0 0.8 v note 1 0 0.2ev dd v notes 3, 5 0 0.3ev dd v note 2 0 0.3av dd0 v input voltage, low v il note 4 0 0.3av dd1 v clock input voltage, high v xh x1 pin 0.7cv dd cv dd v clock input voltage, low v xl x1 pin 0 0.3cv dd v v t + note 1 , falling edge 2.0 v shumitt-triggered input threshold voltage v t ? note 1 , falling edge 1.3 v i oh = ? 1.0 ma ev dd ? 1.0 v output voltage, high v oh i oh = ? 100 a ev dd ? 0.5 v output voltage, low v ol i ol = 3 ma 0.4 v input leakage current, high i lih v i = ev dd , pins other than notes 2, 4 10 a input leakage current, low i lil v i = 0 v, pins other than notes 2, 4 ? 10 a output leakage current, high i loh v o = ev dd 10 a output leakage current, low i lol v o = 0 v ? 10 a analog pin input leakage current i lwasn notes 2, 4 10 a notes 1. p00, p01, p04 to p07, p10 to p15, p20 to p22, p24 to p26, p30 to p 34, p37, p41, p42, p44, p45, p50, p51, trst, reset, cksel, psel, mode0, mode1 pins and their alternate-function pins. however, these pins do not have hysteresis characteristics in port mode. 2. p70 to p77 pins and their alternate-function pins. 3. p27 pin and its alternate-function pins. 4. p80, p81 pins and their alternate-function pins. 5. pcm1, pcd1 pins and their alternate-function pins. remark the typ. value is a reference value at t a = 25 c, v dd = 2.5 v, ev dd = 3.3 v. current flowing through the pull-up resistor is not included.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 960 dc characteristics (t a = ? 40 to +85 c, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v, v ss = ev ss = cv ss = av ss0 = av ss1 = 0 v) (2/2) parameter symbol conditions min. typ. max. unit mask rom versions 1.25 f xx + 20 1.5 f xx + 60 ma i dd1 v dd pin flash memory versions 2.25 f xx + 50 3.2 f xx + 94 ma in normal operation mode i edd1 ev dd + cv dd pins 0.9 f xx + 5 0.95 f xx + 24 ma mask rom versions 1.1 f xx + 24 1.2 f xx + 44 ma i dd2 v dd pin flash memory versions 1.1 f xx + 30 1.2 f xx + 54 ma in halt mode i edd2 ev dd + cv dd pins 0.65 f xx + 3 0.7 f xx + 24 ma mask rom versions 10 20 ma i dd3 v dd pin flash memory versions 18 30 ma in idle mode i edd3 ev dd + cv dd pins 0.35 3 ma i dd4 v dd pin 850 a supply current in stop mode i edd4 ev dd + cv dd pins 50 a remarks 1. the typ. value is a reference value at t a = 25 c, v dd = 2.5 v, ev dd = 3.3 v. current flowing through the pull-up resistor is not included. 2. f xx : system clock frequency (mhz)
chapter 26 electrical specifications user?s manual u16397ej3v0ud 961 data retention characteristics (t a = ? 40 to +85 c, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v, v ss = ev ss = cv ss = av ss0 = av ss1 = 0 v) parameter symbol conditions min. typ. max. unit v dddr stop mode, v dd = v dddr 1.8 2.7 v data retention voltage ev dddr stop mode, ev dd = cv dd = av dd0 = av dd1 = ev dddr v dddr 3.6 v v dd pin 850 a data retention current i dddr v dd = v dddr ev dd + cv dd pins 50 a supply voltage rise time t rvd 200 s supply voltage fall time t fvd 200 s supply voltage retention time (for stop mode setting) t hvd 0 ms stop mode release signal input time t drel 0 ns data retention input voltage, high v ihdr all input pins 0.8ev dddr ev dddr v data retention input voltage, low v ildr all input pins 0 0.2ev dddr v caution shifting to stop mode and restoring from stop mode must be performed within the rated operating range. t drel t hvd t fvd t rvd stop mode release signal input stop mode setting v dddr operating voltage lower limit e dddr ev dd /cv dd /av dd0 /av dd1 operating voltage lower limit v ihdr v ihdr v ildr reset (input) stop mode release interrupt (nmi, etc.) (input) (released by falling edge) stop mode release interrupt (nmi etc.) (input) (released by rising edge) v dd
chapter 26 electrical specifications user?s manual u16397ej3v0ud 962 ac characteristics (t a = ? 40 to +85 c, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v, v ss = ev ss = cv ss = av ss0 = av ss1 = 0 v, output pin load capacitance: c l = 50 pf) ac test input measurement points (a) p00, p01, p04 to p07, p10 to p15, p20 to p22, p24 to p26, p30 to p34, p37, p41, p42, p44, p45, p50, p51, trst, reset, cksel, psel, mode0, mode1 pins and their alternate-function pins. 0.8ev dd 0.2ev dd 0.8ev dd 0.2ev dd input signal ev dd 0 v measurement points (b) p27, p70 to p77, p80, p81, pcm1, pcd0 , x1 pins and their al ternate-function pins. 0.7ev dd 0.3ev dd 0.7ev dd 0.3ev dd input signal ev dd 0 v measurement points remark ev dd should be read as av dd0 when the a/d input pin is used and as av dd1 when the d/a port pin is used.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 963 ac test output measurement point (a) p00, p01, p04 to p07, p10 to p15, p20 to p22, p24 to p26, p30 to p34, p37, p40 to p45, p50, p51, trst, reset, cksel, psel, mode0, mode1 pins and their alternate-function pins 0.8ev dd 0.2ev dd 0.8ev dd 0.2ev dd output signal measurement points (b) p27, p70 to p77, p80, p81, pcm1, p cd0 pins and their alternate-function pins 0.7ev dd 0.3ev dd 0.7ev dd 0.3ev dd output signal measurement points remark ev dd should be read as av dd1 when the d/a output pin is used. ac test bus access measurement points bus control pins during accessing external bus (a0 to a25, ad0 to ad15, cs0 to cs7, iowr, iord, lbe/lwr/ldqm, ube/uwr/udqm, rd, wr/we, astb, bcyst, wait, busclk, hldak, hldrq, refrq, sdcke, sdclk, sdcas, sdras, dmaak0 to dmaak3, dmarq0 to dmarq3) 0.5ev dd 0.5ev dd i/o signal measurement points load conditions c l = 50 pf dut (device under measurement) caution if the load capaci tance exceeds 50 pf due to the circ uit configuration, bring the load capacitance of the device to 50 pf or less by in serting a buffer or by some other means.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 964 (1) clock timing (1/2) parameter symbol conditions min. max. unit clock through mode 40 200 ns psel = l 181.8 250 ns x1 input cycle <1> t cyx pll mode psel = h 125 181.8 ns clock through mode 16 ns x1 input high-level width <2> t wxh pll mode 50 ns clock through mode 16 ns x1 input low-level width <3> t wxl pll mode 50 ns clock through mode 4 ns x1 rise time <4> t xr pll mode 6 ns clock through mode 4 ns x1 fall time <5> t xf pll mode 6 ns cpu operating frequency ? f cpu 5 80 mhz busclk output cycle <6> t cyk1 20 200 ns busclk high-level width <7> t wkh1 0.5t ? 6 ns busclk low-level width <8> t wkl1 0.5t ? 6 ns busclk rise time <9> t kr1 6 ns busclk fall time <10> t kf1 6 ns sdclk output cycle <11> t cyk2 20 200 ns sdclk high-level width <12> t wkh2 0.5t ? 6 ns sdclk low-level width <13> t wkl2 0.5t ? 6 ns sdclk rise time <14> t kr2 6 ns sdclk fall time <15> t kf2 6 ns remarks 1. t = t cykn (n = 1, 2) 2. the phase difference between busclk and sdclk cannot be defined. 3. x1 sdclk delay time and x1 busclk delay time cannot be defined. 4. the division ratio of busclk is set by the bmc.ckm1 and bmc.ckm0 bits. 5. the values of busclk and sdclk in the above spec ifications are when a cl ock with a duty factor of 1:1 is input. if the duty factor of the x1 input clock changes in the cl ock through mode, the duty factor of busclk and sdclk also changes, affecting the timing of memory access. in the pll mode, the memory access timing is not affected.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 965 (1) clock timing (2/2) x1 <3> <2> <4> <5> x1 (clock through mode) ( pll mode) <5> <1> <2> <3> <4> busclk (output) <8> <9> <7> <10> <6> sdclk (output) <13> <14> <12> <15> <11> <1> remark busclk cycle differs de pending on the bus cycle.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 966 (2) output waveform (other than x1, busclk, sdclk) parameter symbol conditions min. max. unit output rise time <16> t or 6 ns output fall time <17> t of 6 ns signal other than x1, busclk, sdclk <16> <17> (3) reset timing parameter symbol conditions min. max. unit reset pin high-level width <18> t wrsh 500 ns when power is on, stop mode released 500 + t os ns reset pin low-level width <19> t wrsl other than when power is on, stop mode released 500 ns caution sufficiently evaluate th e oscillation stabilization time. remark t os : oscillation stabilization time reset (input) <18> <19>
chapter 26 electrical specifications user?s manual u16397ej3v0ud 967 (4) sram, external rom, external i/o access timing (in separate bus mode) (a) access timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit address, xbe output delay time (from busclk ) <20> t dka 0 15 ns address, xbe output hold time (from busclk ) <21> t hka 0 13 ns csn delay time (from busclk ) <22> t dkcsl 0 15 ns csn delay time (from busclk ) <23> t hkcsh 0 13 ns rd, iord delay time (from busclk ) <24> t dkrdl 0 13 ns rd, iord delay time (from busclk ) <25> t hkrdh 0 13 ns xwr, iowr, wr delay time (from busclk ) <26> t dkwrl 0 13 ns xwr, iowr, wr delay time (from busclk ) <27> t hkwrh 0 13 ns bcyst delay time (from busclk ) <28> t dkbsl 0 13 ns bcyst delay time (from busclk ) <29> t hkbsh 0 13 ns wait setup time (to busclk ) <30> t swk 12 ns wait hold time (from busclk ) <31> t hkw 0 ns data input setup time (to busclk ) <32> t skid 13 ns data input hold time (from busclk ) <33> t hkid 0 ns <34> t dkod1 0 ns data output delay time (from busclk ) <35> t dkod2 0 16 ns <36> t hkod1 0 ns data float delay time (from busclk ) <37> t hkod2 16 ns remarks 1. satisfy at least one of data input hold times t hrdid or t hkid . 2. n = 0 to 7 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 968 (a) access timing (sram, external rom, external i/o) (2/2) busclk (output) [read] [write] [read] iord, rd (output) t1 tw t2 xbe (output) <20> <21> <24> <26> <27> <25> <33> <32> <37> <30> <30> <31> a0 to a25 (output) wait (input) ad0 to ad15 (i/o) ad0 to ad15 (i/o) <27> <37> <25> <24> <26> <34> note <35> bcyst (output) <28> <29> <28> csn (output) <22> <23> <36> [write] xwr (output) iowr, wr (output) <31> note the t0 cycle is inserted before the t1 cycle. remarks 1. this is the timing when the number of waits set by the dwc0 and dwc1 registers is 0. 2. the broken lines indicate high impedance. 3. n = 0 to 7, x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 969 (b) read timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit data input setup time (to address, xbe, csn) <38> t said note 1 (2 + w + w d + w as )t ? 25 ns data input setup time (to rd, iord) <39> t srdid (1.5 + w + w d )t ? 25 ns rd, iord low-level width <40> t wrdl (1.5 + w + w d )t ? 4 ns rd, iord high-level width <41> t wrdh (0.5 + w as + i)t ? 4 ns delay time from address, xbe, csn to rd, iord <42> t dard note 1 (0.5 + w as )t ? 6 ns delay time from rd, iord to address, xbe <43> t drda it ? 4 ns data input hold time (from rd, iord ) <44> t hrdid 0 ns delay time from rd, iord to data output <45> t drdod (1 + i)t ? 16 ns wait setup time (to address) <46> t saw notes 1, 2 (1 + w as )t ? 24 ns wait setup time (to bcyst ) <47> t sbsw note 2 (1 + w as )t ? 21 ns wait hold time (from bcyst ) <48> t hbsw note 2 w as t ? 4 ns wait high-level width <49> t wwh t ? 4 ns data output hold time (from xwr, iowr, wr ) <50> t hwrod (0.5 + i)t ? 4 ns notes 1. when the csdc.csdcp bit = 1, output of the falli ng edge of the csp signal is delayed by 1 cycle. 2. during the first wait sampling when the number of waits set by the dwc0 and dwc1 registers is 0. remarks 1. t = t cyk1 2. w: number of waits set by wait 3. w d : number of waits set by the dwc0 and dwc1 registers 4. satisfy at least one of data input hold times t hrdid or t hkid . 5. n = 0 to 7 p = 0, 4, 6, 7 x = u, l 6. i: number of idle states 7. w as : number of address setup waits set by the asc register
chapter 26 electrical specifications user?s manual u16397ej3v0ud 970 (b) read timing (sram, external rom, external i/o) (2/2) busclk (output) rd, iord (output) ad0 to ad15 (i/o) t1 tw t2 <44> <41> <40> <45> <38> <39> <42> <46> <47> ti tasw <48> <50> <49> wait (input) bcyst (output) xwr (output) iowr, wr (output) <43> csn (output) xbe (output) a0 to a25 (output) remarks 1. this is the timing when the number of waits se t by the dwc0 and dwc1 registers is 0, the number of idle states set by the bcc register is 1, and the number of waits set by the asc register is 1. 2. the broken lines indicate high impedance. 3. n = 0 to 7 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 971 (c) write timing (sram, external rom, external i/o) (1/2) parameter symbol conditions min. max. unit wait setup time (to address) <46> t saw notes 1, 2 (1 + w as )t ? 24 ns wait setup time (to bcyst ) <47> t sbsw note 1 (1 + w as )t ? 21 ns wait hold time (from bcyst ) <48> t hbsw note 1 w as t ? 4 ns wait high-level width <49> t wwh note 3 t ? 4 ns delay time from address, xbe, csn to xwr, iowr, wr <51> t dawr note 2 (0.5 + w as )t ? 6 ns address, xbe, csn setup time (to xwr, iowr, wr ) <52> t sawr note 2 (1.5 + w + w d + w as )t ? 6 ns delay time from xwr, iowr, wr to address <53> t dwra (0.5 + i)t ? 4 ns delay time from xwr, iowr, wr to csn <54> t dwrcs 0.5t ? 4 ns xwr, iowr, wr high-level width <55> t wwrh (0.5 + i + w as )t ? 4 ns xwr, iowr, wr low-level width <56> t wwrl (1 + w + w d )t ? 4 ns data output setup time (to xwr, iowr, wr ) <57> t sodwr (1.5 + w as + w + w d )t ? 6 ns data output hold time (from xwr, iowr, wr ) <50> t hwrod (0.5 + i)t ? 4 ns notes 1. during the first wait sampling when the number of waits set by the dwc0 and dwc1 registers is 0. 2. when the csdc.csdcp bit = 1, output of the falli ng edge of the csp signal is delayed by 1 cycle. 3. time required for wait release remark 1. t = t cyk1 2. w: number of waits set by wait 3. w d : number of waits set by the dwc0 and dwc1 registers 4. n = 0 to 7 p = 0, 4, 6, 7 x = u, l 5. i: number of idle states 6. w as : number of address setup waits set by the asc register
chapter 26 electrical specifications user?s manual u16397ej3v0ud 972 (c) write timing (sram, external rom, external i/o) (2/2) <52> <54> <51> <56> busclk (output) t1 tw t2 ti tasw <46> <47> wait (input) bcyst (output) <48> <49> <55> xwr (output) iowr, wr (output) <53> ad0 to ad15 (i/o) <57> <50> ad0 to ad15 (i/o) xbe (output) a0 to a25 (output) csn (output) [write write] remarks 1. this is the timing when the number of waits se t by the dwc0 and dwc1 registers is 0, the number of idle states set by the bcc register is 1, and the number of waits set by the asc register is 1. 2. the broken lines indicate high impedance. 3. n = 0 to 7 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 973 (d) dma flyby transfer timing (sram external i/o transfer) (1/2) parameter symbol conditions min. max. unit wait setup time (to busclk ) <30> t swk 12 ns wait hold time (from busclk ) <31> t hkw 0 ns rd low-level width <40> t wrdl (1.5 + w + w d )t ? 4 ns rd high-level width <41> t wrdh (0.5 + i + w as )t ? 4 ns delay time from address, xbe, csn to rd <42> t dard note 1 (0.5 + w as )t ? 6 ns delay time from rd to address, xbe <43> t drda it ? 4 ns delay time from rd to data output <45> t drdod (1 + i)t ? 16 ns wait setup time (to address) <46> t saw note 2 (1 + w as )t ? 24 ns wait setup time (to bcyst ) <47> t sbsw note 2 (1 + w as )t ? 21 ns wait hold time (from bcyst ) <48> t hbsw note 2 w as t ? 4 ns wait high-level width <49> t wwh t ? 4 ns delay time from address, xbe, csn to iowr <51> t dawr note 1 (0.5 + w as )t ? 6 ns address, xbe, csn setup time (to iowr ) <52> t sawr note 1 (1.5 + w + w d + w as )t ? 6 ns delay time from iowr to address, xbe <53> t dwra (0.5 + i)t ? 4 ns iowr high-level width <55> t wwrh (0.5 + i + w as )t ? 4 ns iowr low-level width <56> t wwrl (1 + w + w d )t ? 4 ns delay time from iowr to rd <58> t diwrrd 0.5t ? 4 ns delay time from dmaakm to iowr <59> t ddawr (0.5 + w as )t ? 8 ns delay time from iowr to dmaakm <60> t dwrda (0.5 + i)t ? 8 ns notes 1. when the csdc.csdcp bit = 1, output of the falli ng edge of the csp signal is delayed by 1 cycle. 2. during the first wait sampling when the number of waits set by the fwc register is 0. remarks 1. t = t cyk1 2. w: number of waits set by wait 3. w d : number of waits set by the fwc register 4. n = 0, 1, 3, 4, 6, 7 m = 0 to 3 p = 0, 4, 6, 7 x = u, l 5. i: number of idle states 6. w as : number of address setup waits set by the asc register
chapter 26 electrical specifications user?s manual u16397ej3v0ud 974 (d) dma flyby transfer timing (sram external i/o transfer) (2/2) <40> <55> <51> <52> <42> <41> <59> <56> <30> <31> <30> <31> <46> dmaakm (output) iord (output) iowr (output) rd (output) wait (input) bcyst (output) <47> a0 to a25 (output) <48> busclk (output) t1 twt2 tasw <43> <60> <53> <45> ti <58> <49> csn (output) ad0 to ad15 (i/o) xbe (output) xwr (output) wr (output) t2 remarks 1. this is the timing when the number of waits set by the fwc register is 0, the number of idle states set by the fic register is 1, and the number of waits set by the asc register is 1. 2. the broken lines indicate high impedance. 3. n = 0, 1, 3, 4, 6, 7, m = 0 to 3, x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 975 (e) dma flyby transfer timing (external i/o sram transfer) (1/2) parameter symbol conditions min. max. unit wait setup time (to busclk ) <30> t swk 12 ns wait hold time (from busclk ) <31> t hkw 0 ns iord low-level width <40> t wrdl (1.5 + w + w d )t ? 4 ns iord high-level width <41> t wrdh (0.5 + i + w as )t ? 4 ns delay time from address, xbe, csn to iord <42> t dard note 1 (0.5 + w as )t ? 6 ns delay time from iord to address, xbe <43> t drda it ? 4 ns delay time from iord to data output <45> t drdod (1 + i)t ? 16 ns wait setup time (to address) <46> t saw note 2 (1 + w as )t ? 24 ns wait setup time (to bcyst ) <47> t sbsw note 2 (1 + w as )t ? 21 ns wait hold time (from bcyst ) <48> t hbsw note 2 w as t ? 4 ns wait high-level width <49> t wwh t ? 4 ns delay time from address, xbe, csn to xwr, wr <51> t dawr note 1 (0.5 + w as )t ? 6 ns address, xbe, csn setup time (to xwr, wr ) <52> t sawr note 1 (1.5 + w + w d + w as )t ? 6 ns delay time from xwr, wr to address, xbe <53> t dwra (0.5 + i)t ? 4 ns xwr, wr high-level width <55> t wwrh (0.5 + i + w as )t ? 4 ns xwr, wr low-level width <56> t wwrl (1 + w + w d )t ? 4 ns delay time from xwr, wr to iord <61> t dwrird 0.5t ? 4 ns delay time from dmaakm to iord <62> t ddard (0.5 + w as )t ? 8 ns delay time from iord to dmaakm <63> t drdda it ? 4 ns notes 1. when the csdc.csdcp bit = 1, output of the falli ng edge of the csp signal is delayed by 1 cycle. 2. during the first wait sampling when the number of waits set by the fwc register is 0. remarks 1. t = t cyk1 2. w: number of waits set by wait 3. w d : number of waits set by the fwc register 4. n = 0, 1, 3, 4, 6, 7 m = 0 to 3 p = 0, 4, 6, 7 x = u, l 5. i: number of idle states 6. w as : number of address setup waits set by the asc register
chapter 26 electrical specifications user?s manual u16397ej3v0ud 976 (e) dma flyby transfer timing (external i/o sram transfer) (2/2) <51> <52> <53> <55> <41> <42> <30> <31> <30> <31> <46> dmaakm (output) iord (output) iowr (output) rd (output) wait (input) bcyst (output) <47> a0 to a25 (output) <48> busclk (output) t1 tw tasw <45> ti <61> <49> csn (output) ad0 to ad15 (i/o) <56> <40> <43> xbe (output) xwr (output) wr (output) <62> <63> t2 remarks 1. this is the timing when the number of waits set by the fwc register is 0, the number of idle states set by the fic register is 1, and the number of waits set by the asc register is 1. 2. the broken lines indicate high impedance. 3. n = 0, 1, 3, 4, 6, 7, m = 0 to 3, x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 977 (5) sram, external rom access timing (in multiplexed bus mode) (a) read timing (busclk asynchronous) (sram, external rom) (1/3) parameter symbol conditions min. max. unit address, xbe, csn setup time (to astb ) <64> t sast (0.5 + w as )t ? 8 ns address hold time (from astb ) <65> t hsta (0.5 + w ah )t ? 8 ns delay time from rd to address float <66> t frda 13 ns data input setup time (to address, xbe, csn) <67> t said (2 + w + w d + w as + w ah )t ? 25 ns data input setup time (to rd ) <68> t srdid (1 + w + w d )t ? 25 ns delay time from astb to rd <69> t dstrd (0.5 + w ah )t ? 8 ns data input hold time (from rd ) <44> t hrdid 0 ns delay time from rd to address, xbe <70> t drda (1 + i)t ? 8 ns delay time from rd to astb <71> t drrst 0.5t ? 8 ns delay time from rd to astb <72> t drdst (1.5 + i)t ? 8 ns rd low-level width <73> t wrd (1 + w + w d )t ? 4 ns astb high-level width <74> t wsth (1 + i + w as )t ? 4 ns wait setup time (to address) <75> t sawt1 note (1.5 + w + w d + w as + w ah )t ? 25 ns wait setup time (to astb ) <76> t sstwt1 note (w + w d + w ah )t ? 25 ns note w, w d 1 remarks 1. t = t cyk1 2. w: number of waits set by wait 3. w d : number of waits set by the dwc0 and dwc1 registers when the programmable wait clock is inserted, the sampling timing differs. 4. satisfy at least one of data input hold times t hrdid and t hkid . 5. n = 0 to 7 x = u, l 6. i: number of idle states 7. w as : number of address setup waits set by the asc register 8. w ah : number of address hold waits set by the ahc register
chapter 26 electrical specifications user?s manual u16397ej3v0ud 978 (a) read timing (busclk synchronous ) (sram, external rom) (2/3) parameter symbol conditions min. max. unit bcyst delay time (from busclk ) <28> t dkbsl 0 13 ns bcyst delay time (from busclk ) <29> t hkbsh 0 13 ns address, xbe, csn output delay time (from busclk ) <20> t dka 0 15 ns address float delay time (from busclk ) <77> t fka 0 15 ns astb delay time (from busclk ) <78> t dkst 0 13 ns rd delay time (from busclk ) <79> t dkrd 0 13 ns data input setup time (to busclk ) <80> t sidk 12 ns data input hold time (from busclk ) <33> t hkid 0 ns wait setup time (to busclk ) <81> t swtk 12 ns wait hold time (from busclk ) <82> t hkwt 0 ns remark n = 0 to 7 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 979 (a) read timing (busclk asynchronous/busclk synchronous) (sram, external rom) (3/3) busclk (output) tasw t1 tah t2 tw t3 ad0 to ad15 (i/o) csn (output) <20> <69> <76> <81> <81> <70> <82> <82> astb (output) rd (output) wait (input) a16 to a25 (output) xbe (output) bcyst (output) <68> <66> <79> <73> <71> <72> <78> <78> <20> <20> address address data <77> <80> <33> <67> <64> <74> <65> <75> <28> <29> <28> <29> ti <79> <44> remarks 1. this is the timing when the number of waits set by the dwc0 and dwc1 registers is 0, the number of idle states set by the bcc register is 1, the number of waits set by the asc register is 1, and the number of waits set by the ahc register is 1. 2. the broken lines indicate high impedance. 3. iord and iowr are not supported in the multiplexed bus mode. 4. n = 0 to 7 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 980 (b) write timing (busclk asynchronous) (sram, external rom) (1/3) parameter symbol conditions min. max. unit address, xbe, csn setup time (to astb ) <64> t sast (0.5 + w as )t ? 8 ns address hold time (from astb ) <65> t hsta (0.5 + w ah )t ? 8 ns delay time from astb to xwr, wr <83> t dstwr (0.5 + w ah )t ? 8 ns delay time from xwr, wr to astb <84> t dwrst 0.5t ? 8 ns xwr, wr low-level width <56> t wwrl (1 + w + w d )t ? 4 ns astb high-level width <85> t wsth (1 + i + w as )t ? 8 ns time from xwr, wr to data output <86> t dwrod 4 ns data output setup time (to xwr, wr ) <87> t sodwr (1 + w + w d )t ? 11 ns data output hold time (from xwr, wr ) <88> t hwrod (1 + i)t ? 8 ns wait setup time (to address) <75> t sawt1 note (1.5 + w + w d + w as + w ah )t ? 25 ns wait setup time (to astb ) <76> t sstwt1 note (w + w d + w ah )t ? 25 ns note w, w d 1 remarks 1. t = t cyk1 2. w: number of waits set by wait 3. w d : number of waits set by the dwc0 and dwc1 registers when a programmable wait clock is inserted, the sampling timing differs. 4. satisfy at least one of data input hold times t hrdid or t hkid . 5. n = 0 to 7 x = u, l 6. i: number of idle states 7. w as : number of address setup waits set by the asc register 8. w ah : number of address hold waits set by the ahc register
chapter 26 electrical specifications user?s manual u16397ej3v0ud 981 (b) write timing (busclk synchronous) (sram, external rom) (2/3) parameter symbol conditions min. max. unit bcyst delay time (from busclk ) <28> t dkbsl 0 13 ns bcyst delay time (from busclk ) <29> t hkbsh 0 13 ns address, xbe, csn output delay time (from busclk ) <20> t dka 0 15 ns astb delay time (from busclk ) <78> t dkst 0 13 ns xwr, wr delay time (from busclk ) <89> t dkwr 0 13 ns data output delay time (from busclk ) <90> t dkod 0 13 ns wait setup time (to busclk ) <81> t swtk 12 ns wait hold time (from busclk ) <82> t hkwt 0 ns remark n = 0 to 7 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 982 (b) write timing (busclk asynchronous/busclk synchronous) (sram, external rom) (3/3) busclk (output) tasw t1 tah t2 tw t3 ad0 to ad15 (i/o) csn (output) <20> <83> <76> <81> <81> <82> <82> astb (output) xwr, wr (output) wait (input) a16 to a25 (output) xbe (output) bcyst (output) <87> <86> <89> <56> <84> <88> <78> <78> <20> <20> address address data <90> <64> <85> <65> <75> <28> <29> <28> <29> ti <89> remarks 1. this is the timing when the number of waits set by the dwc0 and dwc1 registers is 0, the number of idle states set by the bcc register is 1, the number of waits set by the asc register is 1, and the number of waits set by the ahc register is 1. 2. iord and iowr are not supported in multiplexed bus mode. 3. n = 0 to 7 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 983 (6) page rom access timing (1/2) parameter symbol conditions min. max. unit wait setup time (to busclk ) <30> t swk 12 ns wait hold time (from busclk ) <31> t hkw 0 ns data input setup time (to busclk ) <32> t skid 13 ns data input hold time (from busclk ) <33> t hkid 0 ns off-page data input setup time (to address, csn ) <38> t said (2 + w + w d + w as )t ? 25 ns off-page data input setup time (to rd) <39> t srdid (1.5 + w + w d )t ? 25 ns data input hold time (from rd ) <44> t hrdid 0 ns delay time from rd to data output <45> t drdod (1 + i)t ? 16 ns wait high-level width <49> t wwh t ? 4 ns on-page data input setup time (to address) <91> t soaid (2 + w + w pr + w as )t ? 25 ns remarks 1. t = t cyk1 2. w: number of waits set by wait 3. w d : number of waits set by the dwc0 and dwc1 registers 4. w pr : number of waits set by the prc register 5. i: number of idle states inserted when a read cycle is followed by the write cycle 6. w as : number of address setup waits set by the asc register 7. satisfy at least one of data input hold times t hrdid or t hkid .
chapter 26 electrical specifications user?s manual u16397ej3v0ud 984 (6) page rom access timing (2/2) to1 csn (output) busclk (output) t1 tdw tw t2 <38> <39> <33> <31> <30> <30> <31> ad0 to ad15 (i/o) rd (output) <32> tprw tw to2 <91> <32> <33> <94> <31> <31> <49> <30> tasw <45> address (output) wait (input) bcyst (output) iowr (output) wr (output) <30> remarks 1. timing when the following. number of waits set by the dwc0 and dwc1 registers (tdw): 1 number of waits set by the prc register (tprw): 1 number of waits set by the asc register (tasw): 1 2. the broken lines indicate high impedance. 3. n = 0 to 7
chapter 26 electrical specifications user?s manual u16397ej3v0ud 985 (7) sdram access timing (a) read timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from sdclk ) <92> t dska 2 15 ns bcyst delay time (from sdclk ) <93> t dskbc 0 15 ns csn delay time (from sdclk ) <94> t dskcs 1.5 15 ns sdras delay time (from sdclk ) <95> t dskras 1 15 ns sdcas delay time (from sdclk ) <96> t dskcas 1 15 ns xdqm delay time (from sdclk ) <97> t dskdqm 2 15 ns sdcke delay time (from sdclk ) <98> t dskcke 1.5 15 ns data input setup time (sdram read, to sdclk ) <99> t sdrmsk 12 ns data input hold time (sdram read, from sdclk ) <100> t hskdrm 0 ns delay time from sdclk to data output <101> t dsdod (1 + i)t ? 5 ns caution if a sram (external i/o) cycle that uses the xw r signal is generated immediately after the cycle to read sdram, sram (external i/o) may be written by mistake. in this case, see 5.4.2 chip select signal delay control register (csdc). however, sram (external i/o) is not written by mi stake if synchronization is designed so that the xwr signal is sampled with busclk. remarks 1. t = t cyk2 2. i: number of idle states 3. n = 1, 3, 4, 6 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 986 (a) read timing (sdram access) (2/2) sdclk (output) tact tbcw tread tlate tlate <92> sdram: csn (output) ad0 to ad15 (i/o) sdcke (output) a11 (output) a1 to a10 (output) <93> <94> <92> <92> <92> <92> <92> <95> h <96> <99> <100> <93> <94> <95> <96> <97> <92> bcyst (output) sdras (output) sdcas (output) we (output) data address bank address (output) <101> address other than bank address, a1 to a10, a11 (output) bank address row address row address column address <97> <98> <98> udqm (output) ldqm (output) caution a glitch may be generated wh en bcyst successively outputs low levels. remarks 1. number of waits set by the bcwn1 and bcw n0 bits of the scrn register (tbcw): 2 2. the broken lines indicate high impedance. 3. n = 1, 3, 4, 6
chapter 26 electrical specifications user?s manual u16397ej3v0ud 987 (b) write timing (sdram access) (1/2) parameter symbol conditions min. max. unit address delay time (from sdclk ) <92> t dska 2 15 ns bcyst delay time (from sdclk ) <93> t dskbc 0 15 ns csn delay time (from sdclk ) <94> t dskcs 1.5 15 ns sdras delay time (from sdclk ) <95> t dskras 1 15 ns sdcas delay time (from sdclk ) <96> t dskcas 1 15 ns xdqm delay time (from sdclk ) <97> t dskdqm 2 15 ns sdcke delay time (from sdclk ) <98> t dskcke 1.5 15 ns we delay time (from sdclk ) <102> t dskwe 2 15 ns data output delay time (from sdclk ) <103> t dskdt 2 15 ns data float delay time (from sdclk ) <104> t hzskdt 2 15 ns caution if a sram (external i/o) cycle that uses the xwr or wr signal is genera ted immediately after the cycle to write sdram, sram (external i/o) may be wri tten by mistake. in th is case, see 5.4.2 chip select signal delay control register (csdc). however, sram (external i/o) is not written by mi stake if synchronization is designed so that the xwr or wr signal is sampled with busclk. remark n = 1, 3, 4, 6 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 988 (b) write timing (sdram access) (2/2) sdclk (output) address other than bank address, a1 to a10, a11 (output) tact tbcw twr <92> ad0 to ad15 (i/o) sdcke (output) a11 (output) a1 to a10 (output) <93> <94> <92> <92> <92> <92> <92> <95> <96> <102> <97> <103> <104> <93> <94> <95> <96> <102> <97> <92> bcyst (output) sdcas (output) we (output) sdras (output) sdram: csn (output) data address bank address (output) bank address row address row address column address <98> <98> udqm (output) ldqm (output) caution a glitch may be generated when bcyst successively outputs low levels. remarks 1. number of waits (tbcw) set by the bcw n1 and bcwn0 bits of the scrn register: 2 2. the broken lines indicate high impedance. 3. n = 1, 3, 4, 6
chapter 26 electrical specifications user?s manual u16397ej3v0ud 989 (8) dmac timing (1/2) parameter symbol conditions min. max. unit dmarqn setup time (to busclk ) <105> t sdrk 2-cycle transfer 12 ns dmarqn hold time 1 <106> t hkdr1 2-cycle transfer up to dmaakn ns 3t cpu ? 27 note 1 ns nomask 6t cpu ? 27 note 2 ns 2t bus + 5t cpu ? 27 note 1 ns dmarqn hold time 2 (from dmaakn ) <107> t hkdr2 mask 2t bus + 8t cpu ? 27 note 2 ns dmarqn hold time 3 after dmaakn (from busclk ) <108> t hkdr3 2-cycle transfer, mask 2t bus + 2t cpu ? 15 ns 2t cpu ? 6 note 3 ns 2-cycle transfer, nomask 5t cpu ? 6 note 4 ns 2t cpu ? 6 note 3 ns dmaakn low-level width <109> t wdal 2-cycle transfer, mask 5t cpu ? 6 note 4 ns tcn output delay time (from busclk ) <110> t dktc 2-cycle transfer 0 16 ns tcn output hold time (from busclk ) <111> t hktc 2-cycle transfer 0 16 ns notes 1. this is the second dma transfer request disabling timing for single transfer. the access is as follows (when the number of waits for external memory access = 0). transfer source transfer destination internal ram external memory 2. this is the second dma transfer request disabling timing for single transfer. the access is other than that shown in the table in note 1 . 3. the access is as follows. transfer source transfer destination internal ram external memory external memory internal ram 4. the access is other than that shown in the table in note 3 . remarks 1. n = 0 to 3 2. t bus = 1 busclk cycle 3. t cpu = 1 internal system clock cycle 4. nomask: masking of dmarqn is not selected (difc.drmkn bit = 0). 5. mask: masking of dmarqn is selected (difc.drmkn bit = 1).
chapter 26 electrical specifications user?s manual u16397ej3v0ud 990 (8) dmac timing (2/2) busclk (output) <107> <110> <105> dmaakn (output) dmarqn (input) tcn (output) <111> <108> <109> <106> remarks 1. in 2-cycle transfer, the tcn signa l is output in a write cycle. the time from the dmaakn signal falling edge to tcn signal output cannot be defined. 2. n = 0 to 3
chapter 26 electrical specifications user?s manual u16397ej3v0ud 991 (9) bus hold timing (1/2) parameter symbol conditions min. max. unit hldrq setup time (to busclk ) 8 ns hldrq setup time (to sdclk ) <112> t shrk 8 ns hldrq hold time (from busclk ) 0 ns hldrq hold time (from sdclk ) <113> t hkhr 0 ns hldak delay time (from busclk ) 0 18 ns hldak delay time (from sdclk ) <114> t dkhal 0 18 ns hldak delay time (from busclk ) 0 13 ns hldak delay time (from sdclk ) <115> t dkhah 0 13 ns hldrq high-level width <116> t whqh t + 4 ns hldak low-level width <117> t whal t ? 11 ns delay time from bus float to hldak <118> t dhcf 0 ns delay time from hldak to bus output <119> t dhac 0 15 ns delay time from hldrq to hldak <120> t dhqha1 2t ns delay time from hldrq to hldak <121> t dhqha2 t 2t + 21 ns remark t = t cykn (n = 1, 2)
chapter 26 electrical specifications user?s manual u16397ej3v0ud 992 (9) bus hold timing (2/2) <112> th th th ti <113> <112> <120> <114> <117> <121> <116> <115> <118> <119> data busclk (output) sdclk (output) ad0 to ad15 (i/o) a0 to a25 (output) xbe (output) hldrq (input) hldak (output) astb (output) iord, rd (output) iowr, wr (output) xwr (output) remarks 1. the broken lines indicate high impedance. 2. n = 0 to 7 x = u, l
chapter 26 electrical specifications user?s manual u16397ej3v0ud 993 (10) interrupt timing (1/2) parameter symbol conditions min. max. unit nmi high-level width <122> t wnih note 1 500 ns nmi low-level width <123> t wnil note 1 500 ns intpa pin high-level width <124> t with0 note 1 500 ns intpa pin low-level width <125> t witl0 note 1 500 ns intppb, intpqk pins high-level width <126> t with1 notes 1, 2 3t 0 + 500 ns intppb, intpqk pins low-level width <127> t witl1 notes 1, 2 3t 0 + 500 ns intp10, intp11 pins high-level width <128> t with2 note 2 3t 1 + 15 ns intp10, intp11 pins low-level width <129> t witl2 note 2 3t 1 + 15 ns notes 1. noise is eliminated for at least 30 ns. 2. when timer p, timer q, or timer enc1 is selected as an alternate function in the port function settings, noise is digitally eliminated. remarks 1. a = 000, 001, 004, 005, 010 to 013, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137 b = 00, 01, 10, 11, 20, 21 k = 0 to 3 2. t 0 : tpnctl0.tpncks2 to tpnctl0.tpncks0 set values for intppb (n = 0 to 2) tq0ctl0.tq0cks2 to tq0ctl0.tq0cks0 set values for intpqk 3. t 1 : prm10.prm102 to prm10.prm100 set values
chapter 26 electrical specifications user?s manual u16397ej3v0ud 994 (10) interrupt timing (2/2) <122> <123> nmi (input) <124> <125> intpa (input) <126> <127> intppb (input) intpqk (input) <128> <129> intp10 (input) intp11 (input) remark a = 000, 001, 004, 005, 010 to 01 3, 021, 022, 050, 051, 106, 107, 114, 115, 124 to 126, 130 to 134, 137 b = 00, 01, 10, 11, 20, 21 k = 0 to 3 (11) timer p (tmp), timer q (tmq) timing parameter symbol conditions min. max. unit evtpn/tipn, evtq, tiq high-level width <130> t wtih note 3t 0 + 500 ns evtpn/tipn, evtq, tiq low-level width <131> t wtil note 3t 0 + 500 ns note a noise of at least 40 ns is eliminated. remarks 1. n = 0 to 2 2. t 0 : tpnctl0.tpncks2 to tpnctl0.tpncks0 set values for evtpn/tipn tq0ctl0.tq0cks2 to tq0ctl0. tq0cks0 set values for evtq, tiq <130> <131> evtpn/tipn (input) evtq, tiq (input)
chapter 26 electrical specifications user?s manual u16397ej3v0ud 995 (12) timer enc1 (tmenc1) timing parameter symbol conditions min. max. unit tiud10, tcud10, tclr10 pins high-level width <132> t wudih 4t + 10 ns tiud10, tcud10, tclr10 pins low-level width <133> t wudil 4t + 10 ns time difference from tiud10 to tcud10 <134> t phud1 note 4t + 15 ns time difference from tcud10 to tiud10 <135> t phud2 note 4t + 15 ns note the effect when noise is input is not included. remarks 1. t = 1/f xx (f xx : system clock) 2. the digital noise eliminator is vali d for tiud10, tcud10, and tclr10 pins. <132> <133> tiud10 (input) <133> tcud10 (input) <132> <134> <135> <135> <134> <132> <133> tclr10 (input)
chapter 26 electrical specifications user?s manual u16397ej3v0ud 996 (13) uarta timing parameter symbol conditions min. max. unit asckn cycle time <136> t kcy 25 ns asckn high-level width <137> t kh 10 ns asckn low-level width <138> t kl 10 ns remark n = 0 to 2 <137> <138> asckn (input) <136> remark n = 0 to 2
chapter 26 electrical specifications user?s manual u16397ej3v0ud 997 (14) csib timing (1/3) (a) master mode parameter symbol conditions min. max. unit sckn cycle <139> t cysk1 output 100 ns sckn high-level width <140> t wsk1h output 0.5t cysk1 ? 20 ns sckn low-level width <141> t wsk1l output 0.5t cysk1 ? 20 ns sin setup time (to sckn ) 30 ns sin setup time (to sckn ) <142> t ssisk 30 ns sin hold time (from sckn ) 0 ns sin hold time (from sckn ) <143> t hsksi 0 ns son output delay time (from sckn ) 20 ns son output delay time (from sckn ) <144> t dskso 20 ns son output hold time (from sckn ) 0.5t cysk1 ? 5 ns son output hold time (from sckn ) <145> t hskso 0.5t cysk1 ? 5 ns remark n = 0 to 2 (b) slave mode parameter symbol conditions min. max. unit sckn cycle <139> t cysk1 input 100 ns sckn high-level width <140> t wsk1h input 30 ns sckn low-level width <141> t wsk1l input 30 ns sin setup time (to sckn ) 10 ns sin setup time (to sckn ) <142> t ssisk 10 ns sin hold time (from sckn ) 10 ns sin hold time (from sckn ) <143> t hsksi 10 ns son output delay time (from sckn ) 30 ns son output delay time (from sckn ) <144> t dskso 30 ns son output hold time (from sckn ) t wsk1h ns son output hold time (from sckn ) <145> t hskso t wsk1h ns remark n = 0 to 2
chapter 26 electrical specifications user?s manual u16397ej3v0ud 998 (14) csib timing (2/3) (c) timing when cbnctl1.cbnckp , cbnctl1.cbndap bits = 00 <139> <141> <140> <142> <143> <144> <145> sin (input) son (output) sckn (i/o) input data output data remarks 1. the broken lines indicate high impedance. 2. n = 0 to 2 (d) timing when cbnctl1.cbnckp , cbnctl1.cbndap bits = 01 <142> <143> <145> sin (input) son (output) input data output data <139> <141> <140> sckn (i/o) <144> remarks 1. the broken lines indicate high impedance. 2. n = 0 to 2
chapter 26 electrical specifications user?s manual u16397ej3v0ud 999 (14) csib timing (3/3) (e) timing when cbnctl1.cbnckp , cbnctl1.cbndap bits = 10 <139> <140> <141> <142> <143> <144> <145> sin (input) son (output) sckn (i/o) input data output data remarks 1. the broken lines indicate high impedance. 2. n = 0 to 2 (f) timing when cbnctl1.cbnckp, cbnctl1.cbndap bits = 11 <142> <143> <145> sin (input) son (output) input data output data <139> <140> <141> sckn (i/o) <144> remarks 1. the broken lines indicate high impedance. 2. n = 0 to 2
chapter 26 electrical specifications user?s manual u16397ej3v0ud 1000 (15) i 2 c bus mode (i 2 c bus versions (y products) only) (1/2) standard mode high-speed mode parameter symbol min. max. min. max. unit scl clock frequency ? f clk 0 100 0 400 khz bus free time (between stop condition and start condition) <146> t buf 4.7 ? 1.3 ? s hold time note 1 <147> t hd: sta 4.0 ? 0.6 ? s scl clock low-level width <148> t low 4.7 ? 1.3 ? s scl clock high-level width <149> t high 4.0 ? 0.6 ? s start/restart condition setup time <150> t su: sta 4.7 ? 0.6 ? s cbus-compatible master 5.0 ? ? ? s data hold time i 2 c mode <151> t hd: dat 0 note 2 ? 0 note 2 0.9 note 3 s data setup time <152> t su: dat 250 ? 100 note 4 ? ns sda, scl signal rise time <153> t r ? 1000 20 + 0.1cb note 5 300 ns sda, scl signal fall time <154> t f ? 300 20 + 0.1cb note 5 300 ns stop condition setup time <155> t su: sto 4.0 ? 0.6 ? s pulse width of spike suppressed by input filter <156> t sp ? ? 0 50 ns each bus line capacitive load ? cb ? 400 ? 400 pf notes 1. the first clock pulse is generated after a hold time under the start condition. 2. the system must internally supply a hold time of at least 300 ns for the sda signal (at v ihmin . of scl signal) to fill the undefined area at the falling edge of scl. 3. if the system does not extend the low hold time (t low ) of the scl signal, the maximum data hold time (t hd:dat ) must be satisfied. 4. the high-speed mode i 2 c bus can be used in the standard mode i 2 c bus system. in this case, make sure that the following conditions are satisfied. ? if system does not extend the hold time of the scl signal in the low status t su: dat 250 ns ? if system extends the hold time of scl signal in the low status sends the next data bit to the sda line before the scl line is released (t rmax . + t su:dat = 1000 + 250 = 1250 ns: standard mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf)
chapter 26 electrical specifications user?s manual u16397ej3v0ud 1001 (15) i 2 c bus mode (i 2 c bus versions (y products) only) (2/2) stop condition start condition restart condition stop condition sda (i/o) <149> <148> <146> <153> <154> <147> <153> <151> <152> <150> <147> <156> <155> <154> scl (i/o)
chapter 26 electrical specifications user?s manual u16397ej3v0ud 1002 a/d converter characteristics (t a = ? 40 to +85 c, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v, v ss = ev ss = cv ss = av ss0 = av ss1 = 0 v) parameter symbol conditions min. typ. max. unit resolution ? 10 10 10 bit overall error note 1 ? 0.8 %fsr quantization error ? 1/2 lsb conversion time note 2 t conv 2.25 5.00 s sampling time t samp conversion clock note 4 4/26 clock integral linearity error note 1 ? 0.5 %fsr differential linearity error note 1 ? 0.5 %fsr zero-scale error note 3 ? 5 lsb full-scale error note 3 ? 5 lsb analog input voltage v wasn av ss0 av dd0 v av dd0 supply current ai dd0 12 ma notes 1. excluding quantization error ( 0.05%fsr) 2. conversion time only for the analog block. the conver sion time set by the adm1.f r2 to adm1.fr0 bits is the value including the time of transfer to the a/d controller block. 3. excluding quantization error ( 0.5 lsb) 4. conversion clock is the number of clocks set by the adm1 register. remark lsb: least significant bit fsr: full scale range %fsr is the ratio to the full-scale value. d/a converter characteristics (t a = ? 40 to +85 c, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v, v ss = ev ss = cv ss = av ss0 = av ss1 = 0 v) parameter symbol conditions min. typ. max. unit resolution ? 8 8 8 bit overall error note 1 ? load condition: 2 m ? , 20 pf av dd1 = ev dd 1.18 %fsr settling time ? 3 s output resistance ? 3.5 k ? av dd1 supply current note 2 ai dd1 5 ma notes 1. excluding quantization error ( 0.2%fsr). 2. current value when conversion value is 55h or abh.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 1003 26.2 power-on/off sequence if the power to the internal circuitry (v dd ) is outside the guaranteed operating range (2.3 to 2.7 v) in the power- on/off sequence when a voltage is applied to the power supplies for the external circuitry (ev dd , cv dd , av dd0 , and av dd1 ), the following phenomena may occur. [phenomena] ? a current of about 130 ma (typ.) flows into the ev dd pin. ? an undefined level is output from the following pins. tdo/tc3/p27 pin ano0/p80 pin ano1/p81 pin therefore, the following power-on/off sequence is recomm ended. by turning on/off power in this sequence, the above phenomena can be avoided. [recommended sequence] ? to turn on keep the voltage on the ev dd , cv dd , av dd0 , and av dd1 pins to within 0.5 v until the voltage on the v dd pin reaches the guaranteed operation range (2.3 to 2.7 v). ? to turn off keep the voltage on the v dd pin in the guaranteed operation range (2.3 to 2.7 v) until the voltage on the ev dd , cv dd , av dd0 , and av dd1 pin falls below 0.5 v. (a) time of recommended sequence v dd ev dd , cv dd , av dd0 , av dd1 reset (input) 2.3 v 2.3 v 0.5 v 0.5 v 3.0 v 0 ns (min.) 0 ns (min.) oscillation stabilization time caution turn on/off power within this time to avoid the above phenomena. (b) time if external power is turned on first or later reset (input) ev dd , cv dd , av dd0 , av dd1 500 ms (max.) 3 s (max.) v dd 2.3 v 2.3 v 0.5 v 0.5 v oscillation stabilization time caution if the time shown in (a) time of the recommended sequence cannot be satisfied, the above phenomena may occur. keep this time even if the above phenomena do not affect the application.
chapter 26 electrical specifications user?s manual u16397ej3v0ud 1004 26.3 flash memory programming mode ( pd70f3134a, 70f3134ay only) basic characteristics (t a = ? 40 to +85 c, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v, v ss = ev ss = cv ss = av ss0 = av ss1 = 0 v) parameter symbol conditions min. typ. max. unit f cpu1 when self programming 10 80 mhz operating frequency f cpu2 when pg-fp4 is used 40 80 note 1 mhz supply voltage v dd 2.3 2.7 v rewrite count c wrt 1 erasure + 1 rewrite after erasure = 1 rewrite, note 2 100 100 100 times programming temperature t prg ? 20 70 c notes 1. 40 mhz when power is supplied from pg-fp4. 2. when writing initially to shipped products, it is count ed as one rewrite for both ?erase to write? and ?write only?. example (p: write, e: erase) shipped product ?? p e p e p: 3 rewrites shipped product e p e p e p: 3 rewrites remarks 1. when the pg-fp4 is used, a time parameter requi red for writing/erasing by downloading parameter files is automatically set. do not change the settings otherwise specified. 2. block 0 = 00000h to 0ffffh, block 1 = 10000h to 7ffffh
chapter 26 electrical specifications user?s manual u16397ej3v0ud 1005 serial write operation characteristics (t a = ? 20 to +70 c, v dd = 2.5 v 0.2 v, ev dd = cv dd = av dd0 = av dd1 = 3.3 v 0.3 v, v ss = ev ss = cv ss = av ss0 = av ss1 = 0 v) parameter symbol conditions min. typ. max. unit flmd0, flmd1 setup time t mdset 2 s flmd0 count start time from reset t rfcf 8.5 ms count execution time t count 120 ms flmd0 counter high-level width t ch 50 s flmd0 counter low-level width t cl 50 s flmd0 counter rise time t r 50 ns flmd0 counter fall time t f 50 ns v dd flmd1 0 v v dd reset (input) 0 v v dd 0 v v dd flmd0 0 v t rfcf t mdset t cl t f t r t ch v dd (input) t count
user?s manual u16397ej3v0ud 1006 chapter 27 package drawings 108 73 136 109 144 72 37 144-pin plastic lqfp (fine pitch) (20x20) item millimeters note a 22.0 0.2 b 20.0 0.2 c 20.0 0.2 d f 1.25 22.0 0.2 s144gj-50-uen s 1.5 0.1 k 1.0 0.2 l 0.5 0.2 r3 + 4 ? 3 g 1.25 h 0.22 0.05 i 0.08 j 0.5 (t.p.) m 0.17 n 0.08 p 1.4 q 0.10 0.05 + 0.03 ? 0.07 each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. s s m detail of lead end i j f g h q r p k m l n cd s a b
chapter 27 package drawings user?s manual u16397ej3v0ud 1007 161-pin plastic fbga (13x13) item millimeters d e 13.00 0.10 13.00 0.10 w 0.20 e x 0.08 y 0.10 a 1.48 0.10 a1 0.35 0.06 a2 1.13 0.80 index mark a a2 a1 ze zd y1 0.20 zd 1.30 ze 1.30 b 0.50 + 0.05 ? 0.10 p161f1-80-en4-1 a b c d e f g h j k l m n p 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b s y1 e s y s s w a s w b s b x ab m e d
user?s manual u16397ej3v0ud 1008 chapter 28 recommended soldering conditions these products should be soldered and mount ed under the following recommended conditions. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html) table 28-1. surface mounting type soldering cond itions (1/2) (1) pd703131agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd703131aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd703132agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd703132aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd703133agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd703133aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd703134agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd703134aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd70f3134agj-uen 144-pin plastic lqfp (fine pitch) (20 20) pd70f3134aygj-uen 144-pin plasti c lqfp (fine pitch) (20 20) pd703136agj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) pd703136aygj-xxx-uen 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220c or higher), count: 3 times or less, exposure limit: 3 days note (after that, prebake at 125c for 36 to 72 hours) ir60-363-3 partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ?
chapter 28 recommended soldering conditions user?s manual u16397ej3v0ud 1009 table 28-1. surface mounting type soldering cond itions (2/2) (2) pd703131agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703131aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703132agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703132aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703133agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703133aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703134agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703134aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd70f3134agj-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd70f3134aygj-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703136agj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) pd703136aygj-xxx-uen-a 144-pin plastic lqfp (fine pitch) (20 20) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 260 c, time: 60 seconds max. (at 220c or higher), count: 3 times or less, exposure limit: 3 days note (after that, prebake at 125c for 36 to 72 hours) ir60-363-3 wave soldering for details, contact an nec electronics sales representative. ? partial heating pin temperature: 350c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. remarks 1. products with -a at the end of the part number are lead-free products. 2. for soldering methods and conditions other than those recommended, please contact an nec electronics sales representative. 3. soldering conditions of following products are undefined. ? pd703131af1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703131ayf1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703132af1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703132ayf1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703133af1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703133ayf1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703134af1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703134ayf1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703136af1-xxx-en4: 161-pin plastic fbga (13 13) ? pd703136ayf1-xxx-en4: 161-pin plastic fbga (13 13) ? pd70f3134af1-en4: 161-pin plastic fbga (13 13) ? pd70f3134af1-en4-a: 161-pin plastic fbga (13 13) ? pd70f3134ayf1-en4: 161-pin plastic fbga (13 13) ? pd70f3134ayf1-en4-a: 161-pin plastic fbga (13 13)
user?s manual u16397ej3v0ud 1010 appendix a register index (1/9) symbol name unit page adcr0 a/d conversion result register 0 adc 624 adcr0h a/d conversion result register 0h adc 624 adcr1 a/d conversion result register 1 adc 624 adcr1h a/d conversion result register 1h adc 624 adcr2 a/d conversion result register 2 adc 624 adcr2h a/d conversion result register 2h adc 624 adcr3 a/d conversion result register 3 adc 624 adcr3h a/d conversion result register 3h adc 624 adcr4 a/d conversion result register 4 adc 624 adcr4h a/d conversion result register 4h adc 624 adcr5 a/d conversion result register 5 adc 624 adcr5h a/d conversion result register 5h adc 624 adcr6 a/d conversion result register 6 adc 624 adcr6h a/d conversion result register 6h adc 624 adcr7 a/d conversion result register 7 adc 624 adcr7h a/d conversion result register 7h adc 624 adic interrupt control register 52 intc 882 adm0 a/d converter mode register 0 adc 619 adm1 a/d converter mode register 1 adc 621 adm2 a/d converter mode register 2 adc 623 adts a/d trigger select register adc 626 ahc address hold wait control register bcu 225 asc address setup wait control register bcu 224 bcc bus cycle control register bcu 230 bcp bus cycle period control register bcu 226 bct0 bus cycle type configuration register 0 bcu 200 bct1 bus cycle type configuration register 1 bcu 200 bec endian configuration register bcu 205 bmc bus mode control register bcu 221 cb0ctl0 csib0 control register 0 csib 692 cb0ctl1 csib0 control register 1 csib 695 cb0ctl2 csib0 control register 2 csib 696 cb0rx csib0 receive data register (16 bits) csib 691 cb0rxl csib0 receive data register l (8 bits) csib 691 cb0str csib0 status register csib 698 cb0tx csib0 transmit data register (16 bits) csib 691 cb0txl csib0 transmit data r egister l (8 bits) csib 691 cb1ctl0 csib1 control register 0 csib 692 cb1ctl1 csib1 control register 1 csib 695
appendix a register index user?s manual u16397ej3v0ud 1011 (2/9) symbol name unit page cb1ctl2 csib1 control register 2 csib 696 cb1rx csib1 receive data register csib 691 cb1rxl csib1 receive data register l csib 691 cb1str csib1 status register csib 698 cb1tx csib1 transmit data register csib 691 cb1txl csib1 transmit data register l csib 691 cb2ctl0 csib2 control register 0 csib 692 cb2ctl1 csib2 control register 1 csib 695 cb2ctl2 csib2 control register 2 csib 696 cb2rx csib2 receive data register csib 691 cb2rxl csib2 receive data register l csib 691 cb2str csib2 status register csib 698 cb2tx csib2 transmit data register csib 691 cb2txl csib2 transmit data register l csib 691 cc100 capture/compare register 100 timer 535 cc101 capture/compare register 101 timer 536 ccr10 capture/compare control register 10 timer 530 ckc clock control register cg 309 cm100 compare register 100 timer 534 cm101 compare register 101 timer 534 cm10ic0 interrupt control register 30 intc 881 cm10ic1 interrupt control register 31 intc 881 cmd0 compare register d0 timer 518 cmd1 compare register d1 timer 518 cmd2 compare register d2 timer 518 cmd3 compare register d3 timer 518 cmicd0 interrupt control register 26 intc 881 cmicd1 interrupt control register 27 intc 881 cmicd2 interrupt control register 28 intc 881 cmicd3 interrupt control register 29 intc 881 corad0 correction address register 0 cpu 920 corad0h correction address register 0h cpu 920 corad0l correction address register 0l cpu 920 corad1 correction address register 1 cpu 920 corad1h correction address register 1h cpu 920 corad1l correction address register 1l cpu 920 corad2 correction address register 2 cpu 920 corad2h correction address register 2h cpu 920 corad2l correction address register 2l cpu 920 corad3 correction address register 3 cpu 920 corad3h correction address register 3h cpu 920 corad3l correction address register 3l cpu 920 corcn correction control register cpu 921 csc0 chip area select control register 0 bcu 197
appendix a register index user?s manual u16397ej3v0ud 1012 (3/9) symbol name unit page csc1 chip area select control register 1 bcu 197 csdc chip select signal delay control register bcu 202 da0cs0 d/a conversion value setting register 0 dac 654 da0cs1 d/a conversion value setting register 1 dac 654 da0m d/a converter mode register dac 653 dadc0 dma addressing control register 0 dac 818 dadc1 dma addressing control register 1 dac 818 dadc2 dma addressing control register 2 dac 818 dadc3 dma addressing control register 3 dac 818 dakw dmaak width control register dmac 827 dbc0 dma transfer count register 0 dmac 817 dbc1 dma transfer count register 1 dmac 817 dbc2 dma transfer count register 2 dmac 817 dbc3 dma transfer count register 3 dmac 817 dchc0 dma channel control register 0 dmac 820 dchc1 dma channel control register 1 dmac 820 dchc2 dma channel control register 2 dmac 820 dchc3 dma channel control register 3 dmac 820 dda0h dma destination address register 0h dmac 815 dda0l dma destination address register 0l dmac 816 dda1h dma destination address register 1h dmac 815 dda1l dma destination address register 1l dmac 816 dda2h dma destination address register 2h dmac 815 dda2l dma destination address register 2l dmac 816 dda3h dma destination address register 3h dmac 815 dda3l dma destination address register 3l dmac 816 difc dma interface control register dmac 826 dmaic0 interrupt control register 36 intc 881 dmaic1 interrupt control register 37 intc 882 dmaic2 interrupt control register 38 intc 882 dmaic3 interrupt control register 39 intc 882 dsa0h dma source address register 0h dmac 813 dsa0l dma source address register 0l dmac 814 dsa1h dma source address register 1h dmac 813 dsa1l dma source address register 1l dmac 814 dsa2h dma source address register 2h dmac 813 dsa2l dma source address register 2l dmac 814 dsa3h dma source address register 3h dmac 813 dsa3l dma source address register 3l dmac 814 dtfr0 dma trigger factor register 0 dmac 823 dtfr1 dma trigger factor register 1 dmac 823 dtfr2 dma trigger factor register 2 dmac 823 dtfr3 dma trigger factor register 3 dmac 823 dtoc dma terminal count output control register dmac 822 dwc0 data wait control register 0 bcu 222
appendix a register index user?s manual u16397ej3v0ud 1013 (4/9) symbol name unit page dwc1 data wait control register 1 bcu 222 fic dma flyby transfer idle control register dmac 231 fwc dma flyby transfer wait control register dmac 227 hza0ctl0 high impedance output control register 00 timer 560 hza0ctl1 high impedance output control register 01 timer 560 iic iic shift register i 2 c 755 iicc iic control register i 2 c 740 iiccl iic clock selection register i 2 c 751 iicx iic function expansion register i 2 c 752 iicf iic flag register i 2 c 749 iics iic status register i 2 c 746 imr0 interrupt mask register 0 intc 883 imr0h interrupt mask register 0h intc 883 imr0l interrupt mask register 0l intc 883 imr1 interrupt mask register 1 intc 883 imr1h interrupt mask register 1h intc 883 imr1l interrupt mask register 1l intc 883 imr2 interrupt mask register 2 intc 883 imr2h interrupt mask register 2h intc 883 imr2l interrupt mask register 2l intc 883 imr3 interrupt mask register 3 intc 883 imr3h interrupt mask register 3h intc 883 imr3l interrupt mask register 3l intc 883 intf0 external interrupt falling edge specification register 0 intc 887 intf1 external interrupt falling edge specification register 1 intc 888 intf2 external interrupt falling edge specification register 2 intc 889 intf3 external interrupt falling edge specification register 3 intc 890 intf5 external interrupt falling edge specification register 5 intc 891 intr0 external interrupt rising edge specification register 0 intc 887 intr1 external interrupt rising edge specification register 1 intc 888 intr2 external interrupt rising edge specification register 2 intc 889 intr3 external interrupt rising edge specification register 3 intc 890 intr5 external interrupt rising edge specification register 5 intc 891 ispr in-service priority register intc 884 lbs local bus sizing control register bcu 204 nmif nmi falling edge specification register intc 886 nmir nmi rising edge specification register intc 886 osts oscillation stabilization time select register cg 312 ovpic0 interrupt control register 32 intc 881 ovpic1 interrupt control register 34 intc 881 ovpic2 interrupt control register 35 intc 881 ovqic interrupt control register 33 intc 881 p0 port 0 register port 93 p00ic0 interrupt control register 1 intc 881 p00ic1 interrupt control register 2 intc 881
appendix a register index user?s manual u16397ej3v0ud 1014 (5/9) symbol name unit page p00ic4 interrupt control register 3 intc 881 p00ic5 interrupt control register 4 intc 881 p01ic0 interrupt control register 7 intc 881 p01ic1 interrupt control register 8 intc 881 p01ic2 interrupt control register 9 intc 881 p01ic3 interrupt control register 10 intc 881 p02ic1 interrupt control register 13 intc 881 p02ic2 interrupt control register 14 intc 881 p05ic0 interrupt control register 24 intc 881 p05ic1 interrupt control register 25 intc 881 p1 port 1 register port 101 p10ic6 interrupt control register 5 intc 881 p10ic7 interrupt control register 6 intc 881 p11ic4 interrupt control register 11 intc 881 p11ic5 interrupt control register 12 intc 881 p12ic4 interrupt control register 15 intc 881 p12ic5 interrupt control register 16 intc 881 p12ic6 interrupt control register 17 intc 881 p13ic0 interrupt control register 18 intc 881 p13ic1 interrupt control register 19 intc 881 p13ic2 interrupt control register 20 intc 881 p13ic3 interrupt control register 21 intc 881 p13ic4 interrupt control register 22 intc 881 p13ic7 interrupt control register 23 intc 881 p2 port 2 register port 108 p3 port 3 register port 119 p4 port 4 register port 129 p5 port 5 register port 135 p7 port 7 register port 140 p8 port 8 register port 142 pah port ah register port 148 pahh port ahh register port 148 pahl port ahl register port 148 pal port al register port 145 palh port alh register port 145 pall port all register port 145 pbd port bd register port 174 pcc processor clock control register cg 308 pcd port cd register port 170 pcm port cm register port 165 pcs port cs register port 155 pct port ct register port 160 pdl port dl register port 152 pdlh port dlh register port 152
appendix a register index user?s manual u16397ej3v0ud 1015 (6/9) symbol name unit page pdll port dll register port 152 pfc0 port 0 function control register port 95 pfc1 port 1 function control register port 103 pfc2 port 2 function control register port 110 pfc3 port 3 function control register port 121 pfc4 port 4 function control register port 131 pfc5 port 5 function control register port 136 pfccs port cs function control register port 157 pfcct port ct function control register port 162 pfce0 port 0 function control expansion register port 95 pfce1 port 1 function control expansion register port 103 pfce2 port 2 function control expansion register port 110 pfce3 port 3 function control expansion register port 121 pfce5 port 5 function control expansion register port 136 pm0 port 0 mode register port 93 pm1 port 1 mode register port 101 pm2 port 2 mode register port 108 pm3 port 3 mode register port 119 pm4 port 4 mode register port 129 pm5 port 5 mode register port 135 pmah port ah mode register port 149 pmahh port ah mode register h port 149 pmahl port ah mode register l port 149 pmal port al mode register port 146 pmalh port al mode register h port 146 pmall port al mode register l port 146 pmbd port bd mode register port 174 pmc0 port 0 mode control register port 94 pmc1 port 1 mode control register port 102 pmc2 port 2 mode control register port 109 pmc3 port 3 mode control register port 120 pmc4 port 4 mode control register port 130 pmc5 port 5 mode control register port 136 pmc7 port 7 mode control register port 140 pmcah port ah mode control register port 149 pmcahh port ah mode control register h port 149 pmcahl port ah mode control register l port 149 pmcal port al mode control register port 146 pmcalh port al mode control register h port 146 pmcall port al mode control register l port 146 pmcbd port bd mode control register port 175 pmccd port cd mode control register port 171 pmccm port cm mode control register port 166 pmccs port cs mode control register port 156
appendix a register index user?s manual u16397ej3v0ud 1016 (7/9) symbol name unit page pmcct port ct mode control register port 161 pmcd port cd mode register port 170 pmcdl port dl mode control register port 153 pmcdlh port dl mode control register h port 153 pmcdll port dl mode control register l port 153 pmcm port cm mode register port 165 pmcs port cs mode register port 155 pmct port ct mode register port 160 pmdl port dl mode register port 153 pmdlh port dl mode register h port 153 pmdll port dl mode register l port 153 prc page rom configuration register memc 265 prcmd command register cpu 82 prm10 prescaler mode register 10 timer 532 prscm prescaler compare register i 2 c 753 prsm prescaler mode register i 2 c 752 psc power save control register cpu 310, 905 psmr power save mode register cpu 311 rfs1 sdram refresh control register 1 memc 298 rfs3 sdram refresh control register 3 memc 298 rfs4 sdram refresh control register 4 memc 298 rfs6 sdram refresh control register 6 memc 298 scr1 sdram configuration register 1 memc 275 scr3 sdram configuration register 3 memc 275 scr4 sdram configuration register 4 memc 275 scr6 sdram configuration register 6 memc 275 seic0 interrupt control register 40 intc 882 seic1 interrupt control register 43 intc 882 seic2 interrupt control register 46 intc 882 seic3 interrupt control register 49 intc 882 sesa10 valid edge select register 10 timer 530 sric0 interrupt control register 41 intc 882 sric1 interrupt control register 44 intc 882 sric2 interrupt control register 47 intc 882 sric3 interrupt control register 50 intc 882 status10 status register 10 timer 533 stic0 interrupt control register 42 intc 882 stic1 interrupt control register 45 intc 882 stic2 interrupt control register 48 intc 882 stic3 interrupt control register 51 intc 882 sva slave address register i 2 c 755 sys system status register cpu 83 tmc10 timer control register 10 timer 529 tmcd0 timer mode control register d0 timer 520
appendix a register index user?s manual u16397ej3v0ud 1017 (8/9) symbol name unit page tmcd1 timer mode control register d1 timer 520 tmcd2 timer mode control register d2 timer 520 tmcd3 timer mode control register d3 timer 520 tmd0 timer d0 timer 517 tmd1 timer d1 timer 517 tmd2 timer d2 timer 517 tmd3 timer d3 timer 517 tmenc10 timer enc10 timer 526 tp0ccr0 tmp0 capture/compare register 0 timer 326 tp0ccr1 tmp0 capture/compare register 1 timer 328 tp0cnt tmp0 counter read buffer register timer 330 tp0ctl0 tmp0 control register 0 timer 319 tp0ctl1 tmp0 control register 1 timer 320 tp0ioc0 tmp0 i/o control register 0 timer 322 tp0ioc1 tmp0 i/o control register 1 timer 323 tp0ioc2 tmp0 i/o control register 2 timer 324 tp0opt0 tmp0 option register 0 timer 325 tp1ccr0 tmp1 capture/compare register 0 timer 326 tp1ccr1 tmp1 capture/compare register 1 timer 328 tp1cnt tmp1 counter read buffer register timer 330 tp1ctl0 tmp1 control register 0 timer 319 tp1ctl1 tmp1 control register 1 timer 320 tp1ioc0 tmp1 i/o control register 0 timer 322 tp1ioc1 tmp1 i/o control register 1 timer 323 tp1ioc2 tmp1 i/o control register 2 timer 324 tp1opt0 tmp1 option register 0 timer 325 tp2ccr0 tmp2 capture/compare register 0 timer 326 tp2ccr1 tmp2 capture/compare register 1 timer 328 tp2cnt tmp2 counter read buffer register timer 330 tp2ctl0 tmp2 control register 0 timer 319 tp2ctl1 tmp2 control register 1 timer 320 tp2ioc0 tmp2 i/o control register 0 timer 322 tp2ioc1 tmp2 i/o control register 1 timer 323 tp2ioc2 tmp2 i/o control register 2 timer 324 tp2opt0 tmp2 option register 0 timer 325 tq0ccr0 tmq0 capture/compare register 0 timer 419 tq0ccr1 tmq0 capture/compare register 1 timer 421 tq0ccr2 tmq0 capture/compare register 2 timer 423 tq0ccr3 tmq0 capture/compare register 3 timer 425 tq0cnt tmq0 counter read buffer register timer 427 tq0ctl0 tmq0 control register 0 timer 413 tq0ctl1 tmq0 control register 1 timer 414 tq0dtc tmq0 dead time compare register timer 553 tq0ioc0 tmq0 i/o control register 0 timer 415
appendix a register index user?s manual u16397ej3v0ud 1018 (9/9) symbol name unit page tq0ioc1 tmq0 i/o control register 1 timer 416 tq0ioc2 tmq0 i/o control register 2 timer 417 tq0ioc3 tmq0 i/o control register 3 timer 558 tq0opt0 tmq0 option register 0 timer 418, 554 tq0opt1 tmq0 option register 1 timer 555 tq0opt2 tmq0 option register 2 timer 556 tum10 timer unit mode register 10 timer 528 ua0ctl0 uarta0 control register 0 uarta 664 ua0ctl1 uarta0 control register 1 uarta 680 ua0ctl2 uarta0 control register 2 uarta 681 ua0opt0 uarta0 option control register 0 uarta 666 ua0rx uarta0 receive data register uarta 668 ua0str uarta0 status register uarta 666 ua0tx uarta0 transmit data register uarta 668 ua1ctl0 uarta1 control register 0 uarta 664 ua1ctl1 uarta1 control register 1 uarta 680 ua1ctl2 uarta1 control register 2 uarta 681 ua1opt0 uarta1 option control register 0 uarta 666 ua1rx uarta1 receive data register uarta 668 ua1str uarta1 status register uarta 666 ua1tx uarta1 transmit data register uarta 668 ua2ctl0 uarta2 control register 0 uarta 664 ua2ctl1 uarta2 control register 1 uarta 680 ua2ctl2 uarta2 control register 2 uarta 681 ua2opt0 uarta2 option control register 0 uarta 666 ua2rx uarta2 receive data register uarta 668 ua2str uarta2 status register uarta 666 ua2tx uarta2 transmit data register uarta 668 ua3ctl0 uarta3 control register 0 uarta 664 ua3ctl1 uarta3 control register 1 uarta 680 ua3ctl2 uarta3 control register 2 uarta 681 ua3opt0 uarta3 option control register 0 uarta 666 ua3rx uarta3 receive data register uarta 668 ua3str uarta3 status register uarta 666 ua3tx uarta3 transmit data register uarta 668 vswc system wait control register bcu 84 was write access synchronization control register bcu 220 wdcs watchdog timer clock select register wdt 610 wdres watchdog timer reset status register wdt 612, 916 wdtic interrupt control register 0 intc 881 wdtm watchdog timer mode register wdt 611
user?s manual u16397ej3v0ud 1019 appendix b instruction set list b.1 conventions (1) register symbols u sed to describe operands register symbol explanation reg1 general-purpose registers: used as source registers. reg2 general-purpose registers: used mainly as destination registers. also used as source register in some instructions. reg3 general-purpose registers: used mainly to store the remainders of division results and the higher order 32 bits of multiplication results. bit#3 3-bit data for specifying the bit number immx x bit immediate data dispx x bit displacement data regid system register number vector 5-bit data that specifies the trap vector (00h to 1fh) cccc 4-bit data that shows the conditions code sp stack pointer (sp) ep element pointer (r30) listx x item register list (2) register symbols used to describe opcodes register symbol explanation r 1-bit data of a code that specifies reg1 or regid r 1-bit data of the code that specifies reg2 w 1-bit data of the code that specifies reg3 d 1-bit displacement data i 1-bit immediate data (indicates th e higher bits of immediate data) i 1-bit immediate data cccc 4-bit data that shows the condition codes cccc 4-bit data that shows the condition codes of bcond instruction bbb 3-bit data for specifying the bit number l 1-bit data that specifies a program register in the register list s 1-bit data that specifies a system register in the register list
appendix b instruction set list user?s manual u16397ej3v0ud 1020 (3) register symbols used in operations register symbol explanation input for gr [ ] general-purpose register sr [ ] system register zero-extend (n) expand n with zeros until word length. sign-extend (n) expand n with signs until word length. load-memory (a, b) read size b data from address a. store-memory (a, b, c) write data b into address a in size c. load-memory-bit (a, b) read bit b of address a. store-memory-bit (a, b, c) write c to bit b of address a. saturated (n) execute saturated processing of n (n is a 2?s complement). if, as a result of calculations, n 7fffffffh, let it be 7fffffffh. n 80000000h, let it be 80000000h. result reflects the results in a flag. byte byte (8 bits) halfword half word (16 bits) word word (32 bits) + addition ? subtraction ll bit concatenation multiplication division % remainder from division results and logical product or logical sum xor exclusive or not logical negation logically shift left by logical shift left logically shift right by logical shift right arithmetically shift right by arithmetic shift right (4) register symbols u sed in execution clock register symbol explanation i if executing another instruction immediately a fter executing the first instruction (issue). r if repeating execution of the same instruction immedi ately after executing the first instruction (repeat). l if using the results of instruction execution in the instruction immediately afte r the execution (latency).
appendix b instruction set list user?s manual u16397ej3v0ud 1021 (5) register symbols used in flag operations identifier explanation (blank) no change 0 clear to 0 x set or cleared in accordance with the results. r previously saved values are restored. (6) condition codes condition name (cond) condition code (cccc) condition formula explanation v 0 0 0 0 ov = 1 overflow nv 1 0 0 0 ov = 0 no overflow c/l 0 0 0 1 cy = 1 carry lower (less than) nc/nl 1 0 0 1 cy = 0 no carry not lower (greater than or equal) z/e 0 0 1 0 z = 1 zero equal nz/ne 1 0 1 0 z = 0 not zero not equal nh 0 0 1 1 (cy or z) = 1 not higher (less than or equal) h 1 0 1 1 (cy or z) = 0 higher (greater than) n 0 1 0 0 s = 1 negative p 1 1 0 0 s = 0 positive t 0 1 0 1 ? always (unconditional) sa 1 1 0 1 sat = 1 saturated lt 0 1 1 0 (s xor ov) = 1 less than signed ge 1 1 1 0 (s xor ov) = 0 greater than or equal signed le 0 1 1 1 ((s xor ov) or z) = 1 less than or equal signed gt 1 1 1 1 ((s xor ov) or z) = 0 greater than signed
appendix b instruction set list user?s manual u16397ej3v0ud 1022 b.2 instruction set (in alphabetical order) (1/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat reg1,reg2 r r rr r0 01 11 0 rrrrr gr[reg2] gr[reg2]+gr[reg1] 1 1 1 add imm5,reg2 rrrrr010010iiiii gr[reg2] gr[reg2]+sign-extend(imm5) 1 1 1 addi imm16,reg1,reg2 r r rr r1 10 00 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 and reg1,reg2 r r rr r0 01 01 0 rrrrr gr[reg2] gr[reg2]and gr[reg1] 1 1 1 0 andi imm16,reg1,reg2 r r rr r1 10 11 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]and zero-extend(imm16) 1 1 1 0 0 when conditions are satisfied 3 note 2 3 note 2 3 note 2 bcond disp9 ddddd1011dddcccc note 1 if conditions are satisfied then pc pc+sign-extend(disp9) when conditions are not satisfied 1 1 1 bsh reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000010 gr[reg3] gr[reg2] (23 : 16) ll gr[reg2] (31 : 24) ll gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) 1 1 1 0 bsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000000 gr[reg3] gr[reg2] (7 : 0) ll gr[reg2] (15 : 8) ll gr [reg2] (23 : 16) ll gr[reg2] (31 : 24) 1 1 1 0 callt imm6 0000001000iiiiii ctpc pc+2(return pc) ctpsw psw adr ctbp+zero-extend(imm6 logically shift left by 1) pc ctbp+zero-extend(load-memory(adr,halfword)) 5 5 5 bit#3, disp16[reg1] 10bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,0) 3 note 3 3 note 3 3 note 3 clr1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100100 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,0) 3 note 3 3 note 3 3 note 3 cccc,imm5,reg2,reg3 rrrrr111111iiiii wwwww011000cccc0 if conditions are satisfied then gr[reg3] sign-extended(imm5) else gr[reg3] gr[reg2] 1 1 1 cmov cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 r r r r wwwww011001cccc0 if conditions are satisfied then gr[reg3] gr[reg1] else gr[reg3] gr[reg2] 1 1 1 reg1,reg2 r r rr r0 01 11 1 rrrrr result gr[reg2]?gr[reg1] 1 1 1 cmp imm5,reg2 rrrrr010011iiiii result gr[reg2]?sign-extend(imm5) 1 1 1 ctret 0000011111100000 0000000101000100 pc ctpc psw ctpsw 4 4 4 r r r r r dbret 0000011111100000 0000000101000110 pc dbpc psw dbpsw 4 4 4 r r r r r
appendix b instruction set list user?s manual u16397ej3v0ud 1023 (2/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat dbtrap 1111100001000000 dbpc pc+2 (returned pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h 4 4 4 di 0000011111100000 0000000101100000 psw.id 1 1 1 1 imm5,list12 0000011001iiiiil lllllllllll00000 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded n+1 note 4 n+1 note 4 n+1 note 4 dispose imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i l lllllllllllrrrrr note 5 sp sp+zero-extend(imm5 logically shift left by 2) gr[reg in list12] load-memory(sp,word) sp sp+4 repeat 2 steps above until all regs in list12 is loaded pc gr[reg1] n+3 note 4 n+3 note 4 n+3 note 4 div reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000000 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 35 35 35 reg1,reg2 r r rr r0 00 01 0 rrrrr gr[reg2] gr[reg2]gr[reg1] note 6 35 35 35 divh reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000000 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 35 35 35 divhu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01010000010 gr[reg2] gr[reg2]gr[reg1] note 6 gr[reg3] gr[reg2]%gr[reg1] 34 34 34 divu reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01011000010 gr[reg2] gr[reg2]gr[reg1] gr[reg3] gr[reg2]%gr[reg1] 34 34 34 ei 1000011111100000 0000000101100000 psw.id 0 1 1 1 halt 0000011111100000 0000000100100000 stop 1 1 1 hsw reg2,reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 wwwww01101000100 gr[reg3] gr[reg2](15 : 0) ll gr[reg2] (31 : 16) 1 1 1 0 jarl disp22,reg2 r r r r r 1 1 1 1 0 d d d d d d ddddddddddddddd0 note 7 gr[reg2] pc+4 pc pc+sign-extend(disp22) 3 3 3 jmp [reg1] 00000000011rrrrr pc gr[reg1] 4 4 4 jr disp22 0000011110dddddd ddddddddddddddd0 note 7 pc pc+sign-extend(disp22) 3 3 3 ld.b disp16[reg1],reg2 r r rr r1 11 00 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 11 ld.bu disp16[reg1],reg2 r r rr r1 11 10 b rrrrr dddddddddddddd1 notes 8, 10 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 11
appendix b instruction set list user?s manual u16397ej3v0ud 1024 (3/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat ld.h disp16[reg1],reg2 rrrrr111001rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 11 other than regid = psw 1 1 1 ldsr reg2,regid rrrrr111111rrrrr 0000000000100000 note 12 sr[regid] gr[reg2] regid = psw 1 1 1 ld.hu disp16[reg1],reg2 r r rr r1 11 11 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] zero-extend(load-memory(adr,halfword) 1 1 note 11 ld.w disp16[reg1],reg2 r r rr r1 11 00 1 rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) gr[reg2] load-memory(adr,word) 1 1 note 11 reg1,reg2 r r rr r0 00 00 0 rrrrr gr[reg2] gr[reg1] 1 1 1 imm5,reg2 rrrrr010000iiiii gr[reg2] sign-extend(imm5) 1 1 1 mov imm32,reg1 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii gr[reg1] imm32 2 2 2 movea imm16,reg1,reg2 r r rr r1 10 00 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+sign-extend(imm16) 1 1 1 movhi imm16,reg1,reg2 r r rr r1 10 01 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]+(imm16 ll 0 16 ) 1 1 1 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100000 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] 1 2 note 14 2 mul note 22 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii00 note 13 gr[reg3] ll gr[reg2] gr[reg2]xsign-extend(imm9) 1 2 note 14 2 reg1,reg2 r r rr r0 00 11 1 rrrrr gr[reg2] gr[reg2] note 6 xgr[reg1] note 6 1 1 2 mulh imm5,reg2 rrrrr010111iiiii gr[reg2] gr[reg2] note 6 xsign-extend(imm5) 1 1 2 mulhi imm16,reg1,reg2 r r rr r1 10 11 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] note 6 ximm16 1 1 2 reg1,reg2,reg3 r r rr r1 11 11 1 rrrrr wwwww01000100010 gr[reg3] ll gr[reg2] gr[reg2]xgr[reg1] 1 2 note 1 4 2 mulu note 22 imm9,reg2,reg3 rrrrr111111iiiii wwwww01001iiii10 note 13 gr[reg3] ll gr[reg2] gr[reg2]xzero-extend(imm9) 1 2 note 1 4 2 nop 0000000000000000 pass at least one clock cycle doing nothing. 1 1 1 not reg1,reg2 r r rr r0 00 00 1 rrrrr gr[reg2] not(gr[reg1]) 1 1 1 0 bit#3,disp16[reg1] 01bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not(load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,z flag) 3 note 3 3 note 3 3 note 3 not1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100010 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,z flag) 3 note 3 3 note 3 3 note 3
appendix b instruction set list user?s manual u16397ej3v0ud 1025 (4/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat or reg1,reg2 r r rr r0 01 00 0 rrrrr gr[reg2] gr[reg2]or gr[reg1] 1 1 1 0 ori imm16,reg1,reg2 r r rr r1 10 10 0 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1]or zero-extend(imm16) 1 1 1 0 list12,imm5 0000011110iiiiil lllllllllll00001 store-memory(sp?4,gr[reg in list12],word) sp sp?4 repeat 1 step above until all regs in list12 is stored sp sp-zero-extend(imm5) n+1 note 4 n+1 note 4 n+1 note 4 prepare list12,imm5, sp/imm note 15 0000011110iiiiil lllllllllllff011 imm16/imm32 note 16 store-memory(sp?4,gr[reg in list12],word) gr[reg in list 12] load-memory(sp,word) sp sp+4 repeat 2 step above until a ll regs in list12 is loaded pc gr[reg1] n+2 note 4 note 17 n+2 note 4 note 17 n+2 note 4 note 17 reti 0000011111100000 0000000101000000 if psw.ep=1 then pc eipc psw eipsw else if psw.np=1 then pc fepc psw fepsw else pc eipc psw eipsw 4 4 4 r r r r r reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010100000 gr[reg2] gr[reg2]arithmetically shift right by gr[reg1] 1 1 1 0 sar imm5,reg2 rrrrr010101iiiii gr[reg2] gr[reg2]arithmetically shift right by zero-extend (imm5) 1 1 1 0 sasf cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then gr[reg2] (gr[reg2]logically shift left by 1) or 00000001h else gr[reg2] (gr[reg2]logically shift left by 1) or 00000000h 1 1 1 reg1,reg2 r r rr r0 00 11 0 rrrrr gr[reg2] saturated(gr[reg2]+gr[reg1]) 1 1 1 satadd imm5,reg2 rrrrr010001iiiii gr[reg2] saturated(gr[reg2]+sign-extend(imm5) 1 1 1 satsub reg1,reg2 r r rr r0 00 10 1 rrrrr gr[reg2] saturated(gr[reg2]?gr[reg1]) 1 1 1 satsubi imm16,reg1,reg2 r r rr r1 10 01 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] saturated(gr[reg1]?sign-extend(imm16) 1 1 1 satsubr reg1,reg2 r r rr r0 00 10 0 rrrrr gr[reg2] saturated(gr[reg1]?gr[reg2]) 1 1 1 setf cccc,reg2 rrrrr1111110cccc 0000000000000000 if conditions are satisfied then gr[reg2] 00000001h else gr[reg2] 00000000h 1 1 1
appendix b instruction set list user?s manual u16397ej3v0ud 1026 (5/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat bit#3,disp16[reg1] 00bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit(adr,bit#3)) store-memory-bit(adr,bit#3,1) 3 note 3 3 note 3 3 note 3 set1 reg2,[reg1] r r rr r1 11 11 1 rrrrr 0000000011100000 adr gr[reg1] z flag not(load-memory-bit(adr,reg2)) store-memory-bit(adr,reg2,1) 3 note 3 3 note 3 3 note 3 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000011000000 gr[reg2] gr[reg2] logically shift left by gr[reg1] 1 1 1 0 shl imm5,reg2 rrrrr010110iiiii gr[reg2] gr[reg2] logically shift left by zero-extend(imm5) 1 1 1 0 reg1,reg2 r r rr r1 11 11 1 rrrrr 0000000010000000 gr[reg2] gr[reg2] logically shift right by gr[reg1] 1 1 1 0 shr imm5,reg2 rrrrr010100iiiii gr[reg2] gr[reg2] logically shift right by zero-extend(imm5) 1 1 1 0 sld.b disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d adr ep+zero-extend(disp7) gr[reg2] sign-extend(load-memory(adr,byte)) 1 1 note 9 sld.bu disp4[ep],reg2 rrrrr0000110dddd note 18 adr ep+zero-extend(disp4) gr[reg2] zero-extend(load-memory(adr,byte)) 1 1 note 9 sld.h disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d note 19 adr ep+zero-extend(disp8) gr[reg2] sign-extend(load-memory(adr,halfword)) 1 1 note 9 sld.hu disp5[ep],reg2 rrrrr0000111dddd notes 18, 20 adr ep+zero-extend(disp5) gr[reg2] zero-extend(load-memory(adr,halfword)) 1 1 note 9 sld.w disp8[ep],reg2 rrrrr1010dddddd0 note 21 adr ep+zero-extend(disp8) gr[reg2] load-memory(adr,word) 1 1 note 9 sst.b reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d adr ep+zero-extend(disp7) store-memory(adr,gr[reg2],byte) 1 1 1 sst.h reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d note 19 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],halfword) 1 1 1 sst.w reg2,disp8[ep] rrrrr1010dddddd1 note 21 adr ep+zero-extend(disp8) store-memory(adr,gr[reg2],word) 1 1 1 st.b reg2,disp16[reg1] r r rr r1 11 01 0 rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) store-memory(adr,gr[reg2],byte) 1 1 1 st.h reg2,disp16[reg1] r r rr r1 11 01 1 rrrrr ddddddddddddddd0 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], halfword) 1 1 1 st.w reg2,disp16[reg1] rrrrr111011rrrrr ddddddddddddddd1 note 8 adr gr[reg1]+sign-extend(disp16) store-memory (adr,gr[reg2], word) 1 1 1 stsr regid,reg2 r r rr r1 11 11 1 rrrrr 0000000001000000 gr[reg2] sr[regid] 1 1 1
appendix b instruction set list user?s manual u16397ej3v0ud 1027 (6/6) execution clock flags mnemonic operand opcode operation i r l cy ov s z sat sub reg1,reg2 r r rr r0 01 10 1 rrrrr gr[reg2] gr[reg2]?gr[reg1] 1 1 1 subr reg1,reg2 r r rr r0 01 10 0 rrrrr gr[reg2] gr[reg1]?gr[reg2] 1 1 1 switch reg1 00000000010rrrrr adr (pc+2) + (gr [reg1] logically shift left by 1) pc (pc+2) + (sign-extend (load-memory (adr,halfword)) logically shift left by 1 5 5 5 sxb reg1 00000000101rrrrr gr[reg1] sign-extend (gr[reg1] (7 : 0)) 1 1 1 sxh reg1 00000000111rrrrr gr[reg1] sign-extend (gr[reg1] (15 : 0)) 1 1 1 trap vector 00000111111iiiii 0000000100000000 eipc pc+4 (return pc) eipsw psw ecr.eicc exception code (40h to 4fh, 50h to 5fh) psw.ep 1 psw.id 1 pc 00000040h (when vector is 00h to 0fh (exception code: 40h to 4fh)) 00000050h (when vector is 10h to 1fh (exception code: 50h to 5fh)) 4 4 4 tst reg1,reg2 r r rr r0 01 01 1 rrrrr result gr[reg2] and gr[reg1] 1 1 1 0 bit#3,disp16[reg1] 11bbb111110rrrrr dddddddddddddddd adr gr[reg1]+sign-extend(disp16) z flag not (load-memory-bit (adr,bit#3)) 3 note 3 3 note 3 3 note 3 tst1 reg2, [reg1] r r rr r1 11 11 1 rrrrr 0000000011100110 adr gr[reg1] z flag not (load-memory-bit (adr,reg2)) 3 note 3 3 note 3 3 note 3 xor reg1,reg2 r r rr r0 01 00 1 rrrrr gr[reg2] gr[reg2] xor gr[reg1] 1 1 1 0 xori imm16,reg1,reg2 r r rr r1 10 10 1 rrrrr iiiiiiiiiiiiiiii gr[reg2] gr[reg1] xor zero-extend (imm16) 1 1 1 0 zxb reg1 00000000100rrrrr gr[reg1] zero-extend (gr[reg1] (7 : 0)) 1 1 1 zxh reg1 00000000110rrrrr gr[reg1] zero-extend (gr[reg1] (15 : 0)) 1 1 1 notes 1. dddddddd: higher 8 bits of disp9. 2. 4 if there is an instruction that rewrites the contents of the psw immediately before. 3. if there is no wait state (3 + the number of read access wait states). 4. n is the total number of list12 load registers. (a ccording to the number of wait states. also, if there are no wait states, n is the total number of list12 registers. if n = 0, same operation as when n = 1) 5. rrrrr: other than 00000. 6. the lower halfword data only are valid. 7. ddddddddddddddddddddd: the higher 21 bits of disp22. 8. ddddddddddddddd: the higher 15 bits of disp16. 9. according to the number of wait stat es (1 if there are no wait states). 10. b: bit 0 of disp16. 11. according to the number of wait stat es (2 if there are no wait states).
appendix b instruction set list user?s manual u16397ej3v0ud 1028 notes 12. in this instruction, for convenience of mnemonic descr iption, the source register is made reg2, but the reg1 field is used in the opcode. therefore, the m eaning of register specific ation in the mnemonic description and in the opcode differs from other instructions. rrrrr = regid specification rrrrr = reg2 specification 13. iiiii: lower 5 bits of imm9. iiii: higher 4 bits of imm9. 14. in the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register) or reg3 = r0 (the higher 32 bits of the results are not wri tten in the register), shortened by 1 clock. 15. sp/imm: specified by bits 19 and 20 of the sub-opcode. 16. ff = 00: load sp in ep. 01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: load 32-bit immediate data (bits 63 to 32) in ep. 17. if imm = imm32, n + 3 clocks. 18. rrrrr: other than 00 000. 19. ddddddd: higher 7 bits of disp8. 20. dddd: higher 4 bits of disp5. 21. dddddd: higher 6 bits of disp8. 22. do not make a combination that satisfies all the following conditions when using the ?mul reg1, reg2, reg3? instruction and ?mulu reg1, reg2, reg3? in struction. operation is not guaranteed when an instruction that satisfies the fo llowing conditions is executed. ? reg1 = reg3 ? reg1 reg2 ? reg1 r0 ? reg3 r0
user?s manual u16397ej3v0ud 1029 appendix c revision history c.1 major revisions in this edition (1/5) page description throughout ? addition of part numbers pd703136a, 703136ay ? deletion of part numbers pd703131, 703131y, 703132, 703132y, 703133, 703133y, 703134, 703134y, 70f3134, 70f3134y ? addition of following lead-free products pd703131agj-xxx-uen-a, 703131aygj- xxx-uen-a, 703132agj-xxx-uen-a, 703132aygj-xxx-uen-a, 703133agj-xx x-uen-a, 703133aygj-xx x-uen-a, 703134agj-xxx-uen-a, 703134aygj-xxx-uen-a, 70f3134agj-uen-a, 70 f3134aygj-uen-a, 70f3134af1-en4-a, 70f3134ayf1-en4-a ? under development mass production pd703131agj-xxx-uen, 703131aygj-xxx-uen, 703132agj-xxx-uen, 703132aygj-xxx-uen, 703133agj-xxx-uen, 703133 aygj-xxx-uen, 703134a gj-xxx-uen, 703134aygj-xxx-uen p. 21 modification of description in table 1-1 v850e/ma3 product list p. 22 addition of description to inte rnal memory of memory space in 1.2 features p. 24 modification of description in 1.4 ordering information p. 30 addition of note to 1.6.1 internal block diagram p. 32 addition of description to 1.6.2 (4) ram p. 53 modification of note in table 3-2 system register numbers p. 58 modification of description in 3.2.2 (6) exception/debug trap st atus saving registers (dbpc, dbpsw) p. 65 addition of 3.4.5 (2) (a) internal ram (8 kb) p. 69 modification of description in figure 3-10 recommended memory map p. 77 deletion of note in 3.4.8 on-chip peripheral i/o registers p. 80 addition of note to 3.4.8 on-chip peripheral i/o registers p. 81 modification of caution in 3.4.9 (1) setting data to special registers p. 83 addition of (iii) to 3.4.9 (3) (a) set condition (prerr flag = 1) p. 84 modification of description in 3.4.10 system wait control register (vswc) p. 88 modification of description in table 4-2 writing/reading pn register p. 190 addition of description to 4.6.2 cautions on bit manipulation instruction for port n register (pn) p. 196 addition of note to 5.3 memory block function p. 202 partial deletion of description in 5.4.2 (1) chip select signal delay control register (csdc) p. 300 addition of caution to 6.3.6 (1) (a) notes on changing refresh interval p. 319 modification of note in 8.4 (1) tmpn control register 0 (tpnctl0) p. 321 addition of caution in 8.4 (2) tmpn control register 1 (tpnctl1) p. 322 addition of caution to 8.4 (3) tmpn i/o control register 0 (tpnioc0) p. 323 addition of caution to 8.4 (4) tmpn i/o control register 1 (tpnioc1) p. 325 addition of description to 8.4 (6) tmpn option register 0 (tpnopt0)
appendix c revision history user?s manual u16397ej3v0ud 1030 (2/5) page description p. 327 addition of description to 8.4 (7) (a) function as compare register p. 327 addition of description to 8.4 (7) (b) function as capture register p. 329 addition of description to 8.4 (8) (a) function as compare register p. 329 addition of description to 8.4 (8) (b) function as capture register p. 334 addition of note to figure 8-2 flowchart of basic operation for anytime write p. 337 addition of note to figure 8-4 flowchart of basic operation for batch write pp. 340, 341 modification of description in figure 8-8 register setting for interval timer mode operation p. 342 addition of description to figure 8-9 software processing flow in interval timer mode p. 349 addition of 8.6.1 (3) operation by external event count input (evtpn) p. 350 addition of description to 8.6.2 external event count mode (tpnmd2 to tpnmd0 bits = 001) p. 354 addition of caution to 8.6.2 (2) operation timing in external event count mode p. 359 modification of figure 8-21 basic timing in external trigger pulse output mode p. 359 addition of description to 8.6.3 external trigger pulse output mode (tpnmd2 to tpnmd0 bits = 010) p. 360 addition of note to figure 8-22 setting of registers in external trigger pulse output mode p. 366 modification of description in 8.6.3 (2) (b) 0%/100% output of pwm waveform p. 372 addition of note to figure 8-26 setting of registers in one-shot pulse output mode p. 374 modification of figure 8-27 software processing flow in one-shot pulse output mode p. 375 modification of 8.6.4 (2) (a) note on rewriting tpnccra register p. 379 addition of note to figure 8-30 setting of registers in pwm output mode p. 384 modification of description in 8.6.5 (2) (b) 0%/100% output of pwm waveform p. 404 modification of description in 8.6.7 pulse width measurement mode (tpnmd2 to tpnmd0 bits = 110) p. 413 modification of note in 9.4 (1) tmq0 control register 0 (tq0ctl0) p. 415 addition of caution to 9.4 (3) tmq0 i/o control register 0 (tq0ioc0) p. 416 addition of caution to 9.4 (4) tmq0 i/o control register 1 (tq0ioc1) p. 418 addition of description to 9.4 (6) tmq0 option register 0 (tq0opt0) p. 420 addition of description to 9.4 (7) (a) function as compare register p. 420 addition of description to 9.4 (7) (b) function as capture register p. 422 addition of description to 9.4 (8) (a) function as compare register p. 422 addition of description to 9.4 (8) (b) function as capture register p. 424 addition of description to 9.4 (9) (a) function as compare register p. 424 addition of description to 9.4 (9) (b) function as capture register p. 426 addition of description to 9.4 (10) (a) function as compare register p. 426 addition of description to 9.4 (10) (b) function as capture register p. 431 addition of note to figure 9-2 flowchart of basic operation for anytime write p. 434 addition of note to figure 9-4 flowchart of basic operation for batch write pp. 437, 438 modification of description in figure 9-8 register setting for interval timer mode operation p. 440 addition of description to figure 9-9 software processing flow in interval timer mode p. 446 addition of 9.6.1 (3) operation by external event count input (evtq) p. 447 addition of description to 9.6.2 external event count mode (tq0md2 to tq0md0 bits = 001) p. 451 addition of caution to 9.6.2 (2) operation timing in external event count mode p. 457 modification of figure 9-21 basic timing in external trigger pulse output mode
appendix c revision history user?s manual u16397ej3v0ud 1031 (3/5) page description p. 458 addition of description to 9.6.3 external trigger pulse output mode (tq0md2 to tq0md0 bits = 010) p. 459 addition of note to figure 9-22 setting of registers in external trigger pulse output mode p. 465 modification of description in 9.6.3 (2) (b) 0%/100% output of pwm waveform p. 472 addition of note to figure 9-26 setting of registers in one-shot pulse output mode pp. 474, 475 modification of figure 9-27 software processing flow in one-shot pulse output mode p. 481 addition of note to figure 9-30 setting of registers in pwm output mode p. 487 modification of description in 9.6.5 (2) (b) 0%/100% output of pwm waveform p. 510 modification of description in 9.6.7 pulse width measurement mode (tq0md2 to tq0md0 bits = 110) p. 551 modification of figure 12-1 block diagram of motor control p. 552 modification of figure 12-2 tmq0 option p. 556 addition of caution to 12.3 (3) tmq0 option register 2 (tq0opt2) p. 565 modification of figure 12-5 outline of 6-phase pwm output mode p. 566 modification of description in figure 12-6 timing chart of 6-phase pwm output mode p. 568 modification of figure 12-7 interrupt and up/down flag p. 576 addition of description to 12.4.3 interrupt culling function p. 601 addition of description to 12.4.5 (1) (b) setting of tmq0 register p. 647 addition of 14.8.7 variation of a/d conversion results p. 650 addition of description to 14.9 (6) differential linearity error p. 656 deletion of note from (6) in 15.4.3 cautions pp. 664, 665 modification of description in 16.4 (1) uartan control register 0 (uanctl0) p. 666 addition of description to 16.4 (4) uartan option control register 0 (uanopt0) p. 666 deletion of caution in 16.4 (5) uartan status register (uanstr) p. 675 modification of description in 16.6.4 uart reception p. 676 modification of caution in 16.6.5 reception errors p. 693 modification of description in 17.4 (1) csibn control register 0 (cbnctl0) p. 694 addition of 17.4 (1) (a) how to use cbnsce bit p. 698 addition of caution to 17.4 (4) csibn status register (cbnstr) p. 699 addition of 17.5.1 single transfer mode (master mode, transmission mode) p. 701 addition of 17.5.2 single transfer mode (master mode, reception mode) p. 703 addition of 17.5.3 single transfer mode (master mode, transmission/reception mode) p. 705 addition of 17.5.4 single transfer mode (slave mode, transmission mode) p. 707 addition of 17.5.5 single transfer mode (slave mode, reception mode) p. 709 addition of 17.5.6 single transfer mode (slave mode, transmission/reception mode) p. 711 addition of 17.5.7 continuous transfer mode (master mode, transmission mode) p. 713 addition of 17.5.8 continuous transfer mode (master mode, reception mode) p. 716 addition of 17.5.9 continuous transfer mode (master mode, transmission/reception mode) p. 720 addition of 17.5.10 continuous transfer mode (slave mode, transmission mode) p. 722 addition of 17.5.11 continuous transfer mode (slave mode, reception mode) p. 725 addition of 17.5.12 continuous transfer mode (slave mode, transmission/reception mode) p. 729 addition of 17.5.13 reception error pp. 730, 731 addition of caution to 17.5.14 clock timing
appendix c revision history user?s manual u16397ej3v0ud 1032 (4/5) page description p. 736 modification of figure 18-2 i 2 c block diagram p. 739 addition of 18.3 (13) stop condition generator pp. 740 to 744 modification of description in 18.4 (1) iic control register (iicc) pp. 746, 747 modification of description in 18.4 (2) iic status register (iics) p. 750 addition of description to 18.4 (3) iic flag register (iicf) p. 751 addition of description to 18.4 (4) iic clock selection register (iiccl) p. 752 addition of description to 18.4 (5) iic function expansion register (iicx) p. 753 addition of description to 18.4 (7) prescaler compare register (prscm) p. 755 addition of description to 18.4 (9) iic shift register (iic) p. 755 addition of description to 18.4 (10) slave address register (sva) p. 764 addition of 18.6.7 wait state cancellation method p. 765 modification of description in 18.7.1 (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) p. 766 modification of description in 18.7.1 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) p. 767 addition of note to 18.7.1 (3) <1> when wtim bit = 0 p. 771 modification of description in 18.7.2 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop p. 775 modification of description in 18.7.3 (4) start ~ code ~ data ~ start ~ address ~ data ~ stop p. 776 addition of description to 18.7.5 arbitration loss operation (operation as slave after arbitration loss) p. 778 addition of description to 18.7.6 operation when arbitration loss occurs (no communication after arbitration loss) p. 782 addition of 18.7.6 (6) <1> when wtim bit = 0 p. 783 addition of 18.7.6 (7) <1> when wtim bit = 0 p. 784 addition of 18.7.6 (8) <1> when wtim bit = 0 p. 787 addition of description to (3) in 18.11 extension code pp. 790, 791 modification of description in 18.14.1 when communication reservation function is enabled (iicf.iicrsv bit = 0) p. 794 addition of table 18-8 wait periods p. 795 addition of (3) to (6) in 18.15 cautions p. 796 addition of description in 18.16 communication operations p. 797 modification of description in 18.16.1 master operation in single master system p. 798 modification of description in 18.16.2 master operation in multimaster system p. 802 modification of figure 18-19 slave operation flowchart (1) p. 803 modification of figure 18-20 slave operation flowchart (2) pp. 805 to 807 modification of figure 18-21 example of master to slave communication (when 9-clock wait is selected for both master and slave) pp. 808 to 810 modification of figure 18-22 example of slave to master communication (when 8-clock (master)/9- clock (slave) wait is selected) p. 826 addition of caution to 19.3.8 dma interface control register (difc) p. 842 modification of description in table 19-2 minimum value of active width of dmaakn signal during 2- cycle transfer pp. 851, 852 modification of description in figure 19-18 timing during dma flyby transfer (external i/o sram) p. 861 modification of description in table 19-5 number of minimum execution internal system clocks in dma cycle
appendix c revision history user?s manual u16397ej3v0ud 1033 (5/5) page description p. 862 deletion of caution in 19.14 maximum response time for dma transfer request p. 863 deletion of (8) and (9) in 19.15 cautions p. 865 modification of description in table 20-1 interrupt source list p. 909 modification of description in table 21-5 operation status in idle mode p. 911 modification of description in table 21-7 operation status in software stop mode p. 918 addition of caution to figure 22-2 reset operation at power on p. 921 deletion and modification of caution in 23.3 rom correction operation and program flow p. 935 deletion of description in 24.4 cautions p. 960 addition of supply current specifications of mask rom versions in normal operation mode (i dd1 ) and halt mode (i dd2 ) to dc characteristics in 26.1 normal operation mode p. 964 addition of remark to (1) clock timing of ac characteristics in 26.1 normal operation mode p. 969 modification of specifications of wait hold time (from bcyst ) (t hbsw ) and deletion of note in (4) (b) read timing (sram, external rom, external i/o) of ac characteristics in 26.1 normal operation mode p. 971 modification of specifications of wait hold time (from bcyst ) (t hbsw ) and deletion of note in (4) (c) write timing (sram, external rom, external i/o) of ac characteristics in 26.1 normal operation mode p. 973 modification of specifications of wait hold time (from bcyst ) (t hbsw ) and deletion of note in (4) (d) dma flyby transfer timing (sram external i/o transfer) of ac characteristics in 26.1 normal operation mode p. 975 modification of specifications of wait hold time (from bcyst ) (t hbsw ) and delay time from iord to dmaakm (t drdda ), and deletion of note in (4) (e) dma flyby transfer timing (external i/o sram transfer) of ac characteristics in 26.1 normal operation mode p. 994 addition of note to (11) timer p (tmp), timer q (tmq) timing of ac characteristics in 26.1 normal operation mode p. 1003 addition of 26.2 power-on/off sequence p. 1005 addition of serial write operation characteristics to 26.3 flash memory programming mode ( pd70f3134a, 70f3134ay only) p. 1008 addition of chapter 28 recommended soldering conditions p. 1034 addition of c.2 revision history of preceding editions
appendix c revision history user?s manual u16397ej3v0ud 1034 c.2 revision history of preceding editions here is the revision history of the preceding editi ons. chapter indicates the chapter of each edition. (1/6) edition description chapter ? modification of description on out put from the scl and sda pins n-ch open drain output dummy open drain output (p-ch side is always off) ? addition of part numbers pd703131a, 703131ay, 703132a, 703132ay, 703133a, 703133ay, 703134a, 703134ay, 70f3134a, 70f3134ay ? under development mass production pd703131gj-xxx-uen, pd703132gj-xxx-uen, pd70f3134gj-uen, pd70f3134agj-uen, pd70f3134ygj-uen, pd70f3134aygj-uen ? addition of registers chip select signal delay control register (csdc) dmaak width control register (dakw) write access synchronization control register (was) throughout addition of table 1-1 v850e/ma3 product list modification of description in 1.4 ordering information chapter 1 introduction addition of caution to 2.4 pin i/o circuits chapter 2 pin functions addition of note to table 3-2 system register numbers addition of note to 3.4.8 on-chip peripheral i/o registers modification of description in 3.4.9 special registers modification of description in 3.4.9 (1) setting data to special registers addition of remark to 3.4.10 system wait control register (vswc) addition of description to 3.4.11 (1) registers to be set first addition of description to 3.4.11 (2) restriction on conflict between sld instruction and interrupt request chapter 3 cpu function addition of caution to table 4-3 alternate-function pins of port 0 addition of caution to table 4-4 alternate-function pins of port 1 modification of figure 4-7 block diagram of p10 to p13 pins addition of description to 4.3.3 port 2 addition of caution to table 4-5 alternate-function pins of port 2 modification of figure 4-12 block diagram of p25 pin addition of caution to table 4-6 alternate-function pins of port 3 modification of note in 4.3.4 (1) (f) setting of alternate functions of port 3 pins modification of figure 4-18 block diagram of p33 pin modification of figure 4-20 block diagram of p37 pin addition of caution to table 4-7 alternate-function pins of port 4 addition of caution to table 4-8 alternate-function pins of port 5 addition of caution to 4.3.13 (1) (d) port ct function control register (pfcct) modification of note in table 4-19 using alternate function of port pins (4/9) addition of note in table 4-19 using alternate function of port pins (8/9) modification of caution 2 in table 4-21 noise elimination time of timer enc1 input pins 3rd modification of description in 4.6 cautions chapter 4 port functions
appendix c revision history user?s manual u16397ej3v0ud 1035 (2/6) edition description chapter modification of caution 1 in 5.4.1 (1) bus cycle type configuration registers 0, 1 (bct0, bct1) change of the number of clocks for operand data access to internal rom in the table in 5.5.1 number of clocks for access addition of 5.6 write buffer function addition of caution 4 to 5.8.1 (2) address setup wait control register (asc) modification of bit description in 5.8.1 (5) dma flyby transfer wait control register (fwc) modification of description in table 5-2 (a) in separate bus mode addition of 5.10.4 bus hold timing addition of 5.10.5 bus hold timing (sram) addition of 5.10.6 bus hold timing (sdram) deletion of description in 5.11 bus priority chapter 5 bus control function modification of timing in figure 6-3 (e) write (32-bit access (1/2)) modification of timing in figure 6-3 (f) write (16-bit access (1/2)) addition of description to figure 6-4 (b) read (successive 16-bit access) modification of description in 6.2.3 on-page modification of description on register in 6.2.4 page rom configuration register (prc) addition of 6.2.5 page rom access deletion of a part of description on cas latency in 6.3.1 features addition of 6.3.3 (1) output of each address and connection of sdram and (2) bank address output modification of caution 4 and description on register in 6.3.4 sdram configuration registers 1, 3, 4, 6 (scr1, scr3, scr4, scr6) addition of figure 6-10 sdram single read cycle deletion of a part of description in 6.3.5 (2) sdram single write cycle addition of figure 6-11 sdram single write cycle deletion of a part of description in 6.3.5 (3) (c) cas latency setting when read addition of figure 6-12 sdram access timing modification of description in 6.3.6 (1) sdram refresh control registers 1, 3, 4, 6 (rfs1, rfs3, rfs4, rfs6) addition of figure 6-14 cbr (automatic) refresh cycle (16-bit bus width) addition of figure 6-15 self timing (16-bit bus width) modification of description in 6.3.8 sdram initialization sequence addition of figure 6-16 sdram register write operation timing (16-bit bus width) chapter 6 memory access control function modification of cautions in 7.3 (2) clock control register (ckc) modification and addition of notes and addition of caution 2 in 7.3 (3) power save control register (psc) addition of caution 4 to 7.3 (5) oscillation stabilization time select register (osts) chapter 7 clock generator modification of chapter 8 16-bit timer/event counter p (tmp) chapter 8 16-bit timer/event counter p (tmp) 3rd modification of chapter 9 16-bit timer/event counter q (tmq) chapter 9 16-bit timer/event counter q (tmq)
appendix c revision history user?s manual u16397ej3v0ud 1036 (3/6) edition description chapter modification of description in 11.4 (5) prescaler mode register 10 (prm10) addition of description to 11.5.1 (5) timer output operation modification of description in table 11-4 list of count operations in udc mode chapter 11 16-bit 2-phase encoder input up/down counter/general -purpose timer (tmenc1) modification of description in 12.1 functional overview modification of figure 12-1 block diagram of motor control modification of figure 12-2 tmq0 option addition of caution to 12.3 (3) tmq0 option register 2 (tq0opt2) addition of description to 12.3 (4) tmq0i/o control register 3 (tq0ioc3) modification of description in 12.3 (5) high-impedance output control registers 00, 01 (hza0ctln) modification of figure 12-5 outline of 6-phase pwm output mode deletion from cautions and modification in figure 12-6 timing chart of 6-phase pwm output mode modification of figure 12-7 interrupt and up/down flag modification of description in figure 12-12 (b) in vicinity of 0% output (tq0ccrm register = i ( m + 1 ( a/2, tq0ccr0 register = m, tq0dtc register = a) modification of description in figure 12-13 (b) in vicinity of 100% output (tq0ccrm register = i ( a/2, tq0ccr0 register = m, tq0dtc register = a) modification of caution in 12.4.3 interrupt culling function deletion of a portion of the timings in figure 12-18 crest/valley interrupt output deletion of a portion of the timings in figure 12-19 crest interrupt output deletion of a portion of the timings in figure 12-20 valley interrupt output addition of description on batch rewrite mode (transfer mode) in 12.4.4 operation to rewrite register with transfer function modification of note in figure 12-21 timing of reflecting rewritten value addition of description to 12.4.4 (2) batch rewrite mode (transfer mode) modification of description in figure 12-26 basic operation in batch mode modification of description in 12.4.4 (2) (d) transferring tq0opt1 register value addition of description to 12.4.4 (3) intermittent batch rewrite mode (transfer culling mode) modification of description in figure 12-31 basic operation in intermittent batch rewrite mode modification of figure 12-34 rewriting tq0ccr1 register (tq0opt1.tq0ice bit = 1, tq0opt1.tq0ioe bit = 0, tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00001) modification of figure 12-35 rewriting tq0ccr1 register (tq0opt1.tq0ice bit = 1, tq0opt1.tq0ioe bit = 1, tq0opt1.tq0id4 to tq0opt1.tq0id0 bits = 00001) modification of description in 12.4.4 (4) rewriting tq0opt0.tq0cms bit addition of description to 12.4.5 (1) (b) setting of tmq0 register chapter 12 motor control function modification of note 2 in 13.3 (2) watchdog timer mode register (wdtm) deletion of description in 13.4.1 operation as watchdog timer 3rd deletion of description in 13.4.2 operation as interval timer chapter 13 watchdog timer functions
appendix c revision history user?s manual u16397ej3v0ud 1037 (4/6) edition description chapter addition of description to 14.2 (13) av dd0 pin modification of caution 2 in 14.3 (3) a/d converter mode register 2 (adm2) addition of figure 14-12 timer trigger scan operation timing: 8-channel scan (ani0 to ani7) chapter 14 a/d converter modification of descript ion on settling time in 15.1 functions addition of caution to 15.3 (1) d/a converter mode register (da0m) addition of caution to 15.3 (2) d/a conversion value setting registers 0, 1 (da0cs0, da0cs1) modification of (5) and addition of (6) in 15.4.3 cautions chapter 15 d/a converter modification of note in figure 16-2 uarta2/csib2 mode switch settings modification of note in figure 16-3. uarta3/i 2 c mode switch settings modification of description in 16.4 (1) uartan control register 0 (uanctl0) addition of caution in 16.4 (5) uartan status register (uanstr) modification of cautions in 16.6.4 uart reception addition of caution in 16.6.5 reception errors modification of figure 16-10 noise filter circuit addition of figure 16-11 timing of rxdn signal judged as noise modification of caution in 16.7 (2) uartan control register 1 (uanctl1) modification of caution in 16.7 (3) uartan control register 2 (uanctl2) modification of description in table 16-3 baud rate generator setting data addition of 16.8 cautions chapter 16 asynchronous serial interface a (uarta) modification of note in figure 17-2 uarta2/csib2 mode switch settings addition of remark to 17.3 (2) csibn transmit data register (cbntx) modification of description in 17.4 (1) csibn control register 0 (cbnctl0) modification of caution in 17.4 (2) csibn control register 1 (cbnctl1) modification of description in 17.5 operation modification of description in 17.6 (1) sckn pin modification of description in 17.7 operation flow chapter 17 clocked serial interface b (csib) modification of description in chapter 18 i 2 c bus modification of note in figure 18-1 uarta3/i 2 c mode switch settings modification of description in 18.2 (2) i 2 c bus mode (multimaster supported) modification of figure 18-2 i 2 c block diagram modification of description in 18.4 (1) iic control register (iicc) modification of description in 18.4 (4) iic clock selection register (iiccl) addition of description in 18.4 (9) iic shift register (iic) modification of description in 18.5.1 pin configuration addition of caution to 18.6.1 start condition addition of description in figure 18-11 wait signal modification of notes in table 18-3 intiic signal generation timing and wait control 3rd addition of description on sl ave device operation in 18.8 (1) during address transmission/reception chapter 18 i 2 c bus
appendix c revision history user?s manual u16397ej3v0ud 1038 (5/6) edition description chapter addition of 18.14.2 when communication reservation function is disabled (iicf.iicrsv bit = 1) modification of description in 18.15 (1) when iicf.stcen bit = 0 addition of description to 18.15 (2) when iicf.stcen bit = 1 modification of description in 18.16 communication operations modification of description in figure 18-22 (c) stop condition chapter 18 i 2 c bus deletion of description in 19.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) deletion of description in 19.3.2 dma destination address registers 0 to 3 (dda0 to dda3) deletion of description in 19.3.3 dma transfer count registers 0 to 3 (dbc0 to dbc3) addition of caution 5 and modification of description in 19.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) addition of caution and modification of description in 19.3.6 dma terminal count output control register (dtoc) modification and addition of cautions in 19.3.7 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) modification of description in 19.3.8 dma interface control register (difc) addition of 19.3.9 dmaak width control register (dakw) addition of description and figure to 19.5.1 2-cycle transfer addition of description and figure to 19.5.2 flyby transfer addition of note 4 and caution 4 in table 19-3 relationship between transfer type and transfer object addition of description in 19.8 (2) during dma transfer (p eriod start of dma transfer to completion of dma transfer) modification of description in 19.13 times related to dma transfer modification of description in 19.14 maximum response time for dma transfer request modification of description in 19.15 (6) dma start factors modification of description in 19.15 (8) restrictions related to automatic clearing of dchcn.tcn bit (non-a products only (see table 1-1)) modification of description in 19.15 (9) restrictions related to dma transfer when the number of transfers is set to two or more (non-a products only (see table 1-1)) chapter 19 dma functions (dma controller) addition of 20.2.2 (2) with intwdt signal modification of caution in 20.3.6 in-service priority register (ispr) addition of caution to 20.4.2 edge detection addition of caution to 20.6.2 (2) restore modification of description in 20.9 periods in which cpu does not acknowledge interrupts addition of (2) to 20.10 cautions chapter 20 interrupt/ exception processing function modification of description in table 21-1 standby modes addition and modification of notes in figure 21-1 status transition addition of notes and caution 2 to 21.2 (1) power save control register (psc) addition of caution 2 in 21.3.1 setting and operation status modification of description in 21.3.2 releasing halt mode 3rd modification of caution in 21.4.1 setting and operation status chapter 21 standby function
appendix c revision history user?s manual u16397ej3v0ud 1039 (6/6) edition description chapter addition of description to 21.4.2 releasing idle mode addition of caution and description to 21.4.2 (1) releasing idle mode by non-maskable interrupt request signal (nmi pin input) or unmasked maskable interrupt request signal modification of description in table 21-5 operation status in idle mode modification of caution in 21.5.1 setting and operation status addition of description in 21.5.2 releasing software stop mode addition of caution and description to 21.5.2 (1) releasing software stop mode by non- maskable interrupt request signal (nmi pin input) or unmasked maskable interrupt request signal modification of description in table 21-7 operation status in software stop mode addition of 21.7 procedure for setting and restoring from idle and software stop modes chapter 21 standby function addition and deletion of cautions in 23.3 rom correction operation and program flow modification of figure 23-2 rom correction operation and program flow chapter 23 rom correction function addition of 24.1.2 (6) hardware break function addition of 24.1.2 (8) mask function addition of 24.1.2 (9) timer function modification of description in 24.1.3 rom security function addition of 24.2 selecting on-chip debug function and port function (including alternate functions) modification of description in table 24-1 emulator connector pin functions (on target system side) modification of figure 24-3 example of recommended emulator connector modification of description in table 24-2 emulator connector pin functions (on target system side) modification of figure 24-6 example of recommended emulator connector addition of 24.4 cautions chapter 24 on- chip debug function (dcu) addition of description in 25.2 (2) off-board programming deletion of description 25.5.2 (2) malfunction of other device modification of figure 25-10 flash memory operation flow deletion of description in table 25-8 flash memory control command chapter 25 flash memory addition of chapter 26 electrical specifications chapter 26 electrical specifications addition of chapter 27 package drawings chapter 27 package drawings modification of description in b.2 instruction set (in alphabetical order) appendix b instruction set list 3rd addition of appendix c revision history appendix c revision history
nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ [asia & oceania] nec electronics (china) co., ltd 7th floor, quantum plaza, no. 27 zhichunlu haidian district, beijing 100083, p.r.china tel: 010-8235-1155 http://www.cn.necel.com/ nec electronics shanghai ltd. room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai p.r. china p.c:200120 tel: 021-5888-5400 http://www.cn.necel.com/ nec electronics hong kong ltd. 12/f., cityplaza 4, 12 taikoo wan road, hong kong tel: 2886-9318 http://www.hk.necel.com/ seoul branch 11f., samik lavied?or bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-2719-2377 nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 http://www.sg.necel.com/ for further information, please contact: g05.12a [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 dsseldorf, germany tel: 0211-65030 http://www.eu.necel.com/ hanover office podbielski strasse 166 b 30177 hanover tel: 0 511 33 40 2-0 munich office werner-eckert-strasse 9 81829 mnchen tel: 0 89 92 10 03-0 stuttgart office industriestrasse 3 70565 stuttgart tel: 0 711 99 01 0-0 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133 succursale fran?aise 9, rue paul dautier, b.p. 52180 78142 velizy-villacoublay cdex france tel: 01-3067-5800 sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 tyskland filial t?by centrum entrance s (7th floor) 18322 t?by, sweden tel: 08 638 72 00 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands limburglaan 5 5616 hr eindhoven the netherlands tel: 040 265 40 10


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